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MPC85xx BA bits not set for 3-bit bank address DIMM

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The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).

Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
This commit is contained in:
Andy Fleming 2007-08-13 14:49:59 -05:00 committed by Andrew Fleming-AFLEMING
parent 6c543597bb
commit 39980c610c
1 changed files with 6 additions and 1 deletions
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7
cpu/mpc85xx/spd_sdram.c
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@ -176,7 +176,7 @@ spd_sdram(void)
spd_eeprom_t spd; spd_eeprom_t spd;
unsigned int n_ranks; unsigned int n_ranks;
unsigned int rank_density; unsigned int rank_density;
unsigned int odt_rd_cfg, odt_wr_cfg; unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
unsigned int odt_cfg, mode_odt_enable; unsigned int odt_cfg, mode_odt_enable;
unsigned int refresh_clk; unsigned int refresh_clk;
#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
@ -341,9 +341,14 @@ spd_sdram(void)
#endif #endif
} }
ba_bits = 0;
if (spd.nbanks == 0x8)
ba_bits = 1;
ddr->cs0_config = ( 1 << 31 ddr->cs0_config = ( 1 << 31
| (odt_rd_cfg << 20) | (odt_rd_cfg << 20)
| (odt_wr_cfg << 16) | (odt_wr_cfg << 16)
| (ba_bits << 14)
| (spd.nrow_addr - 12) << 8 | (spd.nrow_addr - 12) << 8
| (spd.ncol_addr - 8) ); | (spd.ncol_addr - 8) );
debug("\n"); debug("\n");