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arm: Move check_cache_range() into a common place

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This code is common, so move it into a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Simon Glass 2016-06-19 19:43:01 -06:00 committed by Tom Rini
parent ba169d981f
commit 397b5697ad
5 changed files with 24 additions and 51 deletions
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17
arch/arm/cpu/arm11/cpu.c
View file

@ -69,23 +69,6 @@ void flush_dcache_all(void)
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
} }
static int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (!ok)
debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
start, stop);
return ok;
}
void invalidate_dcache_range(unsigned long start, unsigned long stop) void invalidate_dcache_range(unsigned long start, unsigned long stop)
{ {
if (!check_cache_range(start, stop)) if (!check_cache_range(start, stop))

17
arch/arm/cpu/arm926ejs/cache.c
View file

@ -29,23 +29,6 @@ void flush_dcache_all(void)
); );
} }
static int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (!ok)
debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
start, stop);
return ok;
}
void invalidate_dcache_range(unsigned long start, unsigned long stop) void invalidate_dcache_range(unsigned long start, unsigned long stop)
{ {
if (!check_cache_range(start, stop)) if (!check_cache_range(start, stop))

17
arch/arm/cpu/armv7/cache_v7.c
View file

@ -19,23 +19,6 @@
void v7_flush_dcache_all(void); void v7_flush_dcache_all(void);
void v7_invalidate_dcache_all(void); void v7_invalidate_dcache_all(void);
static int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (!ok)
debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
start, stop);
return ok;
}
static u32 get_ccsidr(void) static u32 get_ccsidr(void)
{ {
u32 ccsidr; u32 ccsidr;

2
arch/arm/include/asm/cache.h
View file

@ -29,6 +29,8 @@ static inline void invalidate_l2_cache(void)
} }
#endif #endif
int check_cache_range(unsigned long start, unsigned long stop);
void l2_cache_enable(void); void l2_cache_enable(void);
void l2_cache_disable(void); void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option); void set_section_dcache(int section, enum dcache_option option);

22
arch/arm/lib/cache.c
View file

@ -10,6 +10,10 @@
#include <common.h> #include <common.h>
#include <malloc.h> #include <malloc.h>
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
/* /*
* Flush range from all levels of d-cache/unified-cache. * Flush range from all levels of d-cache/unified-cache.
* Affects the range [start, start + size - 1]. * Affects the range [start, start + size - 1].
@ -46,6 +50,24 @@ __weak void flush_dcache_range(unsigned long start, unsigned long stop)
/* An empty stub, real implementation should be in platform code */ /* An empty stub, real implementation should be in platform code */
} }
int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
ok = 0;
if (!ok) {
debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
start, stop);
}
return ok;
}
#ifdef CONFIG_SYS_NONCACHED_MEMORY #ifdef CONFIG_SYS_NONCACHED_MEMORY
/* /*
* Reserve one MMU section worth of address space below the malloc() area that * Reserve one MMU section worth of address space below the malloc() area that