mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-14 13:57:00 +00:00
+ Fix compilation error for CI when enabling RTL8169 driver + Fix compilation error for pci_mmc.c by adding acpi_table header file + Support video console and usb keyboard on RISC-V QEMU virt machine + Support StarFive JH7110 PCIe driver + Enable PCI on Unmatched board
This commit is contained in:
commit
38dedebc54
20 changed files with 755 additions and 64 deletions
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@ -7,6 +7,7 @@
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#include "jh7110.dtsi"
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#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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serial0 = &uart0;
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@ -308,6 +309,16 @@
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};
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};
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&pcie0 {
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reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
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status = "disabled";
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};
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&pcie1 {
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reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&syscrg {
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assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
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<&syscrg JH7110_SYSCLK_BUS_ROOT>,
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@ -648,5 +648,79 @@
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gpio-controller;
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#gpio-cells = <2>;
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};
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pcie0: pcie@2b000000 {
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compatible = "starfive,jh7110-pcie";
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reg = <0x0 0x2b000000 0x0 0x1000000
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0x9 0x40000000 0x0 0x10000000>;
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reg-names = "reg", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
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<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
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interrupts = <56>;
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interrupt-parent = <&plic>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
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<0x0 0x0 0x0 0x2 &plic 0x2>,
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<0x0 0x0 0x0 0x3 &plic 0x3>,
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<0x0 0x0 0x0 0x4 &plic 0x4>;
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msi-parent = <&plic>;
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device_type = "pci";
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starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
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bus-range = <0x0 0xff>;
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clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
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<&stgcrg JH7110_STGCLK_PCIE0_TL>,
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<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
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<&stgcrg JH7110_STGCLK_PCIE0_APB>;
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clock-names = "noc", "tl", "axi", "apb";
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resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
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<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
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<&stgcrg JH7110_STGRST_PCIE0_SLV>,
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<&stgcrg JH7110_STGRST_PCIE0_BRG>,
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<&stgcrg JH7110_STGRST_PCIE0_CORE>,
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<&stgcrg JH7110_STGRST_PCIE0_APB>;
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reset-names = "mst0", "slv0", "slv", "brg",
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"core", "apb";
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status = "disabled";
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};
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pcie1: pcie@2c000000 {
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compatible = "starfive,jh7110-pcie";
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reg = <0x0 0x2c000000 0x0 0x1000000
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0x9 0xc0000000 0x0 0x10000000>;
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reg-names = "reg", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
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<0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
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interrupts = <57>;
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interrupt-parent = <&plic>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
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<0x0 0x0 0x0 0x2 &plic 0x2>,
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<0x0 0x0 0x0 0x3 &plic 0x3>,
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<0x0 0x0 0x0 0x4 &plic 0x4>;
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msi-parent = <&plic>;
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device_type = "pci";
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starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
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bus-range = <0x0 0xff>;
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clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
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<&stgcrg JH7110_STGCLK_PCIE1_TL>,
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<&stgcrg JH7110_STGCLK_PCIE1_AXI>,
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<&stgcrg JH7110_STGCLK_PCIE1_APB>;
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clock-names = "noc", "tl", "axi", "apb";
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resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
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<&stgcrg JH7110_STGRST_PCIE1_SLV0>,
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<&stgcrg JH7110_STGRST_PCIE1_SLV>,
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<&stgcrg JH7110_STGRST_PCIE1_BRG>,
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<&stgcrg JH7110_STGRST_PCIE1_CORE>,
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<&stgcrg JH7110_STGRST_PCIE1_APB>;
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reset-names = "mst0", "slv0", "slv", "brg",
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"core", "apb";
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status = "disabled";
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};
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};
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};
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11
arch/riscv/include/asm/acpi_table.h
Normal file
11
arch/riscv/include/asm/acpi_table.h
Normal file
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __ASM_ACPI_TABLE_H__
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#define __ASM_ACPI_TABLE_H__
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/*
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* This file is needed by some drivers.
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* We will fill it when adding ACPI support for RISC-V.
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*/
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#endif /* __ASM_ACPI_TABLE_H__ */
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@ -25,6 +25,10 @@ config SPL_OPENSBI_LOAD_ADDR
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hex
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default 0x80100000
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config PRE_CON_BUF_ADDR
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hex
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default 0x81000000
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select GENERIC_RISCV
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@ -68,5 +72,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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imply MTD_NOR_FLASH
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imply CFI_FLASH
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imply OF_HAS_PRIOR_STAGE
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imply VIDEO
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imply VIDEO_BOCHS
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imply SYS_WHITE_ON_BLACK
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imply PRE_CONSOLE_BUFFER
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imply USB
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imply USB_XHCI_HCD
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imply USB_XHCI_PCI
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imply USB_KEYBOARD
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imply CMD_USB
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endif
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@ -12,6 +12,7 @@
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#include <log.h>
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#include <spl.h>
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#include <init.h>
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#include <usb.h>
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#include <virtio_types.h>
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#include <virtio.h>
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@ -41,29 +42,9 @@ int board_init(void)
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int board_late_init(void)
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{
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ulong kernel_start;
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ofnode chosen_node;
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int ret;
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chosen_node = ofnode_path("/chosen");
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if (!ofnode_valid(chosen_node)) {
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debug("No chosen node found, can't get kernel start address\n");
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return 0;
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}
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#ifdef CONFIG_ARCH_RV64I
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ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
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(u64 *)&kernel_start);
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#else
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ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
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(u32 *)&kernel_start);
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#endif
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if (ret) {
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debug("Can't find kernel start address in device tree\n");
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return 0;
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}
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env_set_hex("kernel_start", kernel_start);
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/* start usb so that usb keyboard can be used as input device */
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if (CONFIG_IS_ENABLED(USB_KEYBOARD))
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usb_init();
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return 0;
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}
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@ -226,7 +226,7 @@ config CONSOLE_FLUSH_SUPPORT
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config CONSOLE_MUX
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bool "Enable console multiplexing"
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default y if VIDEO || VIDEO || LCD
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default y if VIDEO || LCD
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help
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This allows multiple devices to be used for each console 'file'.
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For example, stdout can be set to go to serial and video.
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@ -1010,29 +1010,41 @@ int console_init_f(void)
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return 0;
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}
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void stdio_print_current_devices(void)
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static void stdio_print_current_devices(void)
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{
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char *stdinname, *stdoutname, *stderrname;
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if (CONFIG_IS_ENABLED(CONSOLE_MUX) &&
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CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)) {
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/* stdin stdout and stderr are in environment */
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stdinname = env_get("stdin");
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stdoutname = env_get("stdout");
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stderrname = env_get("stderr");
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stdinname = stdinname ? : "No input devices available!";
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stdoutname = stdoutname ? : "No output devices available!";
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stderrname = stderrname ? : "No error devices available!";
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} else {
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stdinname = stdio_devices[stdin] ?
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stdio_devices[stdin]->name :
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"No input devices available!";
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stdoutname = stdio_devices[stdout] ?
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stdio_devices[stdout]->name :
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"No output devices available!";
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stderrname = stdio_devices[stderr] ?
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stdio_devices[stderr]->name :
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"No error devices available!";
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}
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/* Print information */
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puts("In: ");
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if (stdio_devices[stdin] == NULL) {
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puts("No input devices available!\n");
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} else {
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printf ("%s\n", stdio_devices[stdin]->name);
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}
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printf("%s\n", stdinname);
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puts("Out: ");
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if (stdio_devices[stdout] == NULL) {
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puts("No output devices available!\n");
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} else {
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printf ("%s\n", stdio_devices[stdout]->name);
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}
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printf("%s\n", stdoutname);
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puts("Err: ");
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if (stdio_devices[stderr] == NULL) {
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puts("No error devices available!\n");
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} else {
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printf ("%s\n", stdio_devices[stderr]->name);
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}
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printf("%s\n", stderrname);
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}
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#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)
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@ -31,6 +31,7 @@ CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_ID_EEPROM=y
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CONFIG_PCI_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x100000
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CONFIG_SPL_BSS_START_ADDR=0x85000000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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|
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@ -19,6 +19,8 @@ CONFIG_SPL=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SYS_LOAD_ADDR=0x82000000
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CONFIG_SYS_PCI_64BIT=y
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CONFIG_PCI=y
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CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
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CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
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CONFIG_ARCH_RV64I=y
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@ -62,6 +64,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_TFTPPUT=y
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CONFIG_OF_BOARD=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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|
@ -92,6 +95,11 @@ CONFIG_DWC_ETH_QOS=y
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CONFIG_DWC_ETH_QOS_STARFIVE=y
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CONFIG_RGMII=y
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CONFIG_RMII=y
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CONFIG_RTL8169=y
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CONFIG_NVME_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCI_REGION_MULTI_ENTRY=y
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CONFIG_PCIE_STARFIVE_JH7110=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_SPL_PINCTRL=y
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|
|
|
@ -133,6 +133,16 @@ An attached disk can be emulated in RISC-V virt machine by adding::
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|||
|
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You will have to run 'scsi scan' to use it.
|
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|
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A video console can be emulated in RISC-V virt machine by removing "-nographic"
|
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and adding::
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|
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-serial stdio -device VGA
|
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|
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In addition, a usb keyboard can be attached to an emulated xHCI controller in
|
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RISC-V virt machine as an option of input devices by adding::
|
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|
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-device qemu-xhci,id=xhci -device usb-kbd,bus=xhci.0
|
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|
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Running with KVM
|
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----------------
|
||||
|
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|
|
|
@ -231,6 +231,15 @@ config SYS_I2C_DW
|
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controller is used in various SoCs, e.g. the ST SPEAr, Altera
|
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SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
|
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|
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config SYS_I2C_DW_PCI
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bool "Designware PCI I2C Controller"
|
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depends on SYS_I2C_DW && PCI && ACPIGEN
|
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default y
|
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help
|
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Say yes here to select the Designware PCI I2C Host Controller.
|
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This PCI I2C controller is the base on Desigware I2C host
|
||||
controller.
|
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|
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config SYS_I2C_AST2600
|
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bool "AST2600 I2C Controller"
|
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depends on DM_I2C && ARCH_ASPEED
|
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|
|
|
@ -18,9 +18,7 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
|
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obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
|
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
|
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obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
|
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ifdef CONFIG_PCI
|
||||
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
|
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endif
|
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obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o
|
||||
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
|
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obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
|
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obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
|
||||
|
|
|
@ -96,12 +96,12 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
|
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#define TX_TIMEOUT (6*HZ)
|
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|
||||
/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
|
||||
#define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
|
||||
#define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
|
||||
#define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
|
||||
#define RTL_R8(reg) readb(ioaddr + (reg))
|
||||
#define RTL_R16(reg) readw(ioaddr + (reg))
|
||||
#define RTL_R32(reg) readl(ioaddr + (reg))
|
||||
#define RTL_W8(reg, val8) writeb((val8), (void *)(ioaddr + (reg)))
|
||||
#define RTL_W16(reg, val16) writew((val16), (void *)(ioaddr + (reg)))
|
||||
#define RTL_W32(reg, val32) writel((val32), (void *)(ioaddr + (reg)))
|
||||
#define RTL_R8(reg) readb((void *)(ioaddr + (reg)))
|
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#define RTL_R16(reg) readw((void *)(ioaddr + (reg)))
|
||||
#define RTL_R32(reg) readl((void *)(ioaddr + (reg)))
|
||||
|
||||
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
|
||||
(pci_addr_t)(unsigned long)a)
|
||||
|
@ -311,10 +311,12 @@ static unsigned char rxdata[RX_BUF_LEN];
|
|||
*
|
||||
* This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
|
||||
* the driver to allocate descriptors from a pool of non-cached memory.
|
||||
*
|
||||
* Hardware maintain D-cache coherency in RISC-V architecture.
|
||||
*/
|
||||
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
|
||||
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
|
||||
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
|
||||
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && !defined(CONFIG_RISCV)
|
||||
#warning cache-line size is larger than descriptor size
|
||||
#endif
|
||||
#endif
|
||||
|
@ -351,10 +353,11 @@ static const unsigned int rtl8169_rx_config =
|
|||
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
|
||||
|
||||
static struct pci_device_id supported[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -1049,8 +1052,9 @@ static int rtl8169_eth_probe(struct udevice *dev)
|
|||
int ret;
|
||||
|
||||
switch (pplat->device) {
|
||||
case 0x8168:
|
||||
case 0x8125:
|
||||
case 0x8161:
|
||||
case 0x8168:
|
||||
region = 2;
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -393,4 +393,17 @@ config PCIE_XILINX_NWL
|
|||
Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
|
||||
controller as Root Port.
|
||||
|
||||
config PCIE_PLDA_COMMON
|
||||
bool
|
||||
|
||||
config PCIE_STARFIVE_JH7110
|
||||
bool "Enable Starfive JH7110 PCIe driver"
|
||||
select PCIE_PLDA_COMMON
|
||||
imply STARFIVE_JH7110
|
||||
imply CLK_JH7110
|
||||
imply RESET_JH7110
|
||||
help
|
||||
Say Y here if you want to enable PLDA XpressRich PCIe controller
|
||||
support on StarFive JH7110 SoC.
|
||||
|
||||
endif
|
||||
|
|
|
@ -50,3 +50,5 @@ obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
|
|||
obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
|
||||
obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
|
||||
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
|
||||
obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
|
||||
obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
|
||||
|
|
116
drivers/pci/pcie_plda_common.c
Normal file
116
drivers/pci/pcie_plda_common.c
Normal file
|
@ -0,0 +1,116 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* PLDA XpressRich PCIe host controller common functions.
|
||||
*
|
||||
* Copyright (C) 2023 StarFive Technology Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include "pcie_plda_common.h"
|
||||
|
||||
static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
|
||||
{
|
||||
/*
|
||||
* Single device limitation.
|
||||
* PCIe controller contain HW issue that secondary bus of
|
||||
* host bridge emumerate duplicate devices.
|
||||
* Only can access device 0 in secondary bus.
|
||||
*/
|
||||
if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
|
||||
uint offset, void **paddr)
|
||||
{
|
||||
struct pcie_plda *priv = dev_get_priv(udev);
|
||||
int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
|
||||
PCI_FUNC(bdf), offset);
|
||||
|
||||
if (!plda_pcie_addr_valid(priv, bdf))
|
||||
return -ENODEV;
|
||||
|
||||
*paddr = (void *)(priv->cfg_base + where);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
|
||||
uint offset, ulong *valuep,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
|
||||
bdf, offset, valuep, size);
|
||||
}
|
||||
|
||||
int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
|
||||
uint offset, ulong value,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
struct pcie_plda *priv = dev_get_priv(udev);
|
||||
int ret;
|
||||
|
||||
ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
|
||||
bdf, offset, value, size);
|
||||
|
||||
/* record secondary bus number */
|
||||
if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
|
||||
PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
|
||||
(offset == PCI_SECONDARY_BUS ||
|
||||
(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
|
||||
priv->sec_busno =
|
||||
((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff;
|
||||
debug("Secondary bus number was changed to %d\n",
|
||||
priv->sec_busno);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
|
||||
phys_addr_t trsl_addr, phys_size_t window_size,
|
||||
int trsl_param)
|
||||
{
|
||||
void __iomem *base =
|
||||
plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
|
||||
|
||||
/* Support AXI4 Slave 0 Address Translation Tables 0-7. */
|
||||
if (plda->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) {
|
||||
dev_err(plda->dev, "ATR table number %d exceeds max num\n",
|
||||
plda->atr_table_num);
|
||||
return -EINVAL;
|
||||
}
|
||||
base += XR3PCI_ATR_TABLE_OFFSET * plda->atr_table_num;
|
||||
plda->atr_table_num++;
|
||||
|
||||
/*
|
||||
* X3PCI_ATR_SRC_ADDR_LOW:
|
||||
* - bit 0: enable entry,
|
||||
* - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
|
||||
* - bits 7-11: reserved
|
||||
* - bits 12-31: start of source address
|
||||
*/
|
||||
writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
|
||||
(fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
|
||||
base + XR3PCI_ATR_SRC_ADDR_LOW);
|
||||
writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
|
||||
writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
|
||||
base + XR3PCI_ATR_TRSL_ADDR_LOW);
|
||||
writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
|
||||
writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
|
||||
|
||||
dev_dbg(plda->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
|
||||
src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
|
||||
trsl_addr, (u64)window_size, trsl_param);
|
||||
return 0;
|
||||
}
|
118
drivers/pci/pcie_plda_common.h
Normal file
118
drivers/pci/pcie_plda_common.h
Normal file
|
@ -0,0 +1,118 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2023 StarFive Technology Co., Ltd.
|
||||
* Author: Minda Chen <minda.chen@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PCIE_PLDA_COMMON_H
|
||||
#define PCIE_PLDA_COMMON_H
|
||||
|
||||
#define GEN_SETTINGS 0x80
|
||||
#define PCIE_PCI_IDS 0x9C
|
||||
#define PCIE_WINROM 0xFC
|
||||
#define PMSG_SUPPORT_RX 0x3F0
|
||||
#define PCI_MISC 0xB4
|
||||
|
||||
#define PLDA_EP_ENABLE 0
|
||||
#define PLDA_RP_ENABLE 1
|
||||
|
||||
#define IDS_CLASS_CODE_SHIFT 8
|
||||
|
||||
#define PREF_MEM_WIN_64_SUPPORT BIT(3)
|
||||
#define PMSG_LTR_SUPPORT BIT(2)
|
||||
#define PLDA_FUNCTION_DIS BIT(15)
|
||||
#define PLDA_FUNC_NUM 4
|
||||
#define PLDA_PHY_FUNC_SHIFT 9
|
||||
|
||||
#define XR3PCI_ATR_AXI4_SLV0 0x800
|
||||
#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
|
||||
#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
|
||||
#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
|
||||
#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
|
||||
#define XR3PCI_ATR_TRSL_PARAM 0x10
|
||||
#define XR3PCI_ATR_TABLE_OFFSET 0x20
|
||||
#define XR3PCI_ATR_MAX_TABLE_NUM 8
|
||||
|
||||
#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
|
||||
#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
|
||||
#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
|
||||
#define XR3PCI_ATR_TRSL_DIR BIT(22)
|
||||
/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
|
||||
#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
|
||||
#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
|
||||
|
||||
/**
|
||||
* struct pcie_plda - PLDA PCIe controller state
|
||||
*
|
||||
* @reg_base: The base address of controller register space
|
||||
* @cfg_base: The base address of configuration space
|
||||
* @cfg_size: The size of configuration space
|
||||
* @sec_busno: Secondary bus number.
|
||||
* @atr_table_num: Total ATR table numbers.
|
||||
*/
|
||||
struct pcie_plda {
|
||||
struct udevice *dev;
|
||||
void __iomem *reg_base;
|
||||
void __iomem *cfg_base;
|
||||
phys_size_t cfg_size;
|
||||
int sec_busno;
|
||||
int atr_table_num;
|
||||
};
|
||||
|
||||
int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
|
||||
uint offset, ulong *valuep,
|
||||
enum pci_size_t size);
|
||||
int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
|
||||
uint offset, ulong value,
|
||||
enum pci_size_t size);
|
||||
int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
|
||||
phys_addr_t trsl_addr, phys_size_t window_size,
|
||||
int trsl_param);
|
||||
|
||||
static inline void plda_pcie_enable_root_port(struct pcie_plda *plda)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = readl(plda->reg_base + GEN_SETTINGS);
|
||||
value |= PLDA_RP_ENABLE;
|
||||
writel(value, plda->reg_base + GEN_SETTINGS);
|
||||
}
|
||||
|
||||
static inline void plda_pcie_set_standard_class(struct pcie_plda *plda)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = readl(plda->reg_base + PCIE_PCI_IDS);
|
||||
value &= 0xff;
|
||||
value |= (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT);
|
||||
writel(value, plda->reg_base + PCIE_PCI_IDS);
|
||||
}
|
||||
|
||||
static inline void plda_pcie_set_pref_win_64bit(struct pcie_plda *plda)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = readl(plda->reg_base + PCIE_WINROM);
|
||||
value |= PREF_MEM_WIN_64_SUPPORT;
|
||||
writel(value, plda->reg_base + PCIE_WINROM);
|
||||
}
|
||||
|
||||
static inline void plda_pcie_disable_ltr(struct pcie_plda *plda)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = readl(plda->reg_base + PMSG_SUPPORT_RX);
|
||||
value &= ~PMSG_LTR_SUPPORT;
|
||||
writel(value, plda->reg_base + PMSG_SUPPORT_RX);
|
||||
}
|
||||
|
||||
static inline void plda_pcie_disable_func(struct pcie_plda *plda)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = readl(plda->reg_base + PCI_MISC);
|
||||
value |= PLDA_FUNCTION_DIS;
|
||||
writel(value, plda->reg_base + PCI_MISC);
|
||||
}
|
||||
#endif
|
317
drivers/pci/pcie_starfive_jh7110.c
Normal file
317
drivers/pci/pcie_starfive_jh7110.c
Normal file
|
@ -0,0 +1,317 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* StarFive PLDA PCIe host controller driver
|
||||
*
|
||||
* Copyright (C) 2023 StarFive Technology Co., Ltd.
|
||||
* Author: Mason Huo <mason.huo@starfivetech.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <power-domain.h>
|
||||
#include <regmap.h>
|
||||
#include <reset.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include "pcie_plda_common.h"
|
||||
|
||||
/* system control */
|
||||
#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
|
||||
#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
|
||||
#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
|
||||
#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
|
||||
#define STG_SYSCON_CLKREQ_MASK BIT(22)
|
||||
#define STG_SYSCON_CKREF_SRC_SHIFT 18
|
||||
#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct starfive_pcie {
|
||||
struct pcie_plda plda;
|
||||
struct clk_bulk clks;
|
||||
struct reset_ctl_bulk rsts;
|
||||
struct gpio_desc reset_gpio;
|
||||
struct regmap *regmap;
|
||||
u32 stg_arfun;
|
||||
u32 stg_awfun;
|
||||
u32 stg_rp_nep;
|
||||
};
|
||||
|
||||
static int starfive_pcie_atr_init(struct starfive_pcie *priv)
|
||||
{
|
||||
struct udevice *ctlr = pci_get_controller(priv->plda.dev);
|
||||
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
||||
int i, ret;
|
||||
|
||||
/*
|
||||
* As the two host bridges in JH7110 soc have the same default
|
||||
* address translation table, this cause the second root port can't
|
||||
* access it's host bridge config space correctly.
|
||||
* To workaround, config the ATR of host bridge config space by SW.
|
||||
*/
|
||||
|
||||
ret = plda_pcie_set_atr_entry(&priv->plda,
|
||||
(phys_addr_t)priv->plda.cfg_base, 0,
|
||||
priv->plda.cfg_size,
|
||||
XR3PCI_ATR_TRSLID_PCIE_CONFIG);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < hose->region_count; i++) {
|
||||
if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
|
||||
continue;
|
||||
|
||||
/* Only support identity mappings. */
|
||||
if (hose->regions[i].bus_start !=
|
||||
hose->regions[i].phys_start)
|
||||
return -EINVAL;
|
||||
|
||||
ret = plda_pcie_set_atr_entry(&priv->plda,
|
||||
hose->regions[i].phys_start,
|
||||
hose->regions[i].bus_start,
|
||||
hose->regions[i].size,
|
||||
XR3PCI_ATR_TRSLID_PCIE_MEMORY);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int starfive_pcie_get_syscon(struct udevice *dev)
|
||||
{
|
||||
struct starfive_pcie *priv = dev_get_priv(dev);
|
||||
struct udevice *syscon;
|
||||
struct ofnode_phandle_args syscfg_phandle;
|
||||
u32 cells[4];
|
||||
int ret;
|
||||
|
||||
/* get corresponding syscon phandle */
|
||||
ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
|
||||
&syscfg_phandle);
|
||||
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
|
||||
&syscon);
|
||||
if (ret) {
|
||||
dev_err(dev, "Unable to find syscon device (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
priv->regmap = syscon_get_regmap(syscon);
|
||||
if (!priv->regmap) {
|
||||
dev_err(dev, "Unable to find regmap\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* get syscon register offset */
|
||||
ret = dev_read_u32_array(dev, "starfive,stg-syscon",
|
||||
cells, ARRAY_SIZE(cells));
|
||||
if (ret) {
|
||||
dev_err(dev, "Get syscon register err %d\n", ret);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
|
||||
cells[1], cells[2], cells[3]);
|
||||
priv->stg_arfun = cells[1];
|
||||
priv->stg_awfun = cells[2];
|
||||
priv->stg_rp_nep = cells[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int starfive_pcie_parse_dt(struct udevice *dev)
|
||||
{
|
||||
struct starfive_pcie *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg");
|
||||
if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "Missing required reg address range\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->plda.cfg_base =
|
||||
(void *)dev_read_addr_size_name(dev,
|
||||
"config",
|
||||
&priv->plda.cfg_size);
|
||||
if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "Missing required config address range");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = starfive_pcie_get_syscon(dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get syscon: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_get_bulk(dev, &priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get reset: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_bulk(dev, &priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
|
||||
GPIOD_IS_OUT);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get reset-gpio: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!dm_gpio_is_valid(&priv->reset_gpio)) {
|
||||
dev_err(dev, "reset-gpio is not valid\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int starfive_pcie_init_port(struct udevice *dev)
|
||||
{
|
||||
int ret, i;
|
||||
struct starfive_pcie *priv = dev_get_priv(dev);
|
||||
struct pcie_plda *plda = &priv->plda;
|
||||
|
||||
ret = clk_enable_bulk(&priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_deassert_bulk(&priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
|
||||
goto err_deassert_clk;
|
||||
}
|
||||
|
||||
dm_gpio_set_value(&priv->reset_gpio, 1);
|
||||
/* Disable physical functions except #0 */
|
||||
for (i = 1; i < PLDA_FUNC_NUM; i++) {
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_arfun,
|
||||
STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
|
||||
(i << PLDA_PHY_FUNC_SHIFT) <<
|
||||
STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
|
||||
i << PLDA_PHY_FUNC_SHIFT);
|
||||
|
||||
plda_pcie_disable_func(plda);
|
||||
}
|
||||
|
||||
/* Disable physical functions */
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_arfun,
|
||||
STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
|
||||
0);
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
|
||||
0);
|
||||
|
||||
plda_pcie_enable_root_port(plda);
|
||||
|
||||
/* PCIe PCI Standard Configuration Identification Settings. */
|
||||
plda_pcie_set_standard_class(plda);
|
||||
|
||||
/*
|
||||
* The LTR message forwarding of PCIe Message Reception was set by core
|
||||
* as default, but the forward id & addr are also need to be reset.
|
||||
* If we do not disable LTR message forwarding here, or set a legal
|
||||
* forwarding address, the kernel will get stuck after this driver probe.
|
||||
* To workaround, disable the LTR message forwarding support on
|
||||
* PCIe Message Reception.
|
||||
*/
|
||||
plda_pcie_disable_ltr(plda);
|
||||
|
||||
/* Prefetchable memory window 64-bit addressing support */
|
||||
plda_pcie_set_pref_win_64bit(plda);
|
||||
starfive_pcie_atr_init(priv);
|
||||
|
||||
dm_gpio_set_value(&priv->reset_gpio, 0);
|
||||
/* Ensure that PERST in default at least 300 ms */
|
||||
mdelay(300);
|
||||
|
||||
return 0;
|
||||
|
||||
err_deassert_clk:
|
||||
clk_disable_bulk(&priv->clks);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int starfive_pcie_probe(struct udevice *dev)
|
||||
{
|
||||
struct starfive_pcie *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
priv->plda.atr_table_num = 0;
|
||||
priv->plda.dev = dev;
|
||||
|
||||
ret = starfive_pcie_parse_dt(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_rp_nep,
|
||||
STG_SYSCON_K_RP_NEP_MASK,
|
||||
STG_SYSCON_K_RP_NEP_MASK);
|
||||
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_CKREF_SRC_MASK,
|
||||
2 << STG_SYSCON_CKREF_SRC_SHIFT);
|
||||
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_CLKREQ_MASK,
|
||||
STG_SYSCON_CLKREQ_MASK);
|
||||
|
||||
ret = starfive_pcie_init_port(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_err(dev, "Starfive PCIe bus probed.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops starfive_pcie_ops = {
|
||||
.read_config = plda_pcie_config_read,
|
||||
.write_config = plda_pcie_config_write,
|
||||
};
|
||||
|
||||
static const struct udevice_id starfive_pcie_ids[] = {
|
||||
{ .compatible = "starfive,jh7110-pcie" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(starfive_pcie_drv) = {
|
||||
.name = "starfive_7110_pcie",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = starfive_pcie_ids,
|
||||
.ops = &starfive_pcie_ops,
|
||||
.probe = starfive_pcie_probe,
|
||||
.priv_auto = sizeof(struct starfive_pcie),
|
||||
};
|
|
@ -17,24 +17,19 @@
|
|||
|
||||
/* Environment options */
|
||||
|
||||
#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(QEMU, qemu, na) \
|
||||
func(VIRTIO, virtio, 0) \
|
||||
func(SCSI, scsi, 0) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#define BOOTENV_DEV_QEMU(devtypeu, devtypel, instance) \
|
||||
"bootcmd_qemu=" \
|
||||
"if env exists kernel_start; then " \
|
||||
"bootm ${kernel_start} - ${fdtcontroladdr};" \
|
||||
"fi;\0"
|
||||
|
||||
#define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \
|
||||
"qemu "
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
CFG_STD_DEVICES_SETTINGS \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_addr_r=0x84000000\0" \
|
||||
|
|
|
@ -84,8 +84,6 @@ int stdio_init_tables(void);
|
|||
*/
|
||||
int stdio_add_devices(void);
|
||||
|
||||
void stdio_print_current_devices(void);
|
||||
|
||||
/**
|
||||
* stdio_deregister_dev() - deregister the device "devname".
|
||||
*
|
||||
|
|
Loading…
Add table
Reference in a new issue