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pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
a22eba36a9
commit
37fb54b6e6
1 changed files with 532 additions and 216 deletions
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@ -20,13 +20,23 @@
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#include "sh_pfc.h"
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_9(0, fn, sfx), \
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PORT_GP_32(1, fn, sfx), \
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PORT_GP_32(2, fn, sfx), \
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PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_32(4, fn, sfx), \
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PORT_GP_21(5, fn, sfx), \
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PORT_GP_14(6, fn, sfx)
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PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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#define CPU_ALL_NOGP(fn) \
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PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
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PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
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/*
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* F_() : just information
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@ -933,8 +943,17 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
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};
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/*
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* Pins not associated with a GPIO port.
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*/
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enum {
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GP_ASSIGN_LAST(),
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NOGP_ALL(),
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};
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static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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PINMUX_NOGP_ALL(),
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};
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/* - AUDIO CLOCK ------------------------------------------------------------- */
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@ -1240,31 +1259,23 @@ static const unsigned int i2c3_b_mux[] = {
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SCL3_B_MARK, SDA3_B_MARK,
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};
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/* - MLB+ ------------------------------------------------------------------- */
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static const unsigned int mlb_3pin_pins[] = {
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RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7),
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};
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static const unsigned int mlb_3pin_mux[] = {
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MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
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};
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/* - MMC ------------------------------------------------------------------- */
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static const unsigned int mmc_data1_pins[] = {
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/* D0 */
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RCAR_GP_PIN(3, 2),
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};
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static const unsigned int mmc_data1_mux[] = {
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MMC_D0_MARK,
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};
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static const unsigned int mmc_data4_pins[] = {
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/* D[0:3] */
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RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
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RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
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};
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static const unsigned int mmc_data4_mux[] = {
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MMC_D0_MARK, MMC_D1_MARK,
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MMC_D2_MARK, MMC_D3_MARK,
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};
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static const unsigned int mmc_data8_pins[] = {
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static const unsigned int mmc_data_pins[] = {
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/* D[0:7] */
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RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
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RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
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RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
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RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
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};
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static const unsigned int mmc_data8_mux[] = {
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static const unsigned int mmc_data_mux[] = {
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MMC_D0_MARK, MMC_D1_MARK,
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MMC_D2_MARK, MMC_D3_MARK,
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MMC_D4_MARK, MMC_D5_MARK,
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@ -1673,6 +1684,68 @@ static const unsigned int pwm3_c_mux[] = {
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PWM3_C_MARK,
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};
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/* - QSPI0 ------------------------------------------------------------------ */
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static const unsigned int qspi0_ctrl_pins[] = {
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/* QSPI0_SPCLK, QSPI0_SSL */
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RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
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};
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static const unsigned int qspi0_ctrl_mux[] = {
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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};
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/* - QSPI1 ------------------------------------------------------------------ */
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static const unsigned int qspi1_ctrl_pins[] = {
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/* QSPI1_SPCLK, QSPI1_SSL */
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RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11),
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};
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static const unsigned int qspi1_ctrl_mux[] = {
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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};
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/* - RPC -------------------------------------------------------------------- */
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static const unsigned int rpc_clk_pins[] = {
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/* Octal-SPI flash: C/SCLK */
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/* HyperFlash: CK, CK# */
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RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6),
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};
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static const unsigned int rpc_clk_mux[] = {
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QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
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};
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static const unsigned int rpc_ctrl_pins[] = {
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/* Octal-SPI flash: S#/CS, DQS */
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/* HyperFlash: CS#, RDS */
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RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
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};
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static const unsigned int rpc_ctrl_mux[] = {
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QSPI0_SSL_MARK, QSPI1_SSL_MARK,
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};
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static const unsigned int rpc_data_pins[] = {
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/* DQ[0:7] */
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RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
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RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
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RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8),
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RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10),
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};
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static const unsigned int rpc_data_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK,
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK,
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};
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static const unsigned int rpc_reset_pins[] = {
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/* RPC_RESET# */
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RCAR_GP_PIN(6, 12),
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};
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static const unsigned int rpc_reset_mux[] = {
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RPC_RESET_N_MARK,
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};
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static const unsigned int rpc_int_pins[] = {
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/* RPC_INT# */
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RCAR_GP_PIN(6, 13),
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};
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static const unsigned int rpc_int_mux[] = {
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RPC_INT_N_MARK,
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};
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_a_pins[] = {
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/* RX, TX */
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@ -1933,8 +2006,7 @@ static const unsigned int vin4_data18_mux[] = {
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VI4_DATA20_MARK, VI4_DATA21_MARK,
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VI4_DATA22_MARK, VI4_DATA23_MARK,
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};
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static const union vin_data vin4_data_pins = {
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.data24 = {
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static const unsigned int vin4_data_pins[] = {
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RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
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RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
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RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
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@ -1947,10 +2019,8 @@ static const union vin_data vin4_data_pins = {
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RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
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RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
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RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
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},
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};
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static const union vin_data vin4_data_mux = {
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.data24 = {
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static const unsigned int vin4_data_mux[] = {
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VI4_DATA0_MARK, VI4_DATA1_MARK,
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VI4_DATA2_MARK, VI4_DATA3_MARK,
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VI4_DATA4_MARK, VI4_DATA5_MARK,
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@ -1963,7 +2033,6 @@ static const union vin_data vin4_data_mux = {
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VI4_DATA18_MARK, VI4_DATA19_MARK,
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VI4_DATA20_MARK, VI4_DATA21_MARK,
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VI4_DATA22_MARK, VI4_DATA23_MARK,
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},
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};
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static const unsigned int vin4_sync_pins[] = {
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/* HSYNC#, VSYNC# */
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@ -2032,9 +2101,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(i2c2_b),
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SH_PFC_PIN_GROUP(i2c3_a),
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SH_PFC_PIN_GROUP(i2c3_b),
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SH_PFC_PIN_GROUP(mmc_data1),
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SH_PFC_PIN_GROUP(mmc_data4),
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SH_PFC_PIN_GROUP(mmc_data8),
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SH_PFC_PIN_GROUP(mlb_3pin),
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BUS_DATA_PIN_GROUP(mmc_data, 1),
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BUS_DATA_PIN_GROUP(mmc_data, 4),
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BUS_DATA_PIN_GROUP(mmc_data, 8),
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SH_PFC_PIN_GROUP(mmc_ctrl),
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SH_PFC_PIN_GROUP(msiof0_clk),
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SH_PFC_PIN_GROUP(msiof0_sync),
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@ -2079,6 +2149,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(pwm3_a),
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SH_PFC_PIN_GROUP(pwm3_b),
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SH_PFC_PIN_GROUP(pwm3_c),
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
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SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
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SH_PFC_PIN_GROUP(qspi1_ctrl),
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SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
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SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
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BUS_DATA_PIN_GROUP(rpc_clk, 1),
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BUS_DATA_PIN_GROUP(rpc_clk, 2),
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SH_PFC_PIN_GROUP(rpc_ctrl),
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SH_PFC_PIN_GROUP(rpc_data),
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SH_PFC_PIN_GROUP(rpc_reset),
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SH_PFC_PIN_GROUP(rpc_int),
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SH_PFC_PIN_GROUP(scif0_data_a),
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SH_PFC_PIN_GROUP(scif0_clk_a),
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SH_PFC_PIN_GROUP(scif0_data_b),
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@ -2111,13 +2193,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(ssi4_ctrl_b),
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SH_PFC_PIN_GROUP(ssi4_data_b),
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SH_PFC_PIN_GROUP(usb0),
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VIN_DATA_PIN_GROUP(vin4_data, 8),
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VIN_DATA_PIN_GROUP(vin4_data, 10),
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VIN_DATA_PIN_GROUP(vin4_data, 12),
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VIN_DATA_PIN_GROUP(vin4_data, 16),
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BUS_DATA_PIN_GROUP(vin4_data, 8),
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BUS_DATA_PIN_GROUP(vin4_data, 10),
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BUS_DATA_PIN_GROUP(vin4_data, 12),
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BUS_DATA_PIN_GROUP(vin4_data, 16),
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SH_PFC_PIN_GROUP(vin4_data18),
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VIN_DATA_PIN_GROUP(vin4_data, 20),
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VIN_DATA_PIN_GROUP(vin4_data, 24),
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BUS_DATA_PIN_GROUP(vin4_data, 20),
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BUS_DATA_PIN_GROUP(vin4_data, 24),
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SH_PFC_PIN_GROUP(vin4_sync),
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SH_PFC_PIN_GROUP(vin4_field),
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SH_PFC_PIN_GROUP(vin4_clkenb),
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@ -2193,6 +2275,10 @@ static const char * const i2c3_groups[] = {
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"i2c3_b",
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};
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static const char * const mlb_3pin_groups[] = {
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"mlb_3pin",
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};
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static const char * const mmc_groups[] = {
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"mmc_data1",
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"mmc_data4",
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@ -2200,6 +2286,49 @@ static const char * const mmc_groups[] = {
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"mmc_ctrl",
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};
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static const char * const msiof0_groups[] = {
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"msiof0_clk",
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"msiof0_sync",
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"msiof0_ss1",
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"msiof0_ss2",
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"msiof0_txd",
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"msiof0_rxd",
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};
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static const char * const msiof1_groups[] = {
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"msiof1_clk",
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"msiof1_sync",
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"msiof1_ss1",
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"msiof1_ss2",
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"msiof1_txd",
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"msiof1_rxd",
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};
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static const char * const msiof2_groups[] = {
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"msiof2_clk",
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"msiof2_sync_a",
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"msiof2_sync_b",
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"msiof2_ss1",
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"msiof2_ss2",
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"msiof2_txd",
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"msiof2_rxd",
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};
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static const char * const msiof3_groups[] = {
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"msiof3_clk_a",
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"msiof3_sync_a",
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"msiof3_ss1_a",
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"msiof3_ss2_a",
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"msiof3_txd_a",
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"msiof3_rxd_a",
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"msiof3_clk_b",
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"msiof3_sync_b",
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"msiof3_ss1_b",
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"msiof3_ss2_b",
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"msiof3_txd_b",
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"msiof3_rxd_b",
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};
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static const char * const pwm0_groups[] = {
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"pwm0_a",
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"pwm0_b",
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@ -2224,6 +2353,27 @@ static const char * const pwm3_groups[] = {
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"pwm3_c",
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};
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static const char * const qspi0_groups[] = {
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"qspi0_ctrl",
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"qspi0_data2",
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"qspi0_data4",
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};
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static const char * const qspi1_groups[] = {
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"qspi1_ctrl",
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"qspi1_data2",
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"qspi1_data4",
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};
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static const char * const rpc_groups[] = {
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"rpc_clk1",
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"rpc_clk2",
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"rpc_ctrl",
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"rpc_data",
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"rpc_reset",
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"rpc_int",
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};
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static const char * const scif0_groups[] = {
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"scif0_data_a",
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"scif0_clk_a",
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@ -2297,49 +2447,6 @@ static const char * const vin4_groups[] = {
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"vin4_clk",
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};
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static const char * const msiof0_groups[] = {
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"msiof0_clk",
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"msiof0_sync",
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"msiof0_ss1",
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"msiof0_ss2",
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"msiof0_txd",
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"msiof0_rxd",
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};
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static const char * const msiof1_groups[] = {
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"msiof1_clk",
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"msiof1_sync",
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"msiof1_ss1",
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"msiof1_ss2",
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"msiof1_txd",
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"msiof1_rxd",
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};
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static const char * const msiof2_groups[] = {
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"msiof2_clk",
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"msiof2_sync_a",
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"msiof2_sync_b",
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"msiof2_ss1",
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"msiof2_ss2",
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"msiof2_txd",
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"msiof2_rxd",
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};
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static const char * const msiof3_groups[] = {
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"msiof3_clk_a",
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"msiof3_sync_a",
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"msiof3_ss1_a",
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"msiof3_ss2_a",
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"msiof3_txd_a",
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"msiof3_rxd_a",
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"msiof3_clk_b",
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"msiof3_sync_b",
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"msiof3_ss1_b",
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"msiof3_ss2_b",
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"msiof3_txd_b",
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"msiof3_rxd_b",
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};
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(audio_clk),
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SH_PFC_FUNCTION(avb0),
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|
@ -2353,6 +2460,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
SH_PFC_FUNCTION(mmc),
|
||||
SH_PFC_FUNCTION(msiof0),
|
||||
SH_PFC_FUNCTION(msiof1),
|
||||
|
|
@ -2362,6 +2470,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(rpc),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
|
@ -2377,30 +2488,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_9 RESERVED */
|
||||
GP_0_8_FN, GPSR0_8,
|
||||
GP_0_7_FN, GPSR0_7,
|
||||
GP_0_6_FN, GPSR0_6,
|
||||
|
|
@ -2479,29 +2570,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_10 RESERVED */
|
||||
GP_3_9_FN, GPSR3_9,
|
||||
GP_3_8_FN, GPSR3_8,
|
||||
GP_3_7_FN, GPSR3_7,
|
||||
|
|
@ -2547,18 +2619,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_21 RESERVED */
|
||||
GP_5_20_FN, GPSR5_20,
|
||||
GP_5_19_FN, GPSR5_19,
|
||||
GP_5_18_FN, GPSR5_18,
|
||||
|
|
@ -2581,25 +2646,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_5_1_FN, GPSR5_1,
|
||||
GP_5_0_FN, GPSR5_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
|
||||
GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1),
|
||||
GROUP(
|
||||
/* GP6_31_14 RESERVED */
|
||||
GP_6_13_FN, GPSR6_13,
|
||||
GP_6_12_FN, GPSR6_12,
|
||||
GP_6_11_FN, GPSR6_11,
|
||||
|
|
@ -2750,13 +2801,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP12_7_4
|
||||
IP12_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
|
||||
/* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
|
||||
GROUP(-24, 4, 4),
|
||||
GROUP(
|
||||
/* IP13_31_8 RESERVED */
|
||||
IP13_7_4
|
||||
IP13_3_0 ))
|
||||
},
|
||||
|
|
@ -2766,11 +2814,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
|
||||
1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1,
|
||||
1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* RESERVED 31 */
|
||||
0, 0,
|
||||
MOD_SEL0_30
|
||||
MOD_SEL0_29
|
||||
MOD_SEL0_28
|
||||
|
|
@ -2782,7 +2829,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_20_19
|
||||
MOD_SEL0_18_17
|
||||
/* RESERVED 16 */
|
||||
0, 0,
|
||||
MOD_SEL0_15
|
||||
MOD_SEL0_14
|
||||
MOD_SEL0_13
|
||||
|
|
@ -2790,7 +2836,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_11
|
||||
MOD_SEL0_10
|
||||
/* RESERVED 9, 8, 7, 6 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
MOD_SEL0_5
|
||||
MOD_SEL0_4
|
||||
MOD_SEL0_3
|
||||
|
|
@ -2799,7 +2844,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
|
||||
GROUP(1, 1, 1, 1, 1, 1, -26),
|
||||
GROUP(
|
||||
MOD_SEL1_31
|
||||
MOD_SEL1_30
|
||||
|
|
@ -2807,25 +2852,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_28
|
||||
MOD_SEL1_27
|
||||
MOD_SEL1_26
|
||||
/* RESERVED 25, 24 */
|
||||
0, 0, 0, 0,
|
||||
/* RESERVED 23, 22, 21, 20 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 19, 18, 17, 16 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 11, 10, 9, 8 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 7, 6, 5, 4 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 3, 2, 1, 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
|
||||
/* RESERVED 25-0 */ ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
|
|
@ -2837,6 +2869,214 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
|
|||
return bit;
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */
|
||||
[ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */
|
||||
[ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */
|
||||
[ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */
|
||||
[ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */
|
||||
[ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */
|
||||
[ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */
|
||||
[ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */
|
||||
[ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */
|
||||
[ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */
|
||||
[10] = PIN_MLB_REF, /* MLB_REF */
|
||||
[11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */
|
||||
[12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */
|
||||
[13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */
|
||||
[14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */
|
||||
[15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */
|
||||
[16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */
|
||||
[17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */
|
||||
[18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
|
||||
[19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
|
||||
[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
|
||||
[22] = PIN_FSCLKST_N, /* FSCLKST# */
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = PIN_TDI, /* TDI */
|
||||
[29] = PIN_TMS, /* TMS */
|
||||
[30] = PIN_TCK, /* TCK */
|
||||
[31] = PIN_TRST_N, /* TRST# */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
|
||||
[ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */
|
||||
[ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */
|
||||
[ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */
|
||||
[ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */
|
||||
[ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */
|
||||
[ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */
|
||||
[ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */
|
||||
[ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */
|
||||
[ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */
|
||||
[ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */
|
||||
[10] = RCAR_GP_PIN(1, 31), /* QPOLB */
|
||||
[11] = RCAR_GP_PIN(1, 30), /* QPOLA */
|
||||
[12] = RCAR_GP_PIN(1, 29), /* DU_CDE */
|
||||
[13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */
|
||||
[14] = RCAR_GP_PIN(1, 27), /* DU_DISP */
|
||||
[15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */
|
||||
[16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */
|
||||
[17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */
|
||||
[18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */
|
||||
[19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */
|
||||
[20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */
|
||||
[21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */
|
||||
[22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */
|
||||
[23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */
|
||||
[24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */
|
||||
[25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */
|
||||
[26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */
|
||||
[27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */
|
||||
[28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */
|
||||
[29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */
|
||||
[30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */
|
||||
[31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */
|
||||
[ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */
|
||||
[ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */
|
||||
[ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */
|
||||
[ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */
|
||||
[ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */
|
||||
[ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */
|
||||
[ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */
|
||||
[ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */
|
||||
[ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */
|
||||
[10] = RCAR_GP_PIN(2, 31), /* NFCE# */
|
||||
[11] = RCAR_GP_PIN(2, 30), /* NFCLE */
|
||||
[12] = RCAR_GP_PIN(2, 29), /* NFALE */
|
||||
[13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */
|
||||
[14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */
|
||||
[15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */
|
||||
[16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */
|
||||
[17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */
|
||||
[18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */
|
||||
[19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */
|
||||
[20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */
|
||||
[21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */
|
||||
[22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */
|
||||
[23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */
|
||||
[24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */
|
||||
[25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */
|
||||
[26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */
|
||||
[27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */
|
||||
[28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */
|
||||
[29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */
|
||||
[30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */
|
||||
[31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */
|
||||
[ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */
|
||||
[ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */
|
||||
[ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */
|
||||
[ 4] = RCAR_GP_PIN(4, 27), /* TX2 */
|
||||
[ 5] = RCAR_GP_PIN(4, 26), /* RX2 */
|
||||
[ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */
|
||||
[ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */
|
||||
[ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */
|
||||
[ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */
|
||||
[10] = RCAR_GP_PIN(4, 21), /* TX0_A */
|
||||
[11] = RCAR_GP_PIN(4, 20), /* RX0_A */
|
||||
[12] = RCAR_GP_PIN(4, 19), /* SCK0_A */
|
||||
[13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */
|
||||
[14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */
|
||||
[15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */
|
||||
[16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */
|
||||
[17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */
|
||||
[18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */
|
||||
[19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */
|
||||
[20] = RCAR_GP_PIN(4, 11), /* SDA1 */
|
||||
[21] = RCAR_GP_PIN(4, 10), /* SCL1 */
|
||||
[22] = RCAR_GP_PIN(4, 9), /* SDA0 */
|
||||
[23] = RCAR_GP_PIN(4, 8), /* SCL0 */
|
||||
[24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */
|
||||
[25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */
|
||||
[26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */
|
||||
[27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
|
||||
[28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */
|
||||
[29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */
|
||||
[30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */
|
||||
[31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
|
||||
[ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */
|
||||
[ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */
|
||||
[ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */
|
||||
[ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */
|
||||
[ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */
|
||||
[ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */
|
||||
[ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */
|
||||
[ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */
|
||||
[ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */
|
||||
[10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */
|
||||
[11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */
|
||||
[12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */
|
||||
[13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */
|
||||
[14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */
|
||||
[15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */
|
||||
[16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */
|
||||
[17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */
|
||||
[18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */
|
||||
[19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */
|
||||
[20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */
|
||||
[21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */
|
||||
[22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */
|
||||
[23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */
|
||||
[24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */
|
||||
[25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */
|
||||
[26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */
|
||||
[27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */
|
||||
[28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */
|
||||
[29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */
|
||||
[30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */
|
||||
[31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
|
||||
[ 0] = SH_PFC_PIN_NONE,
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = SH_PFC_PIN_NONE,
|
||||
[ 3] = SH_PFC_PIN_NONE,
|
||||
[ 4] = SH_PFC_PIN_NONE,
|
||||
[ 5] = SH_PFC_PIN_NONE,
|
||||
[ 6] = SH_PFC_PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */
|
||||
[30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */
|
||||
[31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */
|
||||
} },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
TDSELCTRL,
|
||||
};
|
||||
|
|
@ -2846,13 +3086,88 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
|
||||
static const struct pinmux_bias_reg *
|
||||
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int *puen_bit, unsigned int *pud_bit)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
|
||||
if (!reg)
|
||||
return reg;
|
||||
|
||||
*puen_bit = bit;
|
||||
|
||||
/* NFWE# and NFRE# use different bit positions in PUD2 */
|
||||
switch (pin) {
|
||||
case RCAR_GP_PIN(3, 0): /* NFRE# */
|
||||
*pud_bit = 7;
|
||||
break;
|
||||
|
||||
case RCAR_GP_PIN(3, 1): /* NFWE# */
|
||||
*pud_bit = 8;
|
||||
break;
|
||||
|
||||
default:
|
||||
*pud_bit = bit;
|
||||
break;
|
||||
}
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int puen_bit, pud_bit;
|
||||
|
||||
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int puen_bit, pud_bit;
|
||||
u32 enable, updown;
|
||||
|
||||
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE) {
|
||||
enable |= BIT(puen_bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(pud_bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
}
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77995_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
|
||||
.get_bias = r8a77995_pinmux_get_bias,
|
||||
.set_bias = r8a77995_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a77995_pinmux_info = {
|
||||
.name = "r8a77995_pfc",
|
||||
.ops = &r8a77995_pinmux_ops,
|
||||
.ops = &r8a77995_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -2865,6 +3180,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
|
|
|
|||
Loading…
Reference in a new issue