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DHSOM: Power cycle Buck3 in reset

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DHCOM: Switch DWMAC RMII clock to MCO2
 stm32f746: fix display pinmux
 stm32mp: psci: Inhibit PDDS because CSTBYDIS is set
 stm32mp1: DT alignment with v6.4
 stm32mp1: add splashscreen with STMicroelectronics logo
 stm32mp1: clk: remove error for disabled clock in stm32mp1_clk_get_parent
 serial: stm32: Extend TC timeout
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Merge tag 'u-boot-stm32-20230816' of https://source.denx.de/u-boot/custodians/u-boot-stm

DHSOM: Power cycle Buck3 in reset
DHCOM: Switch DWMAC RMII clock to MCO2
stm32f746: fix display pinmux
stm32mp: psci: Inhibit PDDS because CSTBYDIS is set
stm32mp1: DT alignment with v6.4
stm32mp1: add splashscreen with STMicroelectronics logo
stm32mp1: clk: remove error for disabled clock in stm32mp1_clk_get_parent
serial: stm32: Extend TC timeout
This commit is contained in:
Tom Rini 2023-08-16 11:23:58 -04:00
commit 375fea811d
25 changed files with 375 additions and 80 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
MAINTAINERS
View file

@ -633,6 +633,7 @@ F: include/dt-bindings/clock/stm32mp*
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
F: include/dt-bindings/reset/stm32mp*
F: include/stm32_rcc.h
F: tools/logos/st.bmp
F: tools/stm32image.c
N: stm
N: stm32

2
arch/arm/dts/stm32f746-disco-u-boot.dtsi
View file

@ -169,7 +169,7 @@
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
<STM32_PINMUX('G',12, AF14)>, /* B4 */
<STM32_PINMUX('G',12, AF9)>, /* B4 */
<STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
<STM32_PINMUX('I',10, AF14)>, /* HSYNC */
<STM32_PINMUX('I',14, AF14)>, /* CLK */

129
arch/arm/dts/stm32mp13-pinctrl.dtsi
View file

@ -258,4 +258,133 @@
bias-disable;
};
};
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_idle_pins_a: uart8-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_sleep_pins_a: uart8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
};
};
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
bias-pull-up;
};
};
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
bias-pull-up;
};
};
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
};

99
arch/arm/dts/stm32mp131.dtsi
View file

@ -397,12 +397,42 @@
status = "disabled";
};
usart3: serial@4000f000 {
compatible = "st,stm32h7-uart";
reg = <0x4000f000 0x400>;
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
resets = <&rcc USART3_R>;
wakeup-source;
dmas = <&dmamux1 45 0x400 0x5>,
<&dmamux1 46 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
resets = <&rcc UART4_R>;
wakeup-source;
dmas = <&dmamux1 63 0x400 0x5>,
<&dmamux1 64 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart5: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
resets = <&rcc UART5_R>;
wakeup-source;
dmas = <&dmamux1 65 0x400 0x5>,
<&dmamux1 66 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -442,6 +472,32 @@
status = "disabled";
};
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
resets = <&rcc UART7_R>;
wakeup-source;
dmas = <&dmamux1 79 0x400 0x5>,
<&dmamux1 80 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart8: serial@40019000 {
compatible = "st,stm32h7-uart";
reg = <0x40019000 0x400>;
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
resets = <&rcc UART8_R>;
wakeup-source;
dmas = <&dmamux1 81 0x400 0x5>,
<&dmamux1 82 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
timers1: timer@44000000 {
#address-cells = <1>;
#size-cells = <0>;
@ -524,6 +580,19 @@
};
};
usart6: serial@44003000 {
compatible = "st,stm32h7-uart";
reg = <0x44003000 0x400>;
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
resets = <&rcc USART6_R>;
wakeup-source;
dmas = <&dmamux1 71 0x400 0x5>,
<&dmamux1 72 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
i2s1: audio-controller@44004000 {
compatible = "st,stm32h7-i2s";
reg = <0x44004000 0x400>;
@ -748,6 +817,32 @@
status = "disabled";
};
usart1: serial@4c000000 {
compatible = "st,stm32h7-uart";
reg = <0x4c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
resets = <&rcc USART1_R>;
wakeup-source;
dmas = <&dmamux1 41 0x400 0x5>,
<&dmamux1 42 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
usart2: serial@4c001000 {
compatible = "st,stm32h7-uart";
reg = <0x4c001000 0x400>;
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
resets = <&rcc USART2_R>;
wakeup-source;
dmas = <&dmamux1 43 0x400 0x5>,
<&dmamux1 44 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
i2s4: audio-controller@4c002000 {
compatible = "st,stm32h7-i2s";
reg = <0x4c002000 0x400>;
@ -1001,8 +1096,6 @@
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,

42
arch/arm/dts/stm32mp135f-dk.dts
View file

@ -19,6 +19,13 @@
aliases {
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@c0000000 {
@ -267,8 +274,41 @@
};
&uart4 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart8_pins_a>;
pinctrl-1 = <&uart8_sleep_pins_a>;
pinctrl-2 = <&uart8_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};
&usart1 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart1_pins_a>;
pinctrl-1 = <&usart1_sleep_pins_a>;
pinctrl-2 = <&usart1_idle_pins_a>;
uart-has-rtscts;
status = "disabled";
};
/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_sleep_pins_a>;
pinctrl-2 = <&usart2_idle_pins_a>;
uart-has-rtscts;
status = "okay";
};

34
arch/arm/dts/stm32mp15-pinctrl.dtsi
View file

@ -1880,6 +1880,21 @@
};
};
spi1_pins_b: spi1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
bias-disable;
};
};
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
@ -2163,7 +2178,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@ -2181,7 +2196,7 @@
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@ -2448,19 +2463,4 @@
bias-disable;
};
};
spi1_pins_b: spi1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
bias-disable;
};
};
};

4
arch/arm/dts/stm32mp151.dtsi
View file

@ -1148,8 +1148,8 @@
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
clocks = <&rcc USBO_K>, <&usbphyc>;
clock-names = "otg", "utmi";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

3
arch/arm/dts/stm32mp157a-dk1.dts
View file

@ -17,9 +17,6 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
chosen {

3
arch/arm/dts/stm32mp157c-dk2.dts
View file

@ -18,9 +18,6 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
serial3 = &usart2;
};

17
arch/arm/dts/stm32mp157c-ed1.dts
View file

@ -16,6 +16,10 @@
model = "STMicroelectronics STM32MP157C eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
aliases {
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
@ -65,15 +69,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@e8000000 {
reg = <0xe8000000 0x8000000>;
no-map;
};
};
aliases {
serial0 = &uart4;
};
sd_switch: regulator-sd_switch {
@ -148,10 +143,6 @@
status = "okay";
};
&gpu {
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};

9
arch/arm/dts/stm32mp157c-ev1.dts
View file

@ -14,16 +14,15 @@
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart4;
serial1 = &usart3;
ethernet0 = &ethernet0;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;

22
arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
View file

@ -118,13 +118,12 @@
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
pinctrl-0 = <&ethernet0_rmii_pins_c &mco2_pins_a>;
pinctrl-1 = <&ethernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
mdio0 {
#address-cells = <1>;
@ -136,7 +135,7 @@
/* LAN8710Ai */
compatible = "ethernet-phy-id0007.c0f0",
"ethernet-phy-ieee802.3-c22";
clocks = <&rcc ETHCK_K>;
clocks = <&rcc CK_MCO2>;
reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
reset-assert-us = <500>;
reset-deassert-us = <500>;
@ -450,6 +449,21 @@
};
};
&rcc {
/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
clocks = <&rcc CK_MCO2>;
clock-names = "ETH_RX_CLK/ETH_REF_CLK";
/*
* Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
* set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
* so that MCO2 behaves as a divider for the ETHRX clock here.
*/
assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
assigned-clock-parents = <&rcc PLL4_P>;
assigned-clock-rates = <50000000>, <100000000>;
};
&rng1 {
status = "okay";
};

14
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View file

@ -153,6 +153,20 @@
};
&rcc {
/*
* Reinstate clock names from stm32mp151.dtsi, the MCO2 trick
* used in stm32mp15xx-dhcom-som.dtsi is not supported by the
* U-Boot clock framework.
*/
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
<&clk_lse>, <&clk_lsi>;
/* The MCO2 is already configured correctly, remove those. */
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P

15
arch/arm/dts/stm32mp15xx-dkx.dtsi
View file

@ -8,6 +8,12 @@
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@ -53,11 +59,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@d4000000 {
reg = <0xd4000000 0x4000000>;
no-map;
};
};
led {
@ -159,10 +160,6 @@
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};

2
arch/arm/mach-stm32mp/psci.c
View file

@ -729,7 +729,7 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS);
saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR);
saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);

10
board/st/common/stpmic1.c
View file

@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
}
/* early init of PMIC */
void stpmic1_init(u32 voltage_mv)
struct udevice *stpmic1_init(u32 voltage_mv)
{
struct udevice *dev;
if (uclass_get_device_by_driver(UCLASS_PMIC,
DM_DRIVER_GET(pmic_stpmic1), &dev))
return;
return NULL;
/* update VDDCORE = BUCK1 */
if (voltage_mv)
stmpic_buck1_set(dev, voltage_mv);
/* Keep vdd on during the reset cycle */
pmic_clrsetbits(dev,
STPMIC1_BUCKS_MRST_CR,
STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
return dev;
}

2
board/st/common/stpmic1.h
View file

@ -3,4 +3,4 @@
* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
*/
void stpmic1_init(u32 voltage_mv);
struct udevice *stpmic1_init(u32 voltage_mv);

13
board/st/stm32mp1/spl.c
View file

@ -5,6 +5,8 @@
#include <config.h>
#include <common.h>
#include <power/pmic.h>
#include <power/stpmic1.h>
#include <asm/arch/sys_proto.h>
#include "../common/stpmic1.h"
@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv)
int board_early_init_f(void)
{
if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER))
stpmic1_init(opp_voltage_mv);
if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) {
struct udevice *dev = stpmic1_init(opp_voltage_mv);
/* Keep vdd on during the reset cycle */
pmic_clrsetbits(dev,
STPMIC1_BUCKS_MRST_CR,
STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
}
return 0;
}

3
configs/stm32mp15_basic_defconfig
View file

@ -171,6 +171,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@ -178,6 +179,8 @@ CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y

3
configs/stm32mp15_defconfig
View file

@ -147,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@ -154,6 +155,8 @@ CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y

3
configs/stm32mp15_trusted_defconfig
View file

@ -147,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
@ -154,6 +155,8 @@ CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=1280
CONFIG_VIDEO_STM32_MAX_YRES=800
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y

3
drivers/clk/stm32/clk-stm32mp1.c
View file

@ -881,7 +881,8 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
return sel[s].parent[p];
}
log_err("no parents defined for clk id %d\n", (u32)id);
/* clock is DISABLED when the clock src is not in clk_parent[] range */
log_debug("no parents defined for clk id %d\n", (u32)id);
return -EINVAL;
}

18
drivers/serial/serial_stm32.c
View file

@ -22,6 +22,14 @@
#include "serial_stm32.h"
#include <dm/device_compat.h>
/*
* At 115200 bits/s
* 1 bit = 1 / 115200 = 8,68 us
* 8 bits = 69,444 us
* 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us
*/
#define ONE_BYTE_B115200_US 87
static void _stm32_serial_setbrg(fdt_addr_t base,
struct stm32_uart_info *uart_info,
u32 clock_rate,
@ -209,12 +217,10 @@ static int stm32_serial_probe(struct udevice *dev)
* before uart initialization, wait for TC bit (Transmission Complete)
* in case there is still chars from previous bootstage to transmit
*/
ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 10, 150,
plat->base + ISR_OFFSET(stm32f4));
if (ret) {
clk_disable(&clk);
return ret;
}
ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50,
16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4));
if (ret)
dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret);
ret = reset_get_by_index(dev, 0, &reset);
if (!ret) {

4
include/configs/stm32mp15_st_common.h
View file

@ -10,7 +10,9 @@
#define STM32MP_BOARD_EXTRA_ENV \
"usb_pgood_delay=2000\0" \
"console=ttySTM0\0"
"console=ttySTM0\0" \
"splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"splashpos=m,m\0"
#include <configs/stm32mp15_common.h>

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