From 373c1428a0374c29f19cca76f12c0e93378a634a Mon Sep 17 00:00:00 2001
From: Dinesh Maniyam <dinesh.maniyam@intel.com>
Date: Wed, 1 Jun 2022 15:54:59 +0800
Subject: [PATCH] arch: arm: socfpga: timer_s10: Override udelay for secure
 section

Override __udelay() as 'always inlined' function so that PSCI code
run in '__secure' section can call this delay function as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/timer_s10.c | 34 ++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c
index 7d5598e1a3..84b13ce9d3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2022 Intel Corporation <www.intel.com>
  *
  */
 
 #include <common.h>
 #include <init.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
@@ -26,3 +27,34 @@ int timer_init(void)
 #endif
 	return 0;
 }
+
+__always_inline u64 __get_time_stamp(void)
+{
+	u64 cntpct;
+
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+
+	return cntpct;
+}
+
+__always_inline uint64_t __usec_to_tick(unsigned long usec)
+{
+	u64 tick = usec;
+	u64 cntfrq;
+
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+	tick *= cntfrq;
+	do_div(tick, 1000000);
+
+	return tick;
+}
+
+__always_inline void __udelay(unsigned long usec)
+{
+	/* get current timestamp */
+	u64 tmp = __get_time_stamp() + __usec_to_tick(usec);
+
+	while (__get_time_stamp() < tmp + 1)	/* loop till event */
+		;
+}
\ No newline at end of file