mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
ppc4xx: remove CPCIISER4 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
This commit is contained in:
Matthias Fuchs
Tom Rini
parent
2404124c47
commit
3705726010
10 changed files with 0 additions and 4667 deletions
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@ -125,9 +125,6 @@ config TARGET_CPCI405AB
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config TARGET_CPCI405DT
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bool "Support CPCI405DT"
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config TARGET_CPCIISER4
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bool "Support CPCIISER4"
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config TARGET_DP405
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bool "Support DP405"
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@ -247,7 +244,6 @@ source "board/csb472/Kconfig"
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source "board/dave/PPChameleonEVB/Kconfig"
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source "board/esd/cpci2dp/Kconfig"
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source "board/esd/cpci405/Kconfig"
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source "board/esd/cpciiser4/Kconfig"
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source "board/esd/dp405/Kconfig"
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source "board/esd/du405/Kconfig"
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source "board/esd/du440/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_CPCIISER4
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config SYS_BOARD
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default "cpciiser4"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "CPCIISER4"
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endif
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@ -1,6 +0,0 @@
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CPCIISER4 BOARD
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M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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S: Maintained
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F: board/esd/cpciiser4/
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F: include/configs/CPCIISER4.h
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F: configs/CPCIISER4_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = cpciiser4.o flash.o ../common/misc.o
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@ -1,165 +0,0 @@
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/*
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* (C) Copyright 2000
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "cpciiser4.h"
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#include <asm/processor.h>
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#include <command.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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/* ------------------------------------------------------------------------- */
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#if 0
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#define FPGA_DEBUG
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#endif
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#if 0
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#define FPGA_DEBUG2
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#endif
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] = {
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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int board_early_init_f (void)
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{
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int index, len, i;
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int status;
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#ifdef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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/*
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* Boot onboard FPGA
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*/
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status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
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if (status != 0) {
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/* booting FPGA failed */
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#ifndef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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printf ("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf ("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf ("Rebooting in %2d seconds \r", i);
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for (index = 0; index < 1000; index++)
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udelay (1000);
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}
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putc ('\n');
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do_reset (NULL, 0, 0, NULL);
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}
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/*
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* Init FPGA via RESET (read access on CS3)
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*/
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in_8((void *)0xf0200000);
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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/* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */
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mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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int index;
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int len;
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char str[64];
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int i = getenv_f("serial#", str, sizeof (str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming AR405");
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} else {
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puts(str);
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}
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puts ("\nFPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("%s ", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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return 0;
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}
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@ -1,28 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/****************************************************************************
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* FLASH Memory Map as used by TQ Monitor:
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*
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* Start Address Length
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* +-----------------------+ 0x4000_0000 Start of Flash -----------------
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* | MON8xx code | 0x4000_0100 Reset Vector
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* +-----------------------+ 0x400?_????
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* | (unused) |
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* +-----------------------+ 0x4001_FF00
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* | Ethernet Addresses | 0x78
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* +-----------------------+ 0x4001_FF78
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* | (Reserved for MON8xx) | 0x44
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* +-----------------------+ 0x4001_FFBC
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* | Lock Address | 0x04
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* +-----------------------+ 0x4001_FFC0 ^
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* | Hardware Information | 0x40 | MON8xx
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* +=======================+ 0x4002_0000 (sector border) -----------------
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* | Autostart Header | | Applications
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* | ... | v
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*
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*****************************************************************************/
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@ -1,68 +0,0 @@
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/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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/*
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* include common flash code (for esd boards)
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*/
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#include "../common/flash.c"
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0;
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int i;
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uint pbcr;
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unsigned long base_b0;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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/* Setup offsets */
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flash_get_offsets (-size_b0, &flash_info[0]);
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/* Re-do sizing to get full correct info */
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mtdcr(EBC0_CFGADDR, PB0CR);
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pbcr = mfdcr(EBC0_CFGDATA);
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mtdcr(EBC0_CFGADDR, PB0CR);
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base_b0 = -size_b0;
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
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mtdcr(EBC0_CFGDATA, pbcr);
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/* printf("PB1CR = %x\n", pbcr); */
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-monitor_flash_len,
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0xffffffff,
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&flash_info[0]);
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flash_info[0].size = size_b0;
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return (size_b0);
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}
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File diff suppressed because it is too large
Load diff
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@ -1,3 +0,0 @@
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CONFIG_PPC=y
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CONFIG_4xx=y
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CONFIG_TARGET_CPCIISER4=y
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@ -1,237 +0,0 @@
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/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND "bootm fff00000"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_EEPROM
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */
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#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
|
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface.
|
||||
* All other boards should use the standard values (CPCI405 etc.)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC08) for environment
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
|
||||
#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
|
||||
/* total size of a CAT24WC08 is 1024 bytes */
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 1 (Uart 8bit) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */
|
||||
#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 2 (Uart 32bit) initialization */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
|
||||
#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
|
||||
|
||||
/* Memory Bank 3 (FPGA Reset) initialization */
|
||||
#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */
|
||||
#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue