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rockchip: video: Add a display driver for rockchip LVDS
Some Rockchip SoCs support LVDS output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Jacob Chen
Anatolij Gustschin
parent
450f3c7135
commit
35ac89dd8f
3 changed files with 352 additions and 1 deletions
97
arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
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97
arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
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@ -0,0 +1,97 @@
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/*
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* Copyright 2016 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_LVDS_RK3288_H
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#define _ASM_ARCH_LVDS_RK3288_H
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#define RK3288_LVDS_CH0_REG0 0x00
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#define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
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#define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
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#define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
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#define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
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#define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
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#define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
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#define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
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#define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
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#define RK3288_LVDS_CH0_REG1 0x04
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#define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
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#define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
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#define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3)
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#define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2)
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#define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1)
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#define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0)
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#define RK3288_LVDS_CH0_REG2 0x08
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#define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7)
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#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6)
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#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5)
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#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4)
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#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3)
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#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2)
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#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1)
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#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0)
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#define RK3288_LVDS_CH0_REG3 0x0c
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#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff
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#define RK3288_LVDS_CH0_REG4 0x10
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#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5)
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#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4)
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#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3)
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#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2)
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#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1)
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#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)
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#define RK3288_LVDS_CH0_REG5 0x14
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#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5)
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#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4)
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#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3)
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#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2)
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#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1)
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#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0)
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#define RK3288_LVDS_CFG_REGC 0x30
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#define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00
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#define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff
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#define RK3288_LVDS_CH0_REGD 0x34
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#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f
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#define RK3288_LVDS_CH0_REG20 0x80
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#define RK3288_LVDS_CH0_REG20_MSB 0x45
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#define RK3288_LVDS_CH0_REG20_LSB 0x44
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#define RK3288_LVDS_CFG_REG21 0x84
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#define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92
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#define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00
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/* fbdiv value is split over 2 registers, with bit8 in reg2 */
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#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
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(_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
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#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
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(_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
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#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
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(_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
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#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3)
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#define LVDS_FMT_MASK (7 << 16)
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#define LVDS_MSB (1 << 3)
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#define LVDS_DUAL (1 << 4)
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#define LVDS_FMT_1 (1 << 5)
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#define LVDS_TTL_EN (1 << 6)
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#define LVDS_START_PHASE_RST_1 (1 << 7)
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#define LVDS_DCLK_INV (1 << 8)
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#define LVDS_CH0_EN (1 << 11)
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#define LVDS_CH1_EN (1 << 12)
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#define LVDS_PWRDN (1 << 15)
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#define LVDS_24BIT (0 << 1)
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#define LVDS_18BIT (1 << 1)
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#endif
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@ -5,4 +5,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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obj-y += rk_edp.o rk_hdmi.o rk_vop.o
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obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
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254
drivers/video/rockchip/rk_lvds.c
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254
drivers/video/rockchip/rk_lvds.c
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@ -0,0 +1,254 @@
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/*
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* Copyright 2016 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <panel.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/lvds_rk3288.h>
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#include <asm/arch/grf_rk3288.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/video/rk3288.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* struct rk_lvds_priv - private rockchip lvds display driver info
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*
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* @reg: LVDS register address
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* @grf: GRF register
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* @panel: Panel device that is used in driver
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*
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* @output: Output mode, decided single or double channel,
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* LVDS or LVTLL
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* @format: Data format that RGB data will packing as
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*/
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struct rk_lvds_priv {
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void __iomem *regs;
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struct rk3288_grf *grf;
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struct udevice *panel;
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int output;
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int format;
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};
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static inline void lvds_writel(struct rk_lvds_priv *lvds, u32 offset, u32 val)
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{
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writel(val, lvds->regs + offset);
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writel(val, lvds->regs + offset + 0x100);
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}
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int rk_lvds_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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struct rk_lvds_priv *priv = dev_get_priv(dev);
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struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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int ret = 0;
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unsigned int val = 0;
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ret = panel_enable_backlight(priv->panel);
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if (ret) {
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debug("%s: backlight error: %d\n", __func__, ret);
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return ret;
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}
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/* Select the video source */
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if (uc_plat->source_id)
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val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT |
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(RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16);
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else
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val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16;
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rk_setreg(&priv->grf->soc_con6, val);
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/* Select data transfer format */
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val = priv->format;
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if (priv->output == LVDS_OUTPUT_DUAL)
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val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN;
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else if (priv->output == LVDS_OUTPUT_SINGLE)
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val |= LVDS_CH0_EN;
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else if (priv->output == LVDS_OUTPUT_RGB)
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val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN;
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val |= (0xffff << 16);
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rk_setreg(&priv->grf->soc_con7, val);
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/* Enable LVDS PHY */
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if (priv->output == LVDS_OUTPUT_RGB) {
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lvds_writel(priv, RK3288_LVDS_CH0_REG0,
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RK3288_LVDS_CH0_REG0_TTL_EN |
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RK3288_LVDS_CH0_REG0_LANECK_EN |
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RK3288_LVDS_CH0_REG0_LANE4_EN |
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RK3288_LVDS_CH0_REG0_LANE3_EN |
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RK3288_LVDS_CH0_REG0_LANE2_EN |
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RK3288_LVDS_CH0_REG0_LANE1_EN |
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RK3288_LVDS_CH0_REG0_LANE0_EN);
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lvds_writel(priv, RK3288_LVDS_CH0_REG2,
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RK3288_LVDS_PLL_FBDIV_REG2(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG3,
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RK3288_LVDS_PLL_FBDIV_REG3(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG4,
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RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE);
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lvds_writel(priv, RK3288_LVDS_CH0_REG5,
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RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA);
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lvds_writel(priv, RK3288_LVDS_CH0_REGD,
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RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
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lvds_writel(priv, RK3288_LVDS_CH0_REG20,
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RK3288_LVDS_CH0_REG20_LSB);
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} else {
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lvds_writel(priv, RK3288_LVDS_CH0_REG0,
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RK3288_LVDS_CH0_REG0_LVDS_EN |
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RK3288_LVDS_CH0_REG0_LANECK_EN |
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RK3288_LVDS_CH0_REG0_LANE4_EN |
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RK3288_LVDS_CH0_REG0_LANE3_EN |
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RK3288_LVDS_CH0_REG0_LANE2_EN |
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RK3288_LVDS_CH0_REG0_LANE1_EN |
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RK3288_LVDS_CH0_REG0_LANE0_EN);
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lvds_writel(priv, RK3288_LVDS_CH0_REG1,
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RK3288_LVDS_CH0_REG1_LANECK_BIAS |
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RK3288_LVDS_CH0_REG1_LANE4_BIAS |
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RK3288_LVDS_CH0_REG1_LANE3_BIAS |
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RK3288_LVDS_CH0_REG1_LANE2_BIAS |
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RK3288_LVDS_CH0_REG1_LANE1_BIAS |
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RK3288_LVDS_CH0_REG1_LANE0_BIAS);
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lvds_writel(priv, RK3288_LVDS_CH0_REG2,
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RK3288_LVDS_CH0_REG2_RESERVE_ON |
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RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE |
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RK3288_LVDS_PLL_FBDIV_REG2(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG3,
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RK3288_LVDS_PLL_FBDIV_REG3(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG4, 0x00);
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lvds_writel(priv, RK3288_LVDS_CH0_REG5, 0x00);
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lvds_writel(priv, RK3288_LVDS_CH0_REGD,
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RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
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lvds_writel(priv, RK3288_LVDS_CH0_REG20,
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RK3288_LVDS_CH0_REG20_LSB);
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}
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/* Power on */
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writel(RK3288_LVDS_CFG_REGC_PLL_ENABLE,
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priv->regs + RK3288_LVDS_CFG_REGC);
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writel(RK3288_LVDS_CFG_REG21_TX_ENABLE,
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priv->regs + RK3288_LVDS_CFG_REG21);
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return 0;
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}
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int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
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{
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if (fdtdec_decode_display_timing
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(gd->fdt_blob, dev->of_offset, 0, timing)) {
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debug("%s: Failed to decode display timing\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk_lvds_priv *priv = dev_get_priv(dev);
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const void *blob = gd->fdt_blob;
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int node = dev->of_offset;
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int ret;
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priv->regs = (void *)dev_get_addr(dev);
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
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if (ret != -1) {
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priv->output = ret;
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||||||
|
debug("LVDS output : %d\n", ret);
|
||||||
|
} else {
|
||||||
|
/* default set it as output rgb */
|
||||||
|
priv->output = LVDS_OUTPUT_RGB;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
|
||||||
|
if (ret != -1) {
|
||||||
|
priv->format = ret;
|
||||||
|
debug("LVDS data-mapping : %d\n", ret);
|
||||||
|
} else {
|
||||||
|
/* default set it as format jeida */
|
||||||
|
priv->format = LVDS_FORMAT_JEIDA;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
|
||||||
|
if (ret != -1) {
|
||||||
|
debug("LVDS data-width : %d\n", ret);
|
||||||
|
if (ret == 24) {
|
||||||
|
priv->format |= LVDS_24BIT;
|
||||||
|
} else if (ret == 18) {
|
||||||
|
priv->format |= LVDS_18BIT;
|
||||||
|
} else {
|
||||||
|
debug("rockchip-lvds unsupport data-width[%d]\n", ret);
|
||||||
|
ret = -EINVAL;
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
priv->format |= LVDS_24BIT;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int rk_lvds_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct rk_lvds_priv *priv = dev_get_priv(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
|
||||||
|
&priv->panel);
|
||||||
|
if (ret) {
|
||||||
|
debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
|
||||||
|
dev->name, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dm_display_ops lvds_rockchip_ops = {
|
||||||
|
.read_timing = rk_lvds_read_timing,
|
||||||
|
.enable = rk_lvds_enable,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id rockchip_lvds_ids[] = {
|
||||||
|
{.compatible = "rockchip,rk3288-lvds"},
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(lvds_rockchip) = {
|
||||||
|
.name = "lvds_rockchip",
|
||||||
|
.id = UCLASS_DISPLAY,
|
||||||
|
.of_match = rockchip_lvds_ids,
|
||||||
|
.ops = &lvds_rockchip_ops,
|
||||||
|
.ofdata_to_platdata = rk_lvds_ofdata_to_platdata,
|
||||||
|
.probe = rk_lvds_probe,
|
||||||
|
.priv_auto_alloc_size = sizeof(struct rk_lvds_priv),
|
||||||
|
};
|
||||||
Loading…
Reference in a new issue