mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
ARM: remove dkb board support
This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Lei Wen <leiwen@marvell.com> Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
41fbbbbc71
commit
346cfba4f0
18 changed files with 1 additions and 793 deletions
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@ -223,10 +223,6 @@ config ORION5X
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bool "Marvell Orion"
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bool "Marvell Orion"
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select CPU_ARM926EJS
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select CPU_ARM926EJS
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config TARGET_DKB
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bool "Support dkb"
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select CPU_ARM926EJS
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config TARGET_SPEAR300
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config TARGET_SPEAR300
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bool "Support spear300"
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bool "Support spear300"
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select CPU_ARM926EJS
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select CPU_ARM926EJS
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@ -757,7 +753,6 @@ source "board/BuR/tseries/Kconfig"
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source "board/CarMediaLab/flea3/Kconfig"
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source "board/CarMediaLab/flea3/Kconfig"
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source "board/Marvell/aspenite/Kconfig"
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source "board/Marvell/aspenite/Kconfig"
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source "board/Marvell/db-mv784mp-gp/Kconfig"
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source "board/Marvell/db-mv784mp-gp/Kconfig"
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source "board/Marvell/dkb/Kconfig"
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source "board/Marvell/gplugd/Kconfig"
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source "board/Marvell/gplugd/Kconfig"
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source "board/altera/socfpga/Kconfig"
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source "board/altera/socfpga/Kconfig"
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source "board/armadeus/apf27/Kconfig"
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source "board/armadeus/apf27/Kconfig"
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@ -19,5 +19,4 @@ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
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obj-$(CONFIG_MX25) += mx25/
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obj-$(CONFIG_MX25) += mx25/
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obj-$(CONFIG_MX27) += mx27/
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obj-$(CONFIG_MX27) += mx27/
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obj-$(if $(filter mxs,$(SOC)),y) += mxs/
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obj-$(if $(filter mxs,$(SOC)),y) += mxs/
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obj-$(CONFIG_PANTHEON) += pantheon/
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obj-$(if $(filter spear,$(SOC)),y) += spear/
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obj-$(if $(filter spear,$(SOC)),y) += spear/
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2011
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Lei Wen <leiwen@marvell.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = cpu.o timer.o dram.o
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@ -1,85 +0,0 @@
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/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pantheon.h>
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#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
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#define SET_MRVL_ID (1<<8)
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#define L2C_RAM_SEL (1<<4)
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int arch_cpu_init(void)
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{
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u32 val;
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struct panthcpu_registers *cpuregs =
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(struct panthcpu_registers*) PANTHEON_CPU_BASE;
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struct panthapb_registers *apbclkres =
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(struct panthapb_registers*) PANTHEON_APBC_BASE;
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struct panthmpmu_registers *mpmu =
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(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
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struct panthapmu_registers *apmu =
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(struct panthapmu_registers *) PANTHEON_APMU_BASE;
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/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
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val = readl(&cpuregs->cpu_conf);
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val = val | SET_MRVL_ID;
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writel(val, &cpuregs->cpu_conf);
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/* Turn on clock gating (PMUM_CCGR) */
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writel(0xFFFFFFFF, &mpmu->ccgr);
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/* Turn on clock gating (PMUM_ACGR) */
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writel(0xFFFFFFFF, &mpmu->acgr);
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/* Turn on uart2 clock */
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writel(UARTCLK14745KHZ, &apbclkres->uart0);
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/* Enable GPIO clock */
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writel(APBC_APBCLK, &apbclkres->gpio);
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#ifdef CONFIG_I2C_MV
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/* Enable I2C clock */
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writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
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writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
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#endif
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#ifdef CONFIG_MV_SDHCI
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/* Enable mmc clock */
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writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
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&apmu->sd1);
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writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
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&apmu->sd3);
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#endif
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icache_enable();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 id;
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struct panthcpu_registers *cpuregs =
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(struct panthcpu_registers*) PANTHEON_CPU_BASE;
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id = readl(&cpuregs->chip_id);
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printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
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return 0;
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}
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#endif
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#ifdef CONFIG_I2C_MV
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void i2c_clk_enable(void)
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{
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}
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#endif
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@ -1,117 +0,0 @@
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/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>,
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/pantheon.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Pantheon DRAM controller supports upto 8 banks
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* for chip select 0 and 1
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*/
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/*
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* DDR Memory Control Registers
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* Refer Datasheet 4.4
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*/
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struct panthddr_map_registers {
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u32 cs; /* Memory Address Map Register -CS */
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u32 pad[3];
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};
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struct panthddr_registers {
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u8 pad[0x100 - 0x000];
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struct panthddr_map_registers mmap[2];
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};
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/*
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* panth_sdram_base - reads SDRAM Base Address Register
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*/
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u32 panth_sdram_base(int chip_sel)
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{
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struct panthddr_registers *ddr_regs =
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(struct panthddr_registers *)PANTHEON_DRAM_BASE;
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u32 result = 0;
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u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
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if (!CS_valid)
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return 0;
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result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
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return result;
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}
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/*
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* panth_sdram_size - reads SDRAM size
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*/
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u32 panth_sdram_size(int chip_sel)
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{
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struct panthddr_registers *ddr_regs =
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(struct panthddr_registers *)PANTHEON_DRAM_BASE;
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u32 result = 0;
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u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
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if (!CS_valid)
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return 0;
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result = readl(&ddr_regs->mmap[chip_sel].cs);
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result = (result >> 16) & 0xF;
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if (result < 0x7) {
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printf("Unknown DRAM Size\n");
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return -1;
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} else {
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return ((0x8 << (result - 0x7)) * 1024 * 1024);
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}
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}
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#ifndef CONFIG_SYS_BOARD_DRAM_INIT
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int dram_init(void)
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{
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int i;
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gd->ram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = panth_sdram_base(i);
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gd->bd->bi_dram[i].size = panth_sdram_size(i);
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/*
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* It is assumed that all memory banks are consecutive
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* and without gaps.
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* If the gap is found, ram_size will be reported for
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* consecutive memory only
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*/
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if (gd->bd->bi_dram[i].start != gd->ram_size)
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break;
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gd->ram_size += gd->bd->bi_dram[i].size;
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}
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for (; i < CONFIG_NR_DRAM_BANKS; i++) {
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/*
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* If above loop terminated prematurely, we need to set
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* remaining banks' start address & size as 0. Otherwise other
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* u-boot functions and Linux kernel gets wrong values which
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* could result in crash
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*/
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gd->bd->bi_dram[i].start = 0;
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gd->bd->bi_dram[i].size = 0;
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}
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return 0;
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}
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/*
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* If this function is not defined here,
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* board.c alters dram bank zero configuration defined above.
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*/
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void dram_init_banksize(void)
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{
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dram_init();
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}
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#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
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@ -1,201 +0,0 @@
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/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pantheon.h>
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/*
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* Timer registers
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* Refer 6.2.9 in Datasheet
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*/
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struct panthtmr_registers {
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u32 clk_ctrl; /* Timer clk control reg */
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u32 match[9]; /* Timer match registers */
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u32 count[3]; /* Timer count registers */
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u32 status[3];
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u32 ie[3];
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u32 preload[3]; /* Timer preload value */
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u32 preload_ctrl[3];
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u32 wdt_match_en;
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u32 wdt_match_r;
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u32 wdt_val;
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u32 wdt_sts;
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u32 icr[3];
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u32 wdt_icr;
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u32 cer; /* Timer count enable reg */
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u32 cmr;
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u32 ilr[3];
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u32 wcr;
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u32 wfar;
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u32 wsar;
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u32 cvwr[3];
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};
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#define TIMER 0 /* Use TIMER 0 */
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/* Each timer has 3 match registers */
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#define MATCH_CMP(x) ((3 * TIMER) + x)
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#define TIMER_LOAD_VAL 0xffffffff
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#define COUNT_RD_REQ 0x1
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DECLARE_GLOBAL_DATA_PTR;
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/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
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/*
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* For preventing risk of instability in reading counter value,
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* first set read request to register cvwr and then read same
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* register after it captures counter value.
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*/
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ulong read_timer(void)
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{
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struct panthtmr_registers *panthtimers =
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(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
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volatile int loop=100;
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ulong val;
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writel(COUNT_RD_REQ, &panthtimers->cvwr);
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while (loop--)
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val = readl(&panthtimers->cvwr);
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/*
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* This stop gcc complain and prevent loop mistake init to 0
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*/
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val = readl(&panthtimers->cvwr);
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return val;
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}
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ulong get_timer_masked(void)
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{
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ulong now = read_timer();
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if (now >= gd->arch.tbl) {
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/* normal mode */
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gd->arch.tbu += now - gd->arch.tbl;
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} else {
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/* we have an overflow ... */
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gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
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}
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gd->arch.tbl = now;
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return gd->arch.tbu;
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}
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ulong get_timer(ulong base)
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{
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return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
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base);
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}
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void __udelay(unsigned long usec)
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{
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ulong delayticks;
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ulong endtime;
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delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
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endtime = get_timer_masked() + delayticks;
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while (get_timer_masked() < endtime)
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;
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}
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/*
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* init the Timer
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*/
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int timer_init(void)
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{
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struct panthapb_registers *apb1clkres =
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(struct panthapb_registers *) PANTHEON_APBC_BASE;
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struct panthtmr_registers *panthtimers =
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(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
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/* Enable Timer clock at 3.25 MHZ */
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writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
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/* load value into timer */
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writel(0x0, &panthtimers->clk_ctrl);
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/* Use Timer 0 Match Resiger 0 */
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writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
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/* Preload value is 0 */
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writel(0x0, &panthtimers->preload[TIMER]);
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/* Enable match comparator 0 for Timer 0 */
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writel(0x1, &panthtimers->preload_ctrl[TIMER]);
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/* Enable timer 0 */
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writel(0x1, &panthtimers->cer);
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/* init the gd->arch.tbu and gd->arch.tbl value */
|
|
||||||
gd->arch.tbl = read_timer();
|
|
||||||
gd->arch.tbu = 0;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#define MPMU_APRR_WDTR (1<<4)
|
|
||||||
#define TMR_WFAR 0xbaba /* WDT Register First key */
|
|
||||||
#define TMP_WSAR 0xeb10 /* WDT Register Second key */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function uses internal Watchdog Timer
|
|
||||||
* based reset mechanism.
|
|
||||||
* Steps to write watchdog registers (protected access)
|
|
||||||
* 1. Write key value to TMR_WFAR reg.
|
|
||||||
* 2. Write key value to TMP_WSAR reg.
|
|
||||||
* 3. Perform write operation.
|
|
||||||
*/
|
|
||||||
void reset_cpu (unsigned long ignored)
|
|
||||||
{
|
|
||||||
struct panthmpmu_registers *mpmu =
|
|
||||||
(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
|
|
||||||
struct panthtmr_registers *panthtimers =
|
|
||||||
(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
|
|
||||||
u32 val;
|
|
||||||
|
|
||||||
/* negate hardware reset to the WDT after system reset */
|
|
||||||
val = readl(&mpmu->aprr);
|
|
||||||
val = val | MPMU_APRR_WDTR;
|
|
||||||
writel(val, &mpmu->aprr);
|
|
||||||
|
|
||||||
/* reset/enable WDT clock */
|
|
||||||
writel(APBC_APBCLK, &mpmu->wdtpcr);
|
|
||||||
|
|
||||||
/* clear previous WDT status */
|
|
||||||
writel(TMR_WFAR, &panthtimers->wfar);
|
|
||||||
writel(TMP_WSAR, &panthtimers->wsar);
|
|
||||||
writel(0, &panthtimers->wdt_sts);
|
|
||||||
|
|
||||||
/* set match counter */
|
|
||||||
writel(TMR_WFAR, &panthtimers->wfar);
|
|
||||||
writel(TMP_WSAR, &panthtimers->wsar);
|
|
||||||
writel(0xf, &panthtimers->wdt_match_r);
|
|
||||||
|
|
||||||
/* enable WDT reset */
|
|
||||||
writel(TMR_WFAR, &panthtimers->wfar);
|
|
||||||
writel(TMP_WSAR, &panthtimers->wsar);
|
|
||||||
writel(0x3, &panthtimers->wdt_match_en);
|
|
||||||
|
|
||||||
/*enable functional WDT clock */
|
|
||||||
writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function is derived from PowerPC code (read timebase as long long).
|
|
||||||
* On ARM it just returns the timer value.
|
|
||||||
*/
|
|
||||||
unsigned long long get_ticks(void)
|
|
||||||
{
|
|
||||||
return get_timer(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function is derived from PowerPC code (timebase clock frequency).
|
|
||||||
* On ARM it returns the number of timer ticks per second.
|
|
||||||
*/
|
|
||||||
ulong get_tbclk (void)
|
|
||||||
{
|
|
||||||
return (ulong)CONFIG_SYS_HZ;
|
|
||||||
}
|
|
||||||
|
|
@ -1,53 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2011
|
|
||||||
* Marvell Semiconductor <www.marvell.com>
|
|
||||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _PANTHEON_CONFIG_H
|
|
||||||
#define _PANTHEON_CONFIG_H
|
|
||||||
|
|
||||||
#include <asm/arch/pantheon.h>
|
|
||||||
|
|
||||||
/* default Dcache Line length for pantheon */
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
|
||||||
|
|
||||||
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
|
|
||||||
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
|
|
||||||
#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
|
|
||||||
#define MV_MFPR_BASE PANTHEON_MFPR_BASE
|
|
||||||
#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE
|
|
||||||
#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
|
|
||||||
represents UART Unit Enable */
|
|
||||||
/*
|
|
||||||
* I2C definition
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_CMD_I2C
|
|
||||||
#define CONFIG_I2C_MV 1
|
|
||||||
#define CONFIG_MV_I2C_REG 0xd4011000
|
|
||||||
#define CONFIG_HARD_I2C 1
|
|
||||||
#define CONFIG_SYS_I2C_SPEED 0
|
|
||||||
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MMC definition
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_CMD_MMC
|
|
||||||
#define CONFIG_CMD_FAT 1
|
|
||||||
#define CONFIG_MMC 1
|
|
||||||
#define CONFIG_GENERIC_MMC 1
|
|
||||||
#define CONFIG_SDHCI 1
|
|
||||||
#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
|
|
||||||
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
|
|
||||||
#define CONFIG_MMC_SDMA 1
|
|
||||||
#define CONFIG_MV_SDHCI 1
|
|
||||||
#define CONFIG_DOS_PARTITION 1
|
|
||||||
#define CONFIG_EFI_PARTITION 1
|
|
||||||
#define CONFIG_SYS_MMC_NUM 2
|
|
||||||
#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _PANTHEON_CONFIG_H */
|
|
||||||
|
|
@ -1,77 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2011
|
|
||||||
* Marvell Semiconductor <www.marvell.com>
|
|
||||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _PANTHEON_CPU_H
|
|
||||||
#define _PANTHEON_CPU_H
|
|
||||||
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/system.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Main Power Management (MPMU) Registers
|
|
||||||
* Refer Register Datasheet 9.1
|
|
||||||
*/
|
|
||||||
struct panthmpmu_registers {
|
|
||||||
u8 pad0[0x0024];
|
|
||||||
u32 ccgr; /*0x0024*/
|
|
||||||
u8 pad1[0x0200 - 0x024 - 4];
|
|
||||||
u32 wdtpcr; /*0x0200*/
|
|
||||||
u8 pad2[0x1020 - 0x200 - 4];
|
|
||||||
u32 aprr; /*0x1020*/
|
|
||||||
u32 acgr; /*0x1024*/
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Application Power Management (APMU) Registers
|
|
||||||
* Refer Register Datasheet 9.2
|
|
||||||
*/
|
|
||||||
struct panthapmu_registers {
|
|
||||||
u8 pad0[0x0054];
|
|
||||||
u32 sd1; /*0x0054*/
|
|
||||||
u8 pad1[0x00e0 - 0x054 - 4];
|
|
||||||
u32 sd3; /*0x00e0*/
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* APB Clock Reset/Control Registers
|
|
||||||
* Refer Register Datasheet 6.14
|
|
||||||
*/
|
|
||||||
struct panthapb_registers {
|
|
||||||
u32 uart0; /*0x000*/
|
|
||||||
u32 uart1; /*0x004*/
|
|
||||||
u32 gpio; /*0x008*/
|
|
||||||
u8 pad0[0x02c - 0x08 - 4];
|
|
||||||
u32 twsi; /*0x02c*/
|
|
||||||
u8 pad1[0x034 - 0x2c - 4];
|
|
||||||
u32 timers; /*0x034*/
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* CPU Interface Registers
|
|
||||||
* Refer Register Datasheet 4.3
|
|
||||||
*/
|
|
||||||
struct panthcpu_registers {
|
|
||||||
u32 chip_id; /* Chip Id Reg */
|
|
||||||
u32 pad;
|
|
||||||
u32 cpu_conf; /* CPU Conf Reg */
|
|
||||||
u32 pad1;
|
|
||||||
u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
|
|
||||||
u32 pad2;
|
|
||||||
u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
|
|
||||||
u32 mcb_conf; /* MCB Conf Reg */
|
|
||||||
u32 sys_boot_ctl; /* Sytem Boot Control */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Functions
|
|
||||||
*/
|
|
||||||
u32 panth_sdram_base(int);
|
|
||||||
u32 panth_sdram_size(int);
|
|
||||||
int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
|
|
||||||
|
|
||||||
#endif /* _PANTHEON_CPU_H */
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
/*
|
|
||||||
* Based on arch/arm/include/asm/arch-armada100/mfp.h
|
|
||||||
* (C) Copyright 2011
|
|
||||||
* Marvell Semiconductor <www.marvell.com>
|
|
||||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __PANTHEON_MFP_H
|
|
||||||
#define __PANTHEON_MFP_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Frequently used MFP Configuration macros for all PANTHEON family of SoCs
|
|
||||||
*
|
|
||||||
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
|
|
||||||
*/
|
|
||||||
/* UART2 */
|
|
||||||
#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
|
||||||
|
|
||||||
/* More macros can be defined here... */
|
|
||||||
#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
|
|
||||||
#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
|
|
||||||
#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
|
|
||||||
#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
|
|
||||||
#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
|
|
||||||
#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
|
|
||||||
#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
|
||||||
#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
|
||||||
|
|
||||||
#define MFP_PIN_MAX 117
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,38 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2011
|
|
||||||
* Marvell Semiconductor <www.marvell.com>
|
|
||||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _PANTHEON_H
|
|
||||||
#define _PANTHEON_H
|
|
||||||
|
|
||||||
/* Common APB clock register bit definitions */
|
|
||||||
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
|
|
||||||
#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
|
|
||||||
#define APBC_RST (1<<2) /* Reset Generation */
|
|
||||||
/* Functional Clock Selection Mask */
|
|
||||||
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
|
|
||||||
|
|
||||||
/* Common APMU register bit definitions */
|
|
||||||
#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
|
|
||||||
#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
|
|
||||||
#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
|
|
||||||
#define APMU_AXI_RST (1<<0) /* AXI Reset */
|
|
||||||
|
|
||||||
/* Register Base Addresses */
|
|
||||||
#define PANTHEON_DRAM_BASE 0xB0000000
|
|
||||||
#define PANTHEON_TIMER_BASE 0xD4014000
|
|
||||||
#define PANTHEON_WD_TIMER_BASE 0xD4080000
|
|
||||||
#define PANTHEON_APBC_BASE 0xD4015000
|
|
||||||
#define PANTHEON_UART1_BASE 0xD4017000
|
|
||||||
#define PANTHEON_UART2_BASE 0xD4018000
|
|
||||||
#define PANTHEON_GPIO_BASE 0xD4019000
|
|
||||||
#define PANTHEON_MFPR_BASE 0xD401E000
|
|
||||||
#define PANTHEON_MPMU_BASE 0xD4050000
|
|
||||||
#define PANTHEON_APMU_BASE 0xD4282800
|
|
||||||
#define PANTHEON_CPU_BASE 0xD4282C00
|
|
||||||
|
|
||||||
#endif /* _PANTHEON_H */
|
|
||||||
|
|
@ -1,15 +0,0 @@
|
||||||
if TARGET_DKB
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "dkb"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "Marvell"
|
|
||||||
|
|
||||||
config SYS_SOC
|
|
||||||
default "pantheon"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "dkb"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
DKB BOARD
|
|
||||||
M: Lei Wen <leiwen@marvell.com>
|
|
||||||
S: Maintained
|
|
||||||
F: board/Marvell/dkb/
|
|
||||||
F: include/configs/dkb.h
|
|
||||||
F: configs/dkb_defconfig
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
#
|
|
||||||
# (C) Copyright 2011
|
|
||||||
# Marvell Semiconductor <www.marvell.com>
|
|
||||||
# Written-by: Lei Wen <leiwen@marvell.com>
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y := dkb.o
|
|
||||||
|
|
@ -1,85 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2011
|
|
||||||
* Marvell Semiconductor <www.marvell.com>
|
|
||||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <mvmfp.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
#include <asm/arch/mfp.h>
|
|
||||||
#include <asm/arch/cpu.h>
|
|
||||||
#ifdef CONFIG_GENERIC_MMC
|
|
||||||
#include <sdhci.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
int board_early_init_f(void)
|
|
||||||
{
|
|
||||||
u32 mfp_cfg[] = {
|
|
||||||
/* Enable Console on UART2 */
|
|
||||||
MFP47_UART2_RXD,
|
|
||||||
MFP48_UART2_TXD,
|
|
||||||
|
|
||||||
/* I2C */
|
|
||||||
MFP53_CI2C_SCL,
|
|
||||||
MFP54_CI2C_SDA,
|
|
||||||
|
|
||||||
/* MMC1 */
|
|
||||||
MFP_MMC1_DAT7,
|
|
||||||
MFP_MMC1_DAT6,
|
|
||||||
MFP_MMC1_DAT5,
|
|
||||||
MFP_MMC1_DAT4,
|
|
||||||
MFP_MMC1_DAT3,
|
|
||||||
MFP_MMC1_DAT2,
|
|
||||||
MFP_MMC1_DAT1,
|
|
||||||
MFP_MMC1_DAT0,
|
|
||||||
MFP_MMC1_CMD,
|
|
||||||
MFP_MMC1_CLK,
|
|
||||||
MFP_MMC1_CD,
|
|
||||||
MFP_MMC1_WP,
|
|
||||||
|
|
||||||
MFP_EOC /*End of configureation*/
|
|
||||||
};
|
|
||||||
/* configure MFP's */
|
|
||||||
mfp_config(mfp_cfg);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_init(void)
|
|
||||||
{
|
|
||||||
/* arch number of Board */
|
|
||||||
gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB;
|
|
||||||
/* adress of boot parameters */
|
|
||||||
gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_GENERIC_MMC
|
|
||||||
#define I2C_SLAVE_ADDR 0x34
|
|
||||||
#define LDO13_REG 0x28
|
|
||||||
#define LDO_V30 0x6
|
|
||||||
#define LDO_VOLTAGE(x) ((x & 0x7) << 1)
|
|
||||||
#define LDO_EN 0x1
|
|
||||||
int board_mmc_init(bd_t *bd)
|
|
||||||
{
|
|
||||||
ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
|
|
||||||
u8 i, data;
|
|
||||||
|
|
||||||
/* set LDO 13 to 3.0v */
|
|
||||||
data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
|
|
||||||
i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
|
|
||||||
|
|
||||||
for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
|
|
||||||
if (mv_sdh_init(mmc_base_address[i], 0, 0,
|
|
||||||
SDHCI_QUIRK_32BIT_DMA_ADDR))
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,2 +0,0 @@
|
||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_DKB=y
|
|
||||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
||||||
|
|
||||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||||
=================================================================================================
|
=================================================================================================
|
||||||
|
dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
|
||||||
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
|
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
|
||||||
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
|
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
|
||||||
Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
|
Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
|
||||||
|
|
|
||||||
|
|
@ -1,51 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2011
|
|
||||||
* Marvell Semiconductor <www.marvell.com>
|
|
||||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_DKB_H
|
|
||||||
#define __CONFIG_DKB_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Version number information
|
|
||||||
*/
|
|
||||||
#define CONFIG_IDENT_STRING "\nMarvell-TTC DKB"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
|
|
||||||
#define CONFIG_PANTHEON 1 /* SOC Family Name */
|
|
||||||
#define CONFIG_MACH_TTC_DKB 1 /* Machine type */
|
|
||||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
|
|
||||||
#define CONFIG_NR_DRAM_BANKS_MAX 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Commands configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
#define CONFIG_CMD_I2C
|
|
||||||
#define CONFIG_CMD_MMC
|
|
||||||
#undef CONFIG_CMD_NET
|
|
||||||
#undef CONFIG_CMD_NFS
|
|
||||||
/*
|
|
||||||
* mv-common.h should be defined after CMD configs since it used them
|
|
||||||
* to enable certain macros
|
|
||||||
*/
|
|
||||||
#include "mv-common.h"
|
|
||||||
|
|
||||||
#undef CONFIG_ARCH_MISC_INIT
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment variables configurations
|
|
||||||
*/
|
|
||||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
|
|
||||||
#define CONFIG_ENV_SIZE 0x20000 /* 64k */
|
|
||||||
|
|
||||||
#endif /* __CONFIG_DKB_H */
|
|
||||||
Loading…
Reference in a new issue