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ppc4xx: Remove 4xx NAND booting support

Browse source 
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.

This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
This commit is contained in:
Stefan Roese 2014-03-04 15:34:35 +01:00 committed by Tom Rini
parent dc116bd6c4
commit 345b77baca
42 changed files with 15 additions and 1882 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
View file

@ -49,7 +49,6 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void update_rdcc(void)
{
u32 val;
@ -72,7 +71,6 @@ static void update_rdcc(void)
}
}
}
#endif
#if defined(CONFIG_440)
/*
@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);
#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
#if !defined(CONFIG_NAND_SPL)
/*-----------------------------------------------------------------------------+
* sdram_memsize
*-----------------------------------------------------------------------------*/
@ -217,7 +214,6 @@ void board_add_ram_info(int use_default)
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
printf(", CL%d)", val);
}
#endif /* !CONFIG_NAND_SPL */
#if defined(CONFIG_SPD_EEPROM)
@ -2843,16 +2839,6 @@ static void test(void)
*---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
/*
* Only run this SDRAM init code once. For NAND booting
* targets like Kilauea, we call initdram() early from the
* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
* which calls initdram() again. This time the controller
* mustn't be reconfigured again since we're already running
* from SDRAM.
*/
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
#if defined(CONFIG_440)
@ -2969,12 +2955,10 @@ phys_size_t initdram(int board_type)
#endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
@ -3009,13 +2993,10 @@ phys_size_t initdram(int board_type)
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
@ -3062,7 +3043,6 @@ void mtdcr_any(u32 dcr, u32 val)
}
}
#endif /* defined(CONFIG_440) */
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
{

12
arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
View file

@ -27,12 +27,6 @@
#include "ecc.h"
/*
* Only compile the DDR auto-calibration code for NOR boot and
* not for NAND boot (NAND SPL and NAND U-Boot - NUB)
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define MAXBXCF 4
#define SDRAM_RXBAS_SHIFT_1M 20
@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void)
return 0;
}
#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
u32 DQS_autocalibration(void)
{
return 0;
}
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */

4
arch/powerpc/cpu/ppc4xx/Makefile
View file

@ -14,11 +14,7 @@ obj-y += kgdb.o
obj-y += 40x_spd_sdram.o
ifndef CONFIG_NAND_SPL
ifndef CONFIG_NAND_U_BOOT
obj-y += 44x_spd_ddr.o
endif
endif
obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
obj-y += 4xx_pci.o

111
arch/powerpc/cpu/ppc4xx/start.S
View file

@ -182,16 +182,13 @@
.extern ext_bus_cntlr_init
#ifdef CONFIG_NAND_U_BOOT
.extern reconfig_tlb0
#endif
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
@ -205,22 +202,7 @@
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
#endif /* CONFIG_NAND_SPL */
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SPL_BUILD)
/*
* NAND U-Boot image is started from offset 0
*/
.text
#if defined(CONFIG_440)
bl reconfig_tlb0
#endif
GET_GOT
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
#endif
#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
@ -255,9 +237,7 @@
*/
#if defined(CONFIG_440)
#if !defined(CONFIG_NAND_SPL)
.section .bootpg,"ax"
#endif
.globl _start_440
/**************************************************************************/
@ -511,7 +491,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
@ -777,9 +757,6 @@ _start:
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
#ifndef CONFIG_SPL_BUILD
GET_GOT
#endif
@ -787,7 +764,6 @@ _start:
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
#endif
#endif /* CONFIG_440 */
@ -1050,9 +1026,6 @@ _start:
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
@ -1060,13 +1033,11 @@ _start:
bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
@ -1632,7 +1603,7 @@ __440_msr_continue:
blr
function_epilog(dcbz_area)
#endif /* CONFIG_440 */
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_SPL_BUILD */
/*------------------------------------------------------------------------------- */
/* Function: in8 */
@ -1981,75 +1952,3 @@ pll_wait:
blr
function_epilog(mftlb1)
#endif /* CONFIG_440 */
#if defined(CONFIG_NAND_SPL)
/*
* void nand_boot_relocate(dst, src, bytes)
*
* r3 = Destination address to copy code to (in SDRAM)
* r4 = Source address to copy code from
* r5 = size to copy in bytes
*/
nand_boot_relocate:
mr r6,r3
mr r7,r4
mflr r8
/*
* Copy SPL from icache into SDRAM
*/
subi r3,r3,4
subi r4,r4,4
srwi r5,r5,2
mtctr r5
..spl_loop:
lwzu r0,4(r4)
stwu r0,4(r3)
bdnz ..spl_loop
/*
* Calculate "corrected" link register, so that we "continue"
* in execution in destination range
*/
sub r3,r7,r6 /* r3 = src - dst */
sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
mtlr r8
blr
nand_boot_common:
/*
* First initialize SDRAM. It has to be available *before* calling
* nand_boot().
*/
lis r3,CONFIG_SYS_SDRAM_BASE@h
ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
bl initdram
/*
* Now copy the 4k SPL code into SDRAM and continue execution
* from there.
*/
lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
bl nand_boot_relocate
/*
* We're running from SDRAM now!!!
*
* It is necessary for 4xx systems to relocate from running at
* the original location (0xfffffxxx) to somewhere else (SDRAM
* preferably). This is because CS0 needs to be reconfigured for
* NAND access. And we can't reconfigure this CS when currently
* "running" from it.
*/
/*
* Finally call nand_boot() to load main NAND U-Boot image from
* NAND and jump to it.
*/
bl nand_boot /* will not return */
#endif /* CONFIG_NAND_SPL */

13
board/amcc/acadia/memory.c
View file

@ -17,7 +17,6 @@
extern void board_pll_init_f(void);
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val)
return;
}
#endif
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
@ -88,7 +76,6 @@ phys_size_t initdram(int board_type)
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
#endif
return (CONFIG_SYS_MBYTES_RAM << 20);
}

42
board/amcc/acadia/pll.c
View file

@ -135,45 +135,3 @@ void board_pll_init_f(void)
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk(void)
{
unsigned long cpr_plld;
unsigned long cpr_primad;
unsigned long primad_cpudv;
unsigned long pllFbkDiv;
unsigned long freqProcessor;
/*
* Read PLL Mode registers
*/
mfcpr(CPR0_PLLD, cpr_plld);
/*
* Read CPR_PRIMAD register
*/
mfcpr(CPR0_PRIMAD, cpr_primad);
/*
* Determine CPU clock frequency
*/
primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
if (primad_cpudv == 0)
primad_cpudv = 16;
/*
* Determine FBK_DIV.
*/
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
if (pllFbkDiv == 0)
pllFbkDiv = 256;
freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
return (freqProcessor);
}
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */

17
board/amcc/bamboo/bamboo.c
View file

@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
/*************************************************************************
*
* Bamboo has one bank onboard sdram (plus DIMM)
@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
0,
0
};
#endif
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
@ -440,15 +438,11 @@ int checkboard(void)
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
dram_size = spd_sdram();
return dram_size;
#else
return CONFIG_SYS_MBYTES_SDRAM << 20;
#endif
}
/*----------------------------------------------------------------------------+
@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
update_ndfc_ios(gpio_tab);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
#else
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN0 |
SDR0_CUST0_CHIPSELGAT_EN2);
#endif
ndfc_selection_in_fpga();
}
else

33
board/amcc/bamboo/init.S
View file

@ -32,12 +32,7 @@ tlbtab:
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
#else
tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
@ -58,31 +53,3 @@ tlbtab:
tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,0x0000 /* TLB entry #0 */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif

4
board/amcc/canyonlands/canyonlands.c
View file

@ -379,11 +379,7 @@ int board_early_init_r (void)
*/
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);

34
board/amcc/canyonlands/init.S
View file

@ -31,13 +31,7 @@ tlbtab:
* use the speed up boot process. It is patched after relocation to
* enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
#else
tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
#endif
/*
* TLB entries for SDRAM are not needed on this platform.
@ -95,31 +89,3 @@ tlbtab:
#endif
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,0x0000 /* TLB entry #0 */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif

32
board/amcc/sequoia/init.S
View file

@ -48,11 +48,7 @@ tlbtab:
/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#else
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
#endif
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
@ -81,31 +77,3 @@ tlbtab:
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif

13
board/amcc/sequoia/sdram.c
View file

@ -26,14 +26,6 @@
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
#if defined(CONFIG_NAND_SPL)
/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
#define get_bus_freq(val) 133333333
#endif
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void);
************************************************************************/
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
@ -81,7 +72,7 @@ phys_size_t initdram (int board_type)
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */
#endif /* #ifndef CONFIG_SYS_RAMBOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+

10
board/amcc/sequoia/sequoia.c
View file

@ -142,8 +142,7 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
@ -151,8 +150,7 @@ int misc_init_r(void)
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
@ -360,7 +358,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
#endif
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
@ -411,4 +409,4 @@ void ft_board_setup(void *blob, bd_t *bd)
return;
}
}
#endif /* CONFIG_NAND_U_BOOT */
#endif /* CONFIG_SYS_RAMBOOT */

32
board/esd/pmc440/init.S
View file

@ -27,11 +27,7 @@ tlbtab:
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#else
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
#endif
/* TLB entries for DDR2 SDRAM are generated dynamically */
@ -71,31 +67,3 @@ tlbtab:
/* TODO: what about high IO space */
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,0x0000 /* TLB entry #0 */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif

8
board/esd/pmc440/pmc440.c
View file

@ -229,19 +229,11 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(EBC0_CFGADDR, PB2CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(EBC0_CFGADDR, PB2CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
mtdcr(EBC0_CFGDATA, pbcr);
/*

8
boards.cfg
View file

@ -1121,22 +1121,14 @@ Active powerpc ppc4xx - amcc -
Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc - yucca - -
Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>

13
drivers/mtd/nand/ndfc.c
View file

@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
*p++ = in_be32((u32 *)(base + NDFC_DATA));
}
#ifndef CONFIG_NAND_SPL
/*
* Don't use these speedup functions in NAND boot image, since the image
* has to fit into 4kByte.
@ -148,8 +147,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd)
}
#endif /* #ifndef CONFIG_NAND_SPL */
void board_nand_select_device(struct nand_chip *nand, int chip)
{
/*
@ -207,21 +204,11 @@ int board_nand_init(struct nand_chip *nand)
nand->options |= NAND_BUSWIDTH_16;
#endif
#ifndef CONFIG_NAND_SPL
nand->write_buf = ndfc_write_buf;
nand->verify_buf = ndfc_verify_buf;
nand->read_byte = ndfc_read_byte;
chip++;
#else
/*
* Setup EBC (CS0 only right now)
*/
mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
#endif
return 0;
}

75
include/configs/PMC440.h
View file

@ -95,12 +95,7 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* RTC
@ -142,69 +137,10 @@
#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
#endif
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
#if defined (CONFIG_NAND_U_BOOT)
#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 16
#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
#endif
#ifdef CONFIG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
@ -448,7 +384,6 @@
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
@ -458,16 +393,6 @@
/* Memory Bank 2 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x018003c0
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
#else
#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 2 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x03017200
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000)
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x018003c0
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
#endif
/* Memory Bank 1 (RESET) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */

99
include/configs/acadia.h
View file

@ -82,17 +82,11 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
@ -106,16 +100,6 @@
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#else
/*
* No NOR-flash on Acadia when NAND-booting. We need to undef the
* NOR device-tree fixup code as well, since flash_info is not defined
* in this case.
*/
#define CONFIG_SYS_NO_FLASH 1
#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
@ -126,61 +110,6 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 16
#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
#ifdef CONFIG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
@ -219,7 +148,6 @@
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
"kozio=bootm ffc60000\0" \
@ -242,14 +170,6 @@
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB
/*
* No NOR on Acadia when NAND-booting
*/
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#endif
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
@ -260,7 +180,6 @@
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 3
/* Memory Bank 0 (Flash) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03337200
@ -278,24 +197,6 @@
/* Memory Bank 2 (CRAM) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x030400c0
#define CONFIG_SYS_EBC_PB2CR 0x020bc000
#else
#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x018003c0
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
/*
* When NAND-booting the CRAM EBC setup must be done in sync mode, since the
* NAND-SPL already initialized the CRAM and EBC to sync mode.
*/
/* Memory Bank 1 (CRAM) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
#define CONFIG_SYS_EBC_PB1CR 0x000bc000
/* Memory Bank 2 (CRAM) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
#define CONFIG_SYS_EBC_PB2CR 0x020bc000
#endif
/* Memory Bank 4 (CPLD) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x04006000

6
include/configs/amcc-common.h
View file

@ -253,10 +253,4 @@
"cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
"u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\
"nload=tftp 200000 ${u-boot-nand}\0" \
"nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \
"nupd=run nload nupdate\0"
#endif /* __AMCC_COMMON_H */

69
include/configs/bamboo.h
View file

@ -86,12 +86,7 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* FLASH related
@ -120,61 +115,6 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 16
#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
#ifdef CONFIG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
@ -182,15 +122,7 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 1
#else
#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x018003c0
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
@ -226,7 +158,6 @@
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
""

82
include/configs/canyonlands.h
View file

@ -125,78 +125,9 @@
/*
* Define here the location of the environment variables (FLASH).
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*
* This is the first official implementation of booting from 2k page sized
* NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
*/
#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
/* this addr */
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
/* NAND chip page count */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/
#define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63}
#ifdef CONFIG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
*/
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* FLASH related
@ -235,7 +166,6 @@
/*------------------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT)
#if !defined(CONFIG_ARCHES)
/*
* NAND booting U-Boot version uses a fixed initialization, since the whole
@ -308,7 +238,6 @@
#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
#endif /* !defined(CONFIG_ARCHES) */
#endif /* !defined(CONFIG_NAND_U_BOOT) */
#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
@ -421,7 +350,6 @@
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
@ -556,15 +484,6 @@
* 0xfe00.0000 -> 4.ce00.0000
*/
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
/* Memory Bank 3 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x10055e00
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x018003c0
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
#else
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x10055e00
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
@ -574,7 +493,6 @@
#define CONFIG_SYS_EBC_PB3AP 0x018003c0
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
#endif
#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
#if !defined(CONFIG_ARCHES)
/* Memory Bank 2 (CPLD) initialization */

85
include/configs/kilauea.h
View file

@ -118,12 +118,7 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* FLASH related
@ -151,61 +146,6 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 405EX the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from location 0xfffff000...0xffffffff the
* NAND controller cannot be accessed since it is attached to CS0 too.
*/
#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 16
#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
#ifdef CONFIG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
@ -230,11 +170,9 @@
*
* DDR Autocalibration Method_B is the default.
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
#endif
#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
@ -416,7 +354,6 @@
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"logversion=2\0" \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
@ -434,16 +371,7 @@
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
/*
* Don't run the memory POST on the NAND-booting version. It will
* overwrite part of the U-Boot image which is already loaded from NAND
* to SDRAM.
*/
#if defined(CONFIG_NAND_U_BOOT)
#define CONFIG_SYS_POST_MEMORY_ON 0
#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
#endif
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
@ -494,18 +422,6 @@
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
/* booting from NAND, so NAND chips select has to be on CS 0 */
#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 1 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x05806500
#define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x018003c0
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
#else
#define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
@ -515,7 +431,6 @@
/* Memory Bank 1 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x018003c0
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
#endif
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \

1
include/configs/redwood.h
View file

@ -120,7 +120,6 @@
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \

70
include/configs/sequoia.h
View file

@ -97,10 +97,7 @@
/*
* Environment
*/
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
#elif defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
#define CONFIG_ENV_SIZE (8 << 10)
/*
@ -148,68 +145,11 @@
#endif
#endif /* CONFIG_CMD_FLASH */
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
/* this addr */
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 16
#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
#ifdef CONFIG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif
/*
* DDR SDRAM
*/
#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SYS_RAMBOOT)
#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
@ -247,7 +187,6 @@
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
""
@ -321,7 +260,7 @@
* overwrite part of the U-Boot image which is already loaded from NAND
* to SDRAM.
*/
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_POST_MEMORY_ON 0
#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
@ -370,8 +309,7 @@
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SYS_RAMBOOT)
#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03017200

88
nand_spl/board/amcc/acadia/Makefile
View file

@ -1,88 +0,0 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o cache.o
COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
targets += $(__OBJS)
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
$(nandobj)System.map
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)System.map: $(nandobj)u-boot-spl
@$(NM) $< | \
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
sort > $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)/cache.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
$(obj)/gpio.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@
$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)/memory.c:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@
$(obj)/pll.c:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@
# from nand_spl directory
$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@

31
nand_spl/board/amcc/acadia/config.mk
View file

@ -1,31 +0,0 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# AMCC 405EZ Reference Platform (Acadia) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
CONFIG_SYS_TEXT_BASE = 0xf8004000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0xf8008000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

48
nand_spl/board/amcc/acadia/u-boot.lds
View file

@ -1,48 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc:common)
SECTIONS
{
.resetvec 0xf8004ffc :
{
KEEP(*(.resetvec))
} = 0xffff
.text :
{
start.o (.text)
nand_boot.o (.text)
ndfc.o (.text)
*(.text)
*(.fixup)
}
_etext = .;
.data :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
*(.data*)
*(.sdata*)
__got2_start = .;
*(.got2)
__got2_end = .;
}
_edata = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss)
*(.bss)
. = ALIGN(4);
}
__bss_end = . ;
}

70
nand_spl/board/amcc/bamboo/Makefile
View file

@ -1,70 +0,0 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
targets += $(__OBJS)
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)/init.S:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@
# from nand_spl directory
$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@

33
nand_spl/board/amcc/bamboo/config.mk
View file

@ -1,33 +0,0 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# AMCC 440EP Reference Platform (Bamboo) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into instruction-cache in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in i-cache here.
#
CONFIG_SYS_TEXT_BASE = 0x00800000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0x00804000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

76
nand_spl/board/amcc/bamboo/sdram.c
View file

@ -1,76 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
static void wait_init_complete(void)
{
u32 val;
do {
mfsdram(SDRAM0_MCSTS, val);
} while (!(val & 0x80000000));
}
/*
* phys_size_t initdram(int board_type)
*
* As the name already indicates, this function is called very early
* from start.S and configures the SDRAM with fixed values. This is needed,
* since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
* not enough free space to implement the complete I2C SPD DDR autodetection
* routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
* when booting from NAND flash.
*
* Note:
* As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
* DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
* modules are still plugged in. So it is recommended to remove the DIMM
* modules while using the NAND booting code with the fixed SDRAM setup!
*/
phys_size_t initdram(int board_type)
{
/*
* Soft-reset SDRAM controller.
*/
mtsdr(SDR0_SRST, SDR0_SRST_DMC);
mtsdr(SDR0_SRST, 0x00000000);
/*
* Disable memory controller.
*/
mtsdram(SDRAM0_CFG0, 0x00000000);
/*
* Setup some default
*/
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(SDRAM0_B0CR, 0x00082001);
mtsdram(SDRAM0_TR0, 0x41094012);
mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
/*
* Enable the controller, then wait for DCEN to complete
*/
mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
wait_init_complete();
return CONFIG_SYS_MBYTES_SDRAM << 20;
}

50
nand_spl/board/amcc/bamboo/u-boot.lds
View file

@ -1,50 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc:common)
SECTIONS
{
.resetvec 0x00800FFC :
{
KEEP(*(.resetvec))
} = 0xffff
.text :
{
start.o (.text)
init.o (.text)
nand_boot.o (.text)
sdram.o (.text)
ndfc.o (.text)
*(.text)
*(.fixup)
}
_etext = .;
.data :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
*(.data*)
*(.sdata*)
__got2_start = .;
*(.got2)
__got2_end = .;
}
_edata = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss)
*(.bss)
. = ALIGN(4);
}
__bss_end = . ;
}

75
nand_spl/board/amcc/canyonlands/Makefile
View file

@ -1,75 +0,0 @@
#
# (C) Copyright 2008
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
ccflags-y += -DCONFIG_NAND_SPL
SOBJS := start.o
SOBJS += init.o
SOBJS += resetvec.o
COBJS := ddr2_fixed.o
COBJS += nand_boot.o
COBJS += nand_ecc.o
COBJS += ndfc.o
OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
targets += $(__OBJS)
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)/init.S:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@
# from nand_spl directory
$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@

33
nand_spl/board/amcc/canyonlands/config.mk
View file

@ -1,33 +0,0 @@
#
# (C) Copyright 2008
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# AMCC 460EX Reference Platform (Canyonlands) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
CONFIG_SYS_TEXT_BASE = 0xE3003000
# PAD_TO used to generate a 128kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000
PAD_TO = 0xE3023000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

130
nand_spl/board/amcc/canyonlands/ddr2_fixed.c
View file

@ -1,130 +0,0 @@
/*
* (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/io.h>
#include <asm/processor.h>
/*
* This code can configure those two Crucial SODIMM's:
*
* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
*
*/
#define TEST_ADDR 0x10000000
#define TEST_MAGIC 0x11223344
static void wait_init_complete(void)
{
u32 val;
do {
mfsdram(SDRAM_MCSTAT, val);
} while (!(val & 0x80000000));
}
static void ddr_start(void)
{
mtsdram(SDRAM_MCOPT2, 0x28000000);
wait_init_complete();
}
static void ddr_init_common(void)
{
/*
* Reset the DDR-SDRAM controller.
*/
mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
mtsdr(SDR0_SRST, 0x00000000);
/*
* These values are cloned from a running NOR booting
* Canyonlands with SPD-DDR2 detection and calibration
* enabled. This will only work for the same memory
* configuration as used here:
*
*/
mtsdram(SDRAM_MCOPT2, 0x00000000);
mtsdram(SDRAM_MODT0, 0x01000000);
mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243);
mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
mtsdram(SDRAM_MMODE, 0x00000632);
mtsdram(SDRAM_MEMODE, 0x00000040);
mtsdram(SDRAM_INITPLR0, 0xB5380000);
mtsdram(SDRAM_INITPLR1, 0x82100400);
mtsdram(SDRAM_INITPLR2, 0x80820000);
mtsdram(SDRAM_INITPLR3, 0x80830000);
mtsdram(SDRAM_INITPLR4, 0x80810040);
mtsdram(SDRAM_INITPLR5, 0x80800532);
mtsdram(SDRAM_INITPLR6, 0x82100400);
mtsdram(SDRAM_INITPLR7, 0x8A080000);
mtsdram(SDRAM_INITPLR8, 0x8A080000);
mtsdram(SDRAM_INITPLR9, 0x8A080000);
mtsdram(SDRAM_INITPLR10, 0x8A080000);
mtsdram(SDRAM_INITPLR11, 0x80000432);
mtsdram(SDRAM_INITPLR12, 0x808103C0);
mtsdram(SDRAM_INITPLR13, 0x80810040);
mtsdram(SDRAM_RDCC, 0x40000000);
mtsdram(SDRAM_RQDC, 0x80000038);
mtsdram(SDRAM_RFDC, 0x00000257);
mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
}
phys_size_t initdram(int board_type)
{
/*
* First try init for this module:
*
* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
*/
ddr_init_common();
/*
* Crucial CT6464AC667.8FB - 512MB SO-DIMM
*/
mtdcr(SDRAM_R0BAS, 0x0000F800);
mtdcr(SDRAM_R1BAS, 0x0400F800);
mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_MB1CF, 0x00000201);
ddr_start();
/*
* Now test if the dual-ranked module is really installed
* by checking an address in the upper 256MByte region
*/
out_be32((void *)TEST_ADDR, TEST_MAGIC);
if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
/*
* The test failed, so we assume that the single
* ranked module is installed:
*
* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
*/
ddr_init_common();
mtdcr(SDRAM_R0BAS, 0x0000F000);
mtsdram(SDRAM_MCOPT1, 0x05322000);
mtsdram(SDRAM_CODT, 0x00800021);
ddr_start();
}
return CONFIG_SYS_MBYTES_SDRAM << 20;
}

50
nand_spl/board/amcc/canyonlands/u-boot.lds
View file

@ -1,50 +0,0 @@
/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc:common)
SECTIONS
{
.resetvec 0xE3003FFC :
{
KEEP(*(.resetvec))
} = 0xffff
.text :
{
start.o (.text)
init.o (.text)
nand_boot.o (.text)
ddr2_fixed.o (.text)
ndfc.o (.text)
*(.text)
*(.fixup)
}
_etext = .;
.data :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
*(.data*)
*(.sdata*)
__got2_start = .;
*(.got2)
__got2_end = .;
}
_edata = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss)
*(.bss)
. = ALIGN(4);
}
__bss_end = . ;
}

77
nand_spl/board/amcc/kilauea/Makefile
View file

@ -1,77 +0,0 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o cache.o
COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
targets += $(__OBJS)
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)/44x_spd_ddr2.c: $(obj)/ecc.h
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@
$(obj)/cache.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
$(obj)/ecc.h:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@
$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from nand_spl directory
$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/nand directory
$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@

32
nand_spl/board/amcc/kilauea/config.mk
View file

@ -1,32 +0,0 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# AMCC 405EX Reference Platform (Kilauea) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into SDRAM since we can't access the NAND
# controller at CS0 while running from this location. So we set
# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here.
#
CONFIG_SYS_TEXT_BASE = 0x00800000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0x00804000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

48
nand_spl/board/amcc/kilauea/u-boot.lds
View file

@ -1,48 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc:common)
SECTIONS
{
.resetvec 0x00800FFC :
{
KEEP(*(.resetvec))
} = 0xffff
.text :
{
start.o (.text)
nand_boot.o (.text)
ndfc.o (.text)
*(.text)
*(.fixup)
}
_etext = .;
.data :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
*(.data*)
*(.sdata*)
__got2_start = .;
*(.got2)
__got2_end = .;
}
_edata = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss)
*(.bss)
. = ALIGN(4);
}
__bss_end = . ;
}

80
nand_spl/board/amcc/sequoia/Makefile
View file

@ -1,80 +0,0 @@
#
# (C) Copyright 2006-2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
targets += $(__OBJS)
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)/denali_data_eye.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@
$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
$(obj)/init.S:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@
$(obj)/sdram.c:
@rm -f $@
@rm -f $(obj)/sdram.h
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)/sdram.h
# from nand_spl directory
$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@

33
nand_spl/board/amcc/sequoia/config.mk
View file

@ -1,33 +0,0 @@
#
# (C) Copyright 2006
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# AMCC 440EPx Reference Platform (Sequoia) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
CONFIG_SYS_TEXT_BASE = 0xE0013000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0xE0017000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

50
nand_spl/board/amcc/sequoia/u-boot.lds
View file

@ -1,50 +0,0 @@
/*
* (C) Copyright 2006-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc:common)
SECTIONS
{
.resetvec 0xE0013FFC :
{
KEEP(*(.resetvec))
} = 0xffff
.text :
{
start.o (.text)
init.o (.text)
nand_boot.o (.text)
sdram.o (.text)
ndfc.o (.text)
*(.text)
*(.fixup)
}
_etext = .;
.data :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
*(.data*)
*(.sdata*)
__got2_start = .;
*(.got2)
__got2_end = .;
}
_edata = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss)
*(.bss)
. = ALIGN(4);
}
__bss_end = . ;
}