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sunxi: boot0.h: allow RVBAR MMIO address customisation
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need to program the 64-bit start code address into an MMIO mapped register that shadows the architectural RVBAR register. This address is SoC specific, with just two versions out there so far. Now a third address emerged, on a *variant* of an existing SoC (H616). Change the boot0.h start code to make this address a Kconfig selectable option, to allow easier maintenance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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2 changed files with 14 additions and 5 deletions
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@ -39,11 +39,8 @@
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.word 0xf57ff06f // isb sy
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.word 0xf57ff06f // isb sy
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.word 0xe320f003 // wfi
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.word 0xe320f003 // wfi
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.word 0xeafffffd // b @wfi
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.word 0xeafffffd // b @wfi
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#ifndef CONFIG_SUN50I_GEN_H6
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.word 0x017000a0 // writeable RVBAR mapping address
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.word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr
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#else
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.word 0x09010040 // writeable RVBAR mapping address
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#endif
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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.word CONFIG_SPL_TEXT_BASE
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.word CONFIG_SPL_TEXT_BASE
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#else
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#else
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@ -129,6 +129,18 @@ config SUNXI_SRAM_ADDRESS
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Some newer SoCs map the boot ROM at address 0 instead and move the
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Some newer SoCs map the boot ROM at address 0 instead and move the
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SRAM to a different address.
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SRAM to a different address.
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config SUNXI_RVBAR_ADDRESS
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hex
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depends on ARM64
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default 0x09010040 if SUN50I_GEN_H6
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default 0x017000a0
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---help---
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The read-only RVBAR system register holds the address of the first
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instruction to execute after a reset. Allwinner cores provide a
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writable MMIO backing store for this register, to allow to set the
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entry point when switching to AArch64. This store is on different
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addresses, depending on the SoC.
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config SUNXI_A64_TIMER_ERRATUM
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config SUNXI_A64_TIMER_ERRATUM
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bool
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bool
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