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Patch by Denis Peter, 19 Mai 2003:

Browse source 
add support for the MIP405-3 board
This commit is contained in:
wdenk 2003-05-23 11:38:58 +00:00
parent 9919f13cc1
commit 33149b8812
12 changed files with 429 additions and 6237 deletions
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3
CHANGELOG
View file

@ -2,6 +2,9 @@
Changes since U-Boot 0.3.1:
======================================================================
* Patch by Denis Peter, 19 Mai 2003:
add support for the MIP405-3 board
* Patch by Dave Ellis, 22 May 2003:
Fix problem with only partially cleared .bss segment

110
board/mpl/common/common_util.c
View file

@ -32,6 +32,15 @@
#include <devices.h>
#include <pci.h>
#ifdef CONFIG_PIP405
#include "../pip405/pip405.h"
#include <405gp_pci.h>
#endif
#ifdef CONFIG_MIP405
#include "../mip405/mip405.h"
#include <405gp_pci.h>
#endif
extern int gunzip (void *, int, unsigned char *, int *);
extern int mem_test(unsigned long start, unsigned long ramsize, int quiet);
@ -363,12 +372,16 @@ void show_stdio_dev(void)
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
int switch_cs(unsigned char boot)
{
unsigned long pbcr;
mtdcr(ebccfga, pb0cr); /* get cs0 config reg */
pbcr = mfdcr(ebccfgd);
if((pbcr&0x00002000)==0) {
unsigned long pbcr;
int mode;
mode=get_boot_mode();
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
if (mode & BOOT_MPS) {
/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
/* we need only to switch if boot from MPS */
/*printf(" MPS boot mode detected. ");*/
/* printf(" MPS boot mode detected. ");*/
/* printf("cs0 cfg: %lx\n",pbcr); */
if(boot) {
/* switch to boot configuration */
@ -388,8 +401,7 @@ int switch_cs(unsigned char boot)
mtdcr(ebccfgd, pbcr);
SW_CS_PRINTF(" new cs1 cfg: %lx, MPS is on High Address\n",pbcr);
}
else
{
else {
/* map flash to boot area, */
SW_CS_PRINTF("map Flash to boot area\n");
pbcr&=0x000FFFFF; /*mask base address of the cs0 */
@ -412,7 +424,63 @@ int switch_cs(unsigned char boot)
SW_CS_PRINTF("Normal boot, no switching necessary\n");
return 0;
}
}
int get_boot_mode(void)
{
unsigned long pbcr;
int res = 0;
pbcr = mfdcr (strap);
if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
/* boot via MPS or MPS mapping */
res = BOOT_MPS;
if(pbcr & PSR_ROM_LOC)
/* boot via PCI.. */
res |= BOOT_PCI;
return res;
}
/* Setup cs0 parameter finally.
Map the flash high (in boot area)
This code can only be executed from SDRAM (after relocation).
*/
void setup_cs_reloc(void)
{
unsigned long pbcr;
/* Since we are relocated, we can set-up the CS finaly
* but first of all, switch off PCI mapping (in case it was a PCI boot) */
out32r(PMM0MA,0L);
icache_enable (); /* we are relocated */
/* for PCI Boot, we have to set-up the remaining CS correctly */
pbcr = mfdcr (strap);
if(pbcr & PSR_ROM_LOC) {
/* boot via PCI.. */
if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) {
/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
#ifdef DEBUG
printf("Mapping MPS to CS0 @ 0x%lx\n",(MPS_CR_B & 0xfff00000));
#endif
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, MPS_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, MPS_CR_B);
}
else {
/* Flash boot, set up the Flash on CS0 */
#ifdef DEBUG
printf("Mapping Flash to CS0 @ 0x%lx\n",(FLASH_CR_B & 0xfff00000));
#endif
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, FLASH_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, FLASH_CR_B);
}
}
switch_cs(0); /* map Flash High */
}
#elif defined(CONFIG_VCMA9)
int switch_cs(unsigned char boot)
{
@ -425,13 +493,11 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong size,src,ld_addr;
int result;
backup_t back;
char sw;
src = MULTI_PURPOSE_SOCKET_ADDR;
size = IMAGE_SIZE;
if (strcmp(argv[1], "flash") == 0)
{
sw = switch_cs(0); /* Switch flash to normal location */
#if (CONFIG_COMMANDS & CFG_CMD_FDC)
if (strcmp(argv[2], "floppy") == 0) {
char *local_args[3];
@ -450,7 +516,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
result=do_fdcboot(cmdtp, 0, 1, local_args);
}
result=mpl_prg_image(ld_addr);
switch_cs(sw); /* Switch flash back */
return result;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_FDC) */
@ -463,17 +528,13 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf ("\nupdating bootloader image from memory at %lX\n",ld_addr);
result=mpl_prg_image(ld_addr);
switch_cs(sw); /* Switch flash back */
return result;
}
if (strcmp(argv[2], "mps") == 0) {
printf ("\nupdating bootloader image from MSP\n");
printf ("\nupdating bootloader image from MPS\n");
result=mpl_prg(src,size);
switch_cs(sw); /* Switch flash back */
return result;
}
switch_cs(sw); /* Switch flash back */
}
if (strcmp(argv[1], "mem") == 0)
{
@ -551,11 +612,12 @@ void video_get_info_str (int line_number, char *info)
DECLARE_GLOBAL_DATA_PTR;
PPC405_SYS_INFO sys_info;
char rev;
int i;
int i,boot;
unsigned long pvr;
char buf[64];
char tmp[16];
unsigned char *s, *e, bc, sw;
char cpustr[16];
unsigned char *s, *e, bc;
switch (line_number)
{
case 2:
@ -567,8 +629,13 @@ void video_get_info_str (int line_number, char *info)
case PVR_405GP_RC: rev='C'; break;
case PVR_405GP_RD: rev='D'; break;
case PVR_405GP_RE: rev='E'; break;
case PVR_405GPR_RB: rev='B'; break;
default: rev='?'; break;
}
if(pvr==PVR_405GPR_RB)
sprintf(cpustr,"PPC405GPr %c",rev);
else
sprintf(cpustr,"PPC405GP %c",rev);
/* Board info */
i=0;
s=getenv ("serial#");
@ -601,22 +668,21 @@ void video_get_info_str (int line_number, char *info)
}
buf[i++]=0;
}
sprintf (info," %s PPC405GP %c %s MHz (%lu/%lu/%lu MHz)",
buf,rev,
sprintf (info," %s %s %s MHz (%lu/%lu/%lu MHz)",
buf, cpustr,
strmhz (tmp, gd->cpu_clk), sys_info.freqPLB / 1000000,
sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
return;
case 3:
/* Memory Info */
sw = switch_cs (0);
switch_cs (sw);
boot = get_boot_mode();
bc = in8 (CONFIG_PORT_ADDR);
sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s",
gd->bd->bi_memsize / 0x100000,
gd->bd->bi_flashsize / 0x100000,
bc,
sw ? "MPS boot" : "Flash boot",
(boot & BOOT_MPS) ? "MPS boot" : "Flash boot",
ctfb.modeIdent);
return;
case 1:

9
board/mpl/common/common_util.h
View file

@ -27,11 +27,18 @@
typedef struct {
char signature[4];
char serial_name[17]; /* "MIP405_1000xxxxx" */
char eth_addr[21]; /* "00:60:C2:0a:00:00" */
char eth_addr[21]; /* "00:60:C2:0a:00:00" */
} backup_t;
void get_backup_values(backup_t *buf);
int switch_cs(unsigned char boot);
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
int get_boot_mode(void);
void setup_cs_reloc(void);
#define BOOT_MPS 0x01
#define BOOT_PCI 0x02
#endif
void show_stdio_dev(void);
void check_env(void);
#if (CONFIG_COMMANDS & CFG_CMD_DOC)

360
board/mpl/common/flash.c
View file

@ -30,7 +30,7 @@
/*
* Modified 3/7/2001
* - adopted for pip405, Denis Peter, MPL AG Switzerland
* - adapted for pip405, Denis Peter, MPL AG Switzerland
* TODO:
* clean-up
*/
@ -38,12 +38,6 @@
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#ifdef CONFIG_PIP405
#include "../pip405/pip405.h"
#endif
#ifdef CONFIG_MIP405
#include "../mip405/mip405.h"
#endif
#include "common_util.h"
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
@ -52,23 +46,10 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
#ifdef CONFIG_ADCIOP
#define ADDR0 0x0aa9
#define ADDR1 0x0556
#define FLASH_WORD_SIZE unsigned char
#endif
#ifdef CONFIG_CPCI405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned short
#endif
#ifdef CONFIG_PIP405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
@ -92,16 +73,17 @@ unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
unsigned long pbcr;
unsigned long base_b0, base_b1;
unsigned char rc;
rc=switch_cs(FALSE); /* map Flash High */
if(rc)
printf("(MPS Boot) ");
/* Since we are relocated, we can set-up the CS finally */
setup_cs_reloc();
/* get and display boot mode */
i=get_boot_mode();
if(i & BOOT_PCI)
printf("(PCI Boot %s Map) ",(i & BOOT_MPS) ?
"MPS" : "Flash");
else
printf("(Flash Boot) ");
printf("(%s Boot) ",(i & BOOT_MPS) ?
"MPS" : "Flash");
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
@ -115,140 +97,39 @@ unsigned long flash_init (void)
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1)
{
/* Setup offsets */
/* flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); */
/* Monitor protection ON by default */
/* protect the bootloader */
/* Monitor protection ON by default */
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
#endif
size_b1 = 0 ;
flash_info[0].size = size_b0;
}
/* 2 banks */
else
{
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1)
{
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
}
if (size_b0)
{
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b0+size_b0-CFG_MONITOR_LEN,
base_b0+size_b0-1,
&flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1+size_b1-CFG_MONITOR_LEN,
base_b1+size_b1-1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0+size_b0-CFG_MONITOR_LEN,
base_b0+size_b0-1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
}/* else 2 banks */
switch_cs(rc); /* switch mode back */
return (size_b0 + size_b1);
}
static void flash_get_offsets (ulong base, flash_info_t *info)
{
return;
}
size_b1 = 0 ;
flash_info[0].size = size_b0;
#if 0
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)){
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
}
else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* include this if you want to test if
the relocation has be done ok.
This will disable both Chipselects */
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, 0L);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, 0L);
printf("CS0 & CS1 switched off for test\n");
#endif
return (size_b0);
}
#endif
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
@ -297,40 +178,30 @@ void flash_print_info (flash_info_t *info)
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++) {
if (*flash++ != 0xffffffff) {
erased = 0;
break;
}
}
}
if ((i % 5) == 0)
printf ("\n ");
#if 0 /* test-only */
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
#else
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " "
#endif
);
info->protect[i] ? "RO " : " ");
}
printf ("\n");
}
/*-----------------------------------------------------------------------
@ -457,21 +328,22 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)){
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)){
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
}
else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
if(info->sector_count==71) {
@ -501,52 +373,41 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
#if 0 /* test-only */
#ifdef CONFIG_ADCIOP
addr2 = (volatile unsigned char *)info->start[0];
addr2[ADDR0] = 0xAA;
addr2[ADDR1] = 0x55;
addr2[ADDR0] = 0xF0; /* reset bank */
#else
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
#endif
#else /* test-only */
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
#endif /* test-only */
}
return (info->size);
}
int wait_for_DQ7(flash_info_t *info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
return 0;
}
@ -555,20 +416,20 @@ int intel_wait_for_DQ7(flash_info_t *info, int sect)
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
addr[0]=(FLASH_WORD_SIZE)0x00500050;
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
addr[0]=(FLASH_WORD_SIZE)0x00500050;
return 0;
}
@ -621,7 +482,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
/* printf("Erasing sector %p\n", addr2); */ /* CLH */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
@ -630,16 +491,16 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
wait_for_DQ7(info, sect);
}
else {
if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
wait_for_DQ7(info, sect);
}
else {
if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector */
addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */
intel_wait_for_DQ7(info, sect);
intel_wait_for_DQ7(info, sect);
addr2[0] = (FLASH_WORD_SIZE)0x00200020; /* sector erase */
addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */
intel_wait_for_DQ7(info, sect);
intel_wait_for_DQ7(info, sect);
}
else {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
@ -648,18 +509,18 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
wait_for_DQ7(info, sect);
}
}
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
/* wait_for_DQ7(info, sect); */
wait_for_DQ7(info, sect);
}
}
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
/* wait_for_DQ7(info, sect); */
}
}
@ -688,6 +549,7 @@ DONE:
return 0;
}
void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt)
{
int i;
@ -707,8 +569,6 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt)
i++;
c-=(info->start[i]-info->start[i-1]);
}while(c>0);
}

30
board/mpl/common/memtst.c
View file

@ -457,7 +457,7 @@ typedef struct {
#define TEST_STAGES 5
const RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
{RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1,
NULL},
{RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2,
@ -470,9 +470,35 @@ const RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
RAM_MemTest_CheckRandomPattern, NULL}
};
void mem_test_reloc(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long addr;
int i;
for (i=0; i< TEST_STAGES; i++) {
addr = (ulong) (test_stage[i].test_write) + gd->reloc_off;
test_stage[i].test_write=
(void (*) (unsigned long startaddr, unsigned long size,
unsigned long *pat))addr;
addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off;
test_stage[i].test_write_desc=(char *)addr;
if(test_stage[i].test_check1) {
addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off;
test_stage[i].test_check1=
(void *(*) (int mode, unsigned long startaddr,
unsigned long size, unsigned long *pat))addr;
}
if(test_stage[i].test_check2) {
addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off;
test_stage[i].test_check2=
(void *(*) (int mode, unsigned long startaddr,
unsigned long size, unsigned long *pat))addr;
}
}
}
int mem_test (unsigned long start, unsigned long ramsize, int quiet)
int mem_test (unsigned long start, unsigned long ramsize, int quiet, int reloc)
{
unsigned long errors, stage;
unsigned long startaddr, size, i;

5115
board/mpl/common/vga_table.h
View file

File diff suppressed because it is too large Load diff

760
board/mpl/common/video.c
View file

@ -1,760 +0,0 @@
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: Parts of these software are imported from
* - UBL, The Universal Talkware Boot Loader
* Copyright (C) 2000 Universal Talkware Inc.
* - Linux
*
*
*/
#include <common.h>
#ifdef CONFIG_VIDEO
#include <command.h>
#include <asm/processor.h>
#include <devices.h>
#include "video.h"
#include <pci.h>
#include "vga_table.h"
#ifdef CONFIG_VIDEO_CT69000
#define VIDEO_VEND_ID 0x102C
#define VIDEO_DEV_ID 0x00C0
#else
#error CONFIG_VIDEO_CT69000 must be defined
#endif
/*
* Routine for resent board info to video
* resides in pip405.c
*/
extern void video_write_board_info(void);
#undef VGA_DEBUG
#ifdef VGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#define VGA_MAXROWS 25
#define VGA_MAXCOLS 80
#define CRTC_CURSH 14 /* cursor high pos */
#define CRTC_CURSL 15 /* cursor low pos */
/* description of the hardware layout */
#define ATTRI_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3c0 /* Index and Data write port of the attribute Registers */
#define ATTRI_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3c1 /* Data port of the attribute Registers */
#define STATUS_REG0 CFG_ISA_IO_BASE_ADDRESS | 0x3c2 /* Status Register 0 (read only) */
#define MSR_REG_W CFG_ISA_IO_BASE_ADDRESS | 0x3c2 /* Misc. Output Register (write only) */
#define SEQ_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3c4 /* Index port of the Sequencer Controller */
#define SEQ_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3c5 /* Data port of the Sequencer Controller */
#define COL_PAL_MASK CFG_ISA_IO_BASE_ADDRESS | 0x3c6 /* Color Palette Mask */
#define COL_PAL_STAT CFG_ISA_IO_BASE_ADDRESS | 0x3c7 /* Color Palette Status (read only) */
#define COL_PAL_IND_R CFG_ISA_IO_BASE_ADDRESS | 0x3c7 /* Color Palette Read Mode Index (write only) */
#define COL_PAL_IND_W CFG_ISA_IO_BASE_ADDRESS | 0x3c8 /* Color Palette Write Mode Index */
#define COL_PAL_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3c9 /* Color Palette Data Port */
#define FCR_REG_R CFG_ISA_IO_BASE_ADDRESS | 0x3ca /* Feature Control Register (read only) */
#define MSR_REG_R CFG_ISA_IO_BASE_ADDRESS | 0x3cc /* Misc. Output Register (read only) */
#define GR_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3ce /* Index port of the Graphic Controller Registers */
#define GR_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3cf /* Data port of the Graphic Controller Registers */
#define FP_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d0 /* Index port of the Flat panel Registers */
#define FP_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d1 /* Data port of the Flat panel Registers */
#define MR_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d2 /* Index Port of the Multimedia Extension */
#define MR_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d3 /* Data Port of the Multimedia Extension */
#define CRT_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d4 /* Index port of the CRT Controller */
#define CRT_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d5 /* Data port of the CRT Controller */
#define XREG_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d6 /* Extended Register index */
#define XREG_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d7 /* Extended Register data */
#define STATUS_REG1 CFG_ISA_IO_BASE_ADDRESS | 0x3da /* Input Status Register 1 (read only) */
#define FCR_REG_W CFG_ISA_IO_BASE_ADDRESS | 0x3da /* Feature Control Register (write only) */
static unsigned char * video_fb; /* Frame buffer */
/* current hardware state */
static int video_row;
static int video_col;
static unsigned char video_attr;
static unsigned int font_base_addr;
/**********************************************************************
* some forward declerations...
*/
int video_init(int busdevfunc);
void vga_set_attrib(void);
void vga_set_crt(void);
void vga_set_dac(void);
void vga_set_gr(void);
void vga_set_seq(void);
void vga_set_xreg(void);
void vga_write_sr(unsigned char reg,unsigned char val);
void vga_write_gr(unsigned char reg,unsigned char val);
void vga_write_cr(unsigned char reg,unsigned char val);
void vga_set_font(void);
/***************************************************************************
* Init VGA Device
*/
int drv_video_init (void)
{
int error, devices = 1 ;
device_t vgadev ;
int busdevfunc;
busdevfunc=pci_find_device(VIDEO_VEND_ID,VIDEO_DEV_ID,0); /* get PCI Device ID */
if(busdevfunc==-1) {
#ifdef CONFIG_VIDEO_ONBOARD
printf("Error VGA Controller (%04X,%04X) not found\n",VIDEO_VEND_ID,VIDEO_DEV_ID);
#endif
return -1;
}
video_init(busdevfunc);
video_write_board_info();
memset (&vgadev, 0, sizeof(vgadev));
strcpy(vgadev.name, "vga");
vgadev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
vgadev.putc = video_putc;
vgadev.puts = video_puts;
vgadev.getc = NULL;
vgadev.tstc = NULL;
error = device_register (&vgadev);
return (error == 0) ? devices : error ;
}
/***********************************************************
* VGA Initializing
*/
int video_init(int busdevfunc)
{
pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_0, &font_base_addr);
video_fb = (char*)font_base_addr; /* we look into the big linaer memory area */
/* set the extended Registers */
vga_set_xreg();
/* set IO Addresses to 0x3Dx (color mode ) */
out8(MSR_REG_W,0x01);
/* Feature Control Register:
Bits 7-4 Reserved = 0
Bit 3 Vertical Sync select = 1 = Enabled
Bits 2-0 Reserved = 010 = as read from memory.
*/
out8(FCR_REG_W,0x02);
/* Miscelaneous output Register:
Bits 7-6 (num lines) = 01 = VGA 400 lines,
Bit 5 (Odd/Even Page) = 1 = Sleect high page of memory,
Bit 4 reserved = 0,
Bits 3-2 (Clocl Select) = 01 = 28.322Mhz
Bit 1 = Display Ram Enable = 1 = Enable processor access.
Bit 0 = Io Address Select = 1 = Color Graphics Enulation.
*/
out8(MSR_REG_W,0x67);
/* set the palette */
vga_set_dac();
/* set the attributes (before we bring up the engine
then we dont have to wait for refresh).
*/
vga_set_attrib();
/* set the crontroller register. */
vga_set_crt();
vga_write_sr(0x00,0x01); /* synchronous reset */
vga_write_sr(0x01,0x00); /* clocking mode */
vga_write_sr(0x02,0x03); /* write to map 0, 1 */
vga_write_sr(0x03,0x00); /* select character map 0 */
vga_write_sr(0x04,0x03); /* even-odd addressing */
vga_write_sr(0x00,0x03); /* clear synchronous reset */
vga_set_seq(); /* Set the extended sr's. */
vga_set_gr(); /* Set the graphic registers. */
/* load the font */
vga_set_font();
/* initialize the rol/col counts and the text attribute. */
video_row=0;
video_col=0;
video_attr = VGA_ATTR_CLR_WHT;
/* Clear the video ram */
video_clear();
return 1;
}
void vga_set_font(void)
{
int i,j;
char *fontmap;
fontmap = (char *)font_base_addr;
vga_write_sr(0x00,0x01); /* synchronous reset */
vga_write_sr(0x04,0x06); /* sequential addressing */
vga_write_sr(0x02,0x04); /* write to map 2 */
vga_write_sr(0x00,0x03); /* clear synchronous reset */
vga_write_gr(0x04,0x02); /* select map 2 */
vga_write_gr(0x05,0x00); /* disable odd-even addressing */
vga_write_gr(0x06,0x00); /* map start at 0xa0000 */
for(i=0;i<0x100;i++) {
for(j=0;j<0x10;j++) {
*((char *)fontmap+i*32+j)=(char)fontdata_8x16[i*16+j];
}
}
vga_write_sr(0x00,0x01); /* synchronous reset */
vga_write_sr(0x02,0x03); /* write to map 0 and 1 */
vga_write_sr(0x04,0x03); /* odd-even addressing */
vga_write_sr(0x03,0x00); /* Character map 0 & 1 */
vga_write_sr(0x00,0x03); /* clear synchronous reset */
vga_write_gr(0x04,0x00); /* select map 0 for CPU */
vga_write_gr(0x05,0x10); /* enable odd-even addressing */
vga_write_gr(0x06,0x0E); /* map start at 0xb8000 */
}
/* since we are BIG endian, swap attributes and char */
unsigned short vga_swap_short(unsigned short val)
{
unsigned short swapped;
swapped = ((val & 0xff)<<8) | ((val & 0xff00)>>8);
return swapped;
}
/****************************************************
* Routines usable Outside world
*/
/* scolls the text up row rows */
void video_scroll(int row)
{
unsigned short clear = ((unsigned short)video_attr << 8) | (' ');
unsigned short* addr16 = &((unsigned short *)video_fb)[(VGA_MAXROWS-row)*VGA_MAXCOLS];
int i;
clear=vga_swap_short(clear);
memcpy(video_fb, video_fb+row*(VGA_MAXCOLS*2), (VGA_MAXROWS-row)*(VGA_MAXCOLS*2));
for (i = 0 ; i < row * VGA_MAXCOLS ; i++)
addr16[i] = clear;
video_row-=row;
video_col=0;
}
unsigned long video_cursor(int col, int row)
{
unsigned short off = row * VGA_MAXCOLS + col ;
unsigned long saved = (video_col << 16) | (video_row & 0xFFFF);
video_col = col;
video_row = row;
vga_write_cr(CRTC_CURSH,(unsigned char)((off & 0xff00)>>8)); /* Cursor pos. high */
vga_write_cr(CRTC_CURSL,(unsigned char)(off & 0xff)); /* Cursor pos. low */
return saved;
}
void video_set_lxy(unsigned long lxy)
{
int col = (lxy >> 16) & 0xFFFF;
int row = lxy & 0xFFFF;
video_cursor(col,row);
}
unsigned long video_get_lxy(void)
{
return (video_col << 16) | (video_row & 0xFFFF);
}
void video_clear(void)
{
int i;
unsigned short clear = ((unsigned short)video_attr << 8) | (' ');
unsigned short * addr16 = (unsigned short * )video_fb;
clear=vga_swap_short(clear);
video_row = video_col = 0;
for (i = 0 ; i < 2000 ; i++) {
addr16[i] = clear;
}
}
void video_copy(unsigned short *buffer)
{
int i;
unsigned short * addr16 = (unsigned short * )video_fb;
for (i = 0 ; i < 2000 ; i++) {
buffer[i] = addr16[i];
}
}
void video_write(unsigned short *buffer)
{
int i;
unsigned short * addr16 = (unsigned short *)video_fb;
for (i = 0 ; i < 2000 ; i++) {
addr16[i] = buffer[i];
}
}
void video_putc(char ch)
{
char* addr;
#if 0
char buf[48];
char buf1[16];
static int i=0;
sprintf(buf1,"%02X ",ch);
serial_puts(buf1);
buf[i++]=((ch>=0x20)&&(ch<=0x7f)) ? ch : '.';
if(i>=16) {
buf[i++]='\n';
buf[i]='\0';
i=0;
serial_puts(" ");
serial_puts(buf);
}
#endif
switch (ch) {
case '\n':
video_col=0;
video_row++;
break;
case '\r':
video_col=0;
break;
case '\t':
video_col += 8 - video_col % 8;
break;
case '\a':
/* beep(); */
break;
case '\b':
if(video_col)
video_col--;
else
return;
break;
default:
addr = video_fb + 2 * video_row * 80 + 2 * video_col;
*((char *)addr+1) = (char) video_attr;
*((char *)addr) = (char) ch;
video_col++;
if (video_col > (VGA_MAXCOLS-1)) {
video_row++;
video_col=0;
}
}
/* If we're on the bottom of the secreen, wrap one row */
if (video_row > (VGA_MAXROWS-1))
video_scroll(1);
video_cursor(video_col, video_row);
}
unsigned char video_set_attr(unsigned char attr)
{
unsigned char saved_attr = video_attr;
video_attr = attr;
return saved_attr;
}
unsigned char video_set_attr_xy(unsigned char attr, int x, int y)
{
unsigned char *addr = video_fb + (x * 80 + y) * 2 + 1;
unsigned char saved_attr = *addr;
*addr = attr;
return saved_attr;
}
/* put char at xy */
void video_putc_xy(char ch, int x, int y)
{
video_col = x;
video_row = y;
video_putc(ch);
}
/* put char at xy relative to the position */
void video_putc_rxy(char ch, int x, int y)
{
video_col += x;
video_row += y;
video_putc(ch);
}
/* put char with attribute at xy */
void video_putc_axy(char ch, char attr, int x, int y)
{
unsigned char saved_attr = video_set_attr(attr);
video_col = x;
video_row = y;
video_putc(ch);
video_set_attr(saved_attr);
}
void video_puts(const char *s)
{
while(*s) {
video_putc(*s);
s++;
}
}
void video_puts_a(const char *s, char attr)
{
unsigned char saved_attr = video_set_attr(attr);
video_puts(s);
video_set_attr(saved_attr);
}
void video_puts_xy(const char *s, int x, int y)
{
video_cursor(x,y);
video_puts(s);
}
void video_puts_axy(const char *s, char attr, int x, int y)
{
unsigned char saved_attr = video_set_attr(attr);
video_puts_xy(s, x, y);
video_set_attr(saved_attr);
}
void video_wipe_ca_area(unsigned char ch, char attr, int x, int y, int w, int h)
{
int r, c;
/* better to do this as word writes */
unsigned short * addr16 = (unsigned short *)video_fb + (y * 80 + x);
unsigned short charattr = (unsigned short)ch << 8 | attr;
charattr=vga_swap_short(charattr);
for (r = 0 ; r < h ; r++, addr16 += 80) {
for (c = 0 ; c < w ; c++) {
addr16[c] = charattr;
}
}
}
void video_wipe_a_area(unsigned char attr, int x, int y, int w, int h)
{
int r, c;
/* better to do this as word writes */
unsigned short * addr16 = (unsigned short *)video_fb + (y * 80 + x);
for (r = 0 ; r < h ; r++, addr16 += 80) {
for (c = 0 ; c < w ; c++) {
((char*)addr16)[c*2+1] = attr;
}
}
}
void video_wipe_c_area(unsigned char ch, int x, int y, int w, int h)
{
int r, c;
/* better to do this as word writes */
unsigned short * addr16 = (unsigned short *)video_fb + (y * 80 + x);
for (r = 0 ; r < h ; r++, addr16 += 80) {
for (c = 0 ; c < w ; c++) {
((char*)addr16)[c*2] = ch;
}
}
}
/*
tl t tr
l l
bl b br
*/
typedef struct {
unsigned char tl; /* top left corner */
unsigned char t; /* top edge */
unsigned char tr; /* top right corner */
unsigned char l; /* left edge */
unsigned char r; /* right edge */
unsigned char bl; /* bottom left corner */
unsigned char b; /* bottom edge */
unsigned char br; /* bottom right corner */
} box_chars_t;
box_chars_t sbox_chars = {
0xDA, 0xC4, 0xBF,
0xB3, 0xB3,
0xC0, 0xC4, 0xD9
};
box_chars_t dbox_chars = {
0xC9, 0xCD, 0xBB,
0xBA, 0xBA,
0xC8, 0xCD, 0xBC
};
static char cmap[] = "0123456789ABCDEF";
void video_putchex(char c)
{
video_putc(cmap[(c >> 4 ) & 0xF]);
video_putc(cmap[c & 0xF]);
}
void video_putchexl(char c)
{
video_putc(cmap[c & 0xF]);
}
void video_putchexh(char c)
{
video_putc(cmap[(c >> 4) & 0xF]);
}
#define VGA_CELL_CA(a,c) (((unsigned short)c<<8)|a) /* for BIG endians */
void video_gbox_area(box_chars_t *box_chars_p, int x, int y, int w, int h)
{
int r, c;
/* better to do this as word writes */
unsigned short* addr16 = (unsigned short *)video_fb + (y * VGA_MAXCOLS + x);
for (r = 0 ; r < h ; r++, addr16 += VGA_MAXCOLS) {
if (r == 0) {
addr16[0] = VGA_CELL_CA(video_attr, box_chars_p->tl);
addr16[w-1] = VGA_CELL_CA(video_attr, box_chars_p->tr);
for (c = 1 ; c < w - 1 ; c++)
addr16[c] = VGA_CELL_CA(video_attr, box_chars_p->t);
} else if (r == h - 1) {
addr16[0] = VGA_CELL_CA(video_attr, box_chars_p->bl);
addr16[w-1] = VGA_CELL_CA(video_attr, box_chars_p->br);
for (c = 1 ; c < w - 1 ; c++)
addr16[c] = VGA_CELL_CA(video_attr, box_chars_p->b);
} else {
addr16[0] = VGA_CELL_CA(video_attr, box_chars_p->l);
addr16[w-1] = VGA_CELL_CA(video_attr, box_chars_p->r);
}
}
}
/* Writes a box on the screen */
void video_box_area(int x, int y, int w, int h) {
video_gbox_area(&sbox_chars, x, y, w, h);
}
/*writes a box with double lines on the screen */
void video_dbox_area(int x, int y, int w, int h) {
video_gbox_area(&dbox_chars, x, y, w, h);
}
/* routines to set the VGA registers */
/* set attributes */
void vga_set_attrib(void)
{
int i;
unsigned char status;
status=in8(STATUS_REG1);
i=0;
while(attr[i].reg!=0xFF) {
out8(ATTRI_INDEX,attr[i].reg);
out8(ATTRI_INDEX,attr[i].val); /* Attribute uses index for index and data */
i++;
}
out8(ATTRI_INDEX,0x20); /* unblank the screen */
}
/* set CRT Controller Registers */
void vga_set_crt(void)
{
int i;
i=0;
while(crtc[i].reg!=0xFF) {
out8(CRT_INDEX,crtc[i].reg);
out8(CRT_DATA,crtc[i].val);
i++;
}
}
/* Set Palette Registers (DAC) */
void vga_set_dac(void)
{
int i;
for(i=0;i<256;i++) {
out8(COL_PAL_IND_W,(unsigned char)i);
out8(COL_PAL_DATA,dac[i][0]); /* red */
out8(COL_PAL_DATA,dac[i][1]); /* green */
out8(COL_PAL_DATA,dac[i][2]); /* blue */
}
out8(COL_PAL_MASK,0xff); /* set mask */
}
/* set Graphic Controller Register */
void vga_set_gr(void)
{
int i;
i=0;
while(grmr[i].reg!=0xFF) {
out8(GR_INDEX,grmr[i].reg);
out8(GR_DATA,grmr[i].val);
i++;
}
}
/* Set Sequencer Registers */
void vga_set_seq(void)
{
int i;
i=0;
while(seq[i].reg!=0xFF) {
out8(SEQ_INDEX,seq[i].reg);
out8(SEQ_DATA,seq[i].val);
i++;
}
}
/* Set Extension Registers */
void vga_set_xreg(void)
{
int i;
i=0;
while(xreg[i].reg!=0xFF) {
out8(XREG_INDEX,xreg[i].reg);
out8(XREG_DATA,xreg[i].val);
i++;
}
}
/************************************************************
* some helping routines
*/
void vga_write_sr(unsigned char reg,unsigned char val)
{
out8(SEQ_INDEX,reg);
out8(SEQ_DATA,val);
}
void vga_write_gr(unsigned char reg,unsigned char val)
{
out8(GR_INDEX,reg);
out8(GR_DATA,val);
}
void vga_write_cr(unsigned char reg,unsigned char val)
{
out8(CRT_INDEX,reg);
out8(CRT_DATA,val);
}
#if 0
void video_dump_reg(void)
{
/* first dump attributes */
int i;
unsigned char status;
printf("Extended Regs:\n");
i=0;
while(xreg[i].reg!=0xFF) {
out8(XREG_INDEX,xreg[i].reg);
status=in8(XREG_DATA);
printf("XR%02X is %02X, should be %02X\n",xreg[i].reg,status,xreg[i].val);
i++;
}
printf("Sequencer Regs:\n");
i=0;
while(seq[i].reg!=0xFF) {
out8(SEQ_INDEX,seq[i].reg);
status=in8(SEQ_DATA);
printf("SR%02X is %02X, should be %02X\n",seq[i].reg,status,seq[i].val);
i++;
}
printf("Graphic Regs:\n");
i=0;
while(grmr[i].reg!=0xFF) {
out8(GR_INDEX,grmr[i].reg);
status=in8(GR_DATA);
printf("GR%02X is %02X, should be %02X\n",grmr[i].reg,status,grmr[i].val);
i++;
}
printf("CRT Regs:\n");
i=0;
while(crtc[i].reg!=0xFF) {
out8(CRT_INDEX,crtc[i].reg);
status=in8(CRT_DATA);
printf("CR%02X is %02X, should be %02X\n",crtc[i].reg,status,crtc[i].val);
i++;
}
printf("Attributes:\n");
status=in8(STATUS_REG1);
i=0;
while(attr[i].reg!=0xFF) {
out8(ATTRI_INDEX,attr[i].reg);
status=in8(ATTRI_DATA);
out8(ATTRI_INDEX,attr[i].val); /* Attribute uses index for index and data */
printf("AR%02X is %02X, should be %02X\n",attr[i].reg,status,attr[i].val);
i++;
}
}
#endif
#endif /* CONFIG_VIDEO */

75
board/mpl/common/video.h
View file

@ -1,75 +0,0 @@
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifdef CONFIG_VIDEO
#ifndef _VIDEO_H
#define _VIDEO_H
int video_init(int busdevfunc);
void video_clear(void);
void video_putc(char ch);
void video_puts(const char *s);
void video_puts_a(const char *s, char attr);
unsigned char video_set_attr(unsigned char attr);
void video_box_area(int x, int y, int w, int h);
void video_dbox_area(int x, int y, int w, int h);
void video_wipe_c_area(unsigned char ch, int x, int y, int w, int h);
void video_wipe_a_area(unsigned char attr, int x, int y, int w, int h);
void video_wipe_ca_area(unsigned char ch, char attr, int x, int y, int w, int h);
void video_puts_axy(const char *s, char attr, int x, int y);
void video_putc_rxy(char ch, int x, int y);
void video_putc_xy(char ch, int x, int y);
unsigned char video_set_attr_xy(unsigned char attr, int x, int y);
void video_copy(unsigned short *buffer);
void video_write(unsigned short *buffer);
#define VGA_ATTR_CLR_RED 0x4
#define VGA_ATTR_CLR_GRN 0x2
#define VGA_ATTR_CLR_BLU 0x1
#define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)
#define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
#define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)
#define VGA_ATTR_CLR_BLK 0
#define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
#define VGA_ATTR_BNK 0x80
#define VGA_ATTR_ITN 0x08
#define VGA_ATTR_BG_MSK 0x70
#define VGA_ATTR_FG_MSK 0x07
#define VGA_ATTR_BG_GET(v) (((v) & VGA_ATTR_BG_MSK)>>4)
#define VGA_ATTR_BG_SET(v, c) (((c) & VGA_ATTR_FG_MSK)<<4) | (v & ~VGA_ATTR_BG_MSK))
#define VGA_ATTR_FG_GET(v) ((v) & VGA_ATTR_FG_MSK)
#define VGA_ATTR_FG_SET(v, c) ((c) & VGA_ATTR_FG_MSK) | (v & ~VGA_ATTR_FG_MSK))
#define VGA_ATTR_FG_BG_SET(v, b, f) (VGA_ATTR_BG_SET(v, b) | VGA_ATTR_FG_SET(v, cf))
#define VGA_ATTR_INVERT(A) ((((A)&0x7)<<4)|(((A)&0x70)>>4) |((A)&0x88))
#endif /* _VIDEO_H */
#endif /* CONFIG_VIDEO */

41
board/mpl/mip405/mip405.c
View file

@ -113,28 +113,37 @@ const sdram_t sdram_table[] = {
{ 0x0f, /* Rev A, 128MByte -1 Board */
3, /* Case Latenty = 3 */
3, /* trp 20ns / 7.5 ns datain[27] */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
4, /* tcpt 44 - 20ns = 24ns */
3, /* Address Mode = 3 */
3, /* Address Mode = 3 */
5, /* size value */
1}, /* ECC enabled */
{ 0x07, /* Rev A, 64MByte -2 Board */
3, /* Case Latenty = 3 */
3, /* trp 20ns / 7.5 ns datain[27] */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
4, /* tcpt 44 - 20ns = 24ns */
2, /* Address Mode = 2 */
2, /* Address Mode = 2 */
4, /* size value */
1}, /* ECC enabled */
{ 0x03, /* Rev A, 128MByte -4 Board */
3, /* Case Latenty = 3 */
3, /* trp 20ns / 7.5 ns datain[27] */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
4, /* tcpt 44 - 20ns = 24ns */
3, /* Address Mode = 3 */
3, /* Address Mode = 3 */
5, /* size value */
1}, /* ECC enabled */
{ 0x1f, /* Rev B, 128MByte -3 Board */
3, /* Case Latenty = 3 */
3, /* trp 20ns / 7.5 ns datain[27] */
3, /* trcd 20ns /7.5 ns (datain[29]) */
6, /* tras 44ns /7.5 ns (datain[30]) */
4, /* tcpt 44 - 20ns = 24ns */
3, /* Address Mode = 3 */
5, /* size value */
1}, /* ECC enabled */
{ 0xff, /* terminator */
@ -515,6 +524,9 @@ int checkboard (void)
var >>= 1;
}
rc++;
if((((bc>>4) & 0xf)==0x1) /* Rev B PCB with */
&& (rc==0x1)) /* Population Option 1 is a -3 */
rc=3;
i = getenv_r ("serial#", s, 32);
if ((i == 0) || strncmp (s, "MIP405", 6)) {
get_backup_values (b);
@ -614,17 +626,24 @@ void print_mip405_rev (void)
vers &= 0xf;
rev = (((vers & 0x1) ? 0x8 : 0) |
((vers & 0x2) ? 0x4 : 0) |
((vers & 0x4) ? 0x2 : 0) | ((vers & 0x8) ? 0x1 : 0));
((vers & 0x4) ? 0x2 : 0) |
((vers & 0x8) ? 0x1 : 0));
vers=16-rev;
rev=vers;
if((rev==1) && ((cfg >> 4)==1)) /* Rev B PCB and -1 is a -3 */
rev=3;
part = in8 (PLD_PART_REG);
vers = in8 (PLD_VERS_REG);
printf ("Rev: MIP405-%d Rev %c PLD%d Vers %d\n",
(16 - rev), ((cfg >> 4) & 0xf) + 'A', part, vers);
rev, ((cfg >> 4) & 0xf) + 'A', part, vers);
}
extern void mem_test_reloc(void);
int last_stage_init (void)
{
mem_test_reloc();
/* write correct LED configuration */
if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
printf ("Error writing to the PHY\n");

159
board/mpl/pip405/pip405.h
View file

@ -51,3 +51,162 @@ void user_led1(unsigned char on);
#define PIIX4_IDE_DEV_ID 0x7111
/* timings */
/* PLD (CS7) */
#define PLD_BME 0 /* Burst disable */
#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define PLD_OEN 1 /* Cycles from CS low to OE low */
#define PLD_WBN 1 /* Cycles from CS low to WE low */
#define PLD_WBF 1 /* Cycles from WE high to CS high */
#define PLD_TH 2 /* Number of hold cycles after transfer */
#define PLD_RE 0 /* Ready disabled */
#define PLD_SOR 1 /* Sample on Ready disabled */
#define PLD_BEM 0 /* Byte Write only active on Write cycles */
#define PLD_PEN 0 /* Parity disable */
#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define PLD_BS 0 /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define PLD_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define PLD_BW 0 /* 16Bit */
#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
/* timings */
#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
/* Dummy CS to get the board revision */
#define BOARD_BME 0 /* Burst disable */
#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define BOARD_OEN 1 /* Cycles from CS low to OE low */
#define BOARD_WBN 1 /* Cycles from CS low to WE low */
#define BOARD_WBF 1 /* Cycles from WE high to CS high */
#define BOARD_TH 2 /* Number of hold cycles after transfer */
#define BOARD_RE 0 /* Ready disabled */
#define BOARD_SOR 1 /* Sample on Ready disabled */
#define BOARD_BEM 0 /* Byte Write only active on Write cycles */
#define BOARD_PEN 0 /* Parity disable */
#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define BOARD_BS 0 /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define BOARD_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define BOARD_BW 0 /* 16Bit */
#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
/* UART0 CS2 */
#define UART0_BME 0 /* Burst disable */
#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define UART0_OEN 1 /* Cycles from CS low to OE low */
#define UART0_WBN 1 /* Cycles from CS low to WE low */
#define UART0_WBF 1 /* Cycles from WE high to CS high */
#define UART0_TH 2 /* Number of hold cycles after transfer */
#define UART0_RE 0 /* Ready disabled */
#define UART0_SOR 1 /* Sample on Ready disabled */
#define UART0_BEM 0 /* Byte Write only active on Write cycles */
#define UART0_PEN 0 /* Parity disable */
#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define UART0_BS 0 /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define UART0_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define UART0_BW 0 /* 8Bit */
#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
/* UART1 CS3 */
#define UART1_AP UART0_AP /* same timing as UART0 */
#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
/* Flash CS0 or CS 1 */
/* 0x7F8FFE80 slowest timing at all... */
#define FLASH_BME_B 1 /* Burst enable */
#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
#define FLASH_BME 0 /* Burst disable */
#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define FLASH_OEN 1 /* Cycles from CS low to OE low */
#define FLASH_WBN 1 /* Cycles from CS low to WE low */
#define FLASH_WBF 1 /* Cycles from WE high to CS high */
#define FLASH_TH 2 /* Number of hold cycles after transfer */
#define FLASH_RE 0 /* Ready disabled */
#define FLASH_SOR 1 /* Sample on Ready disabled */
#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
#define FLASH_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Access Parameter Register for Boot */
#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_BS 2 /* 4 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define FLASH_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define FLASH_BW 1 /* 16Bit */
/* CR register for Boot */
#define FLASH_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
/* CR register for non Boot */
#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
/* MPS CS1 or CS0 */
/* Boot CS: */
#define MPS_BME_B 1 /* Burst enable */
#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
#define MPS_BME 0 /* Burst disable */
#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define MPS_OEN 1 /* Cycles from CS low to OE low */
#define MPS_WBN 1 /* Cycles from CS low to WE low */
#define MPS_WBF 1 /* Cycles from WE high to CS high */
#define MPS_TH 2 /* Number of hold cycles after transfer */
#define MPS_RE 0 /* Ready disabled */
#define MPS_SOR 1 /* Sample on Ready disabled */
#define MPS_BEM 0 /* Byte Write only active on Write cycles */
#define MPS_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Access Parameter Register for Boot */
#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define MPS_BS 2 /* 4 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define MPS_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define MPS_BW 0 /* 8Bit */
/* CR register for Boot */
#define MPS_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
/* CR register for non Boot */
#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))

2
board/mpl/vcma9/vcma9.c
View file

@ -216,9 +216,11 @@ void print_vcma9_rev(void)
Get_PLD_Version(), Get_PLD_Revision());
}
extern void mem_test_reloc(void);
int last_stage_init(void)
{
mem_test_reloc();
print_vcma9_rev();
show_stdio_dev();
check_env();

2
include/configs/MIP405.h
View file

@ -217,7 +217,7 @@
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */