Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2025-02-26 12:27:12 +00:00
Code Issues Projects Releases Packages Wiki Activity

video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()

Browse source 
The clk_set_rate() function returns rate as an 'ulong' not
an 'int' and rate > 0 by default.

This patch avoids to display the associated warning when
the set rate function returns the new frequency.

Fixes: aeaf330649 ("video: stm32: stm32_ltdc: add bridge to display controller")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Gabriel Fernandez 2022-02-01 14:02:14 +01:00 • committed by Patrice Chotard
parent 6ed21f3d70
commit 310ef93028
1 changed files with 6 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
drivers/video/stm32/stm32_ltdc.c
View file

@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
ulong rate;
int ret;
priv->regs = (void *)dev_read_addr(dev);
@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev)
}
}
ret = clk_set_rate(&pclk, timings.pixelclock.typ);
if (ret)
dev_warn(dev, "fail to set pixel clock %d hz\n",
timings.pixelclock.typ);
rate = clk_set_rate(&pclk, timings.pixelclock.typ);
if (IS_ERR_VALUE(rate))
dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
timings.pixelclock.typ, rate);
dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
timings.pixelclock.typ, clk_get_rate(&pclk));
timings.pixelclock.typ, rate);
ret = reset_get_by_index(dev, 0, &rst);
if (ret) {