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Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze

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This commit is contained in:
Tom Rini 2015-01-26 06:42:15 -05:00
commit 306df2c824
11 changed files with 137 additions and 40 deletions
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1
arch/arm/cpu/armv7/zynq/Makefile
View file

@ -13,4 +13,5 @@ obj-y += cpu.o
obj-y += ddrc.o
obj-y += slcr.o
obj-y += clk.o
obj-y += lowlevel_init.o
obj-$(CONFIG_SPL_BUILD) += spl.o

7
arch/arm/cpu/armv7/zynq/config.mk Normal file
View file

@ -0,0 +1,7 @@
#
# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
#
# SPDX-License-Identifier: GPL-2.0
#
# Allow NEON instructions (needed for lowlevel_init.S with GNU toolchain)
PLATFORM_RELFLAGS += -mfpu=neon

4
arch/arm/cpu/armv7/zynq/cpu.c
View file

@ -10,10 +10,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
void lowlevel_init(void)
{
}
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28

2
arch/arm/cpu/armv7/zynq/ddrc.c
View file

@ -42,6 +42,8 @@ void zynq_ddrc_init(void)
*/
/* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
gd->ram_size /= 2;
} else {
puts("ECC disabled ");
}

26
arch/arm/cpu/armv7/zynq/lowlevel_init.S Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (C) 2013 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
/* Enable the the VFP */
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, #(0x3 << 20)
orr r1, r1, #(0x3 << 20)
mcr p15, 0, r1, c1, c0, 2
isb
fmrx r1, FPEXC
orr r1,r1, #(1<<30)
fmxr FPEXC, r1
/* Move back to caller */
mov pc, lr
ENDPROC(lowlevel_init)

2
arch/arm/cpu/armv7/zynq/slcr.c
View file

@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
zynq_slcr_unlock();
/* Disable AXI interface by asserting FPGA resets */
writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
writel(0xF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
writel(0xA, &slcr_base->lvl_shftr_en);

9
arch/arm/cpu/armv7/zynq/spl.c
View file

@ -43,12 +43,21 @@ u32 spl_boot_device(void)
mode = BOOT_DEVICE_SPI;
break;
#endif
case ZYNQ_BM_NAND:
mode = BOOT_DEVICE_NAND;
break;
case ZYNQ_BM_NOR:
mode = BOOT_DEVICE_NOR;
break;
#ifdef CONFIG_SPL_MMC_SUPPORT
case ZYNQ_BM_SD:
puts("mmc boot\n");
mode = BOOT_DEVICE_MMC1;
break;
#endif
case ZYNQ_BM_JTAG:
mode = BOOT_DEVICE_RAM;
break;
default:
puts("Unsupported boot mode selected\n");
hang();

5
arch/arm/include/asm/arch-zynq/hardware.h
View file

@ -21,6 +21,9 @@
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
#define ZYNQ_SMC_BASEADDR 0xE000E000
#define ZYNQ_NAND_BASEADDR 0xE1000000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
#define ZYNQ_USB_BASEADDR0 0xE0002000
@ -28,7 +31,9 @@
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0x7
#define ZYNQ_BM_QSPI 0x1
#define ZYNQ_BM_NOR 0x2
#define ZYNQ_BM_NAND 0x4
#define ZYNQ_BM_SD 0x5
#define ZYNQ_BM_JTAG 0x0

14
board/xilinx/zynq/board.c
View file

@ -91,6 +91,14 @@ int board_late_init(void)
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tXilinx Zynq\n");
return 0;
}
#endif
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
@ -115,11 +123,13 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
CONFIG_ZYNQ_GEM_PHY_ADDR0,
CONFIG_ZYNQ_GEM_EMIO0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
CONFIG_ZYNQ_GEM_PHY_ADDR1,
CONFIG_ZYNQ_GEM_EMIO1);
# endif
#endif
return ret;

30
drivers/serial/serial_zynq.c
View file

@ -27,14 +27,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
struct uart_zynq {
u32 control; /* Control Register [8:0] */
u32 mode; /* Mode Register [10:0] */
u32 control; /* 0x0 - Control Register [8:0] */
u32 mode; /* 0x4 - Mode Register [10:0] */
u32 reserved1[4];
u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
u32 reserved2[4];
u32 channel_sts; /* Channel Status [11:0] */
u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
u32 channel_sts; /* 0x2c - Channel Status [11:0] */
u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
};
static struct uart_zynq *uart_zynq_ports[2] = {
@ -42,29 +42,13 @@ static struct uart_zynq *uart_zynq_ports[2] = {
[1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
};
#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
#endif
#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
#endif
struct uart_zynq_params {
u32 baudrate;
};
static struct uart_zynq_params uart_zynq_ports_param[2] = {
[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
};
/* Set up the baud rate in gd struct */
static void uart_zynq_serial_setbrg(const int port)
{
/* Calculation results. */
unsigned int calc_bauderror, bdiv, bgen;
unsigned long calc_baud = 0;
unsigned long baud = uart_zynq_ports_param[port].baudrate;
unsigned long baud = gd->baudrate;
unsigned long clock = get_uart_clk(port);
struct uart_zynq *regs = uart_zynq_ports[port];

77
include/configs/zynq-common.h
View file

@ -47,6 +47,17 @@
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHYLIB
# define CONFIG_PHY_MARVELL
# define CONFIG_BOOTP_SERVERIP
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_HOSTNAME
# define CONFIG_BOOTP_MAY_FAIL
# if !defined(CONFIG_ZYNQ_GEM_EMIO0)
# define CONFIG_ZYNQ_GEM_EMIO0 0
# endif
# if !defined(CONFIG_ZYNQ_GEM_EMIO1)
# define CONFIG_ZYNQ_GEM_EMIO1 0
# endif
#endif
/* SPI */
@ -90,6 +101,55 @@
# define CONFIG_USB_ULPI
# define CONFIG_EHCI_IS_TDI
# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
# define CONFIG_USB_GADGET
# define CONFIG_USB_GADGET_DUALSPEED
# define CONFIG_USBDOWNLOAD_GADGET
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_DFU_FUNCTION
# define CONFIG_DFU_RAM
# define CONFIG_USB_GADGET_VBUS_DRAW 2
# define CONFIG_G_DNL_VENDOR_NUM 0x03FD
# define CONFIG_G_DNL_PRODUCT_NUM 0x0300
# define CONFIG_G_DNL_MANUFACTURER "Xilinx"
# define CONFIG_USB_GADGET
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_DFU
# define CONFIG_CMD_THOR_DOWNLOAD
# define CONFIG_THOR_FUNCTION
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"set dfu_alt_info " \
"${kernel_image} ram 0x3000000 0x500000\\\\;" \
"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
"${ramdisk_image} ram 0x2000000 0x600000\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
# if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
# define CONFIG_DFU_MMC
# define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
"${kernel_image} fat 0 1\\\\;" \
"${devicetree_image} fat 0 1\\\\;" \
"${ramdisk_image} fat 0 1\0" \
"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
# define DFU_ALT_INFO \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_MMC
# else
# define DFU_ALT_INFO \
DFU_ALT_INFO_RAM
# endif
#endif
#if !defined(DFU_ALT_INFO)
# define DFU_ALT_INFO
#endif
#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
@ -100,6 +160,7 @@
# define CONFIG_DOS_PARTITION
# define CONFIG_CMD_EXT4
# define CONFIG_CMD_EXT4_WRITE
# define CONFIG_CMD_FS_GENERIC
#endif
#define CONFIG_SYS_I2C_ZYNQ
@ -121,12 +182,6 @@
# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */
#endif
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_MAY_FAIL
/* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE (128 << 10)
@ -159,16 +214,17 @@
"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
"bootm ${load_addr}\0" \
"sdboot=echo Copying FIT from SD to RAM... && " \
"fatload mmc 0 ${load_addr} ${fit_image} && " \
"load mmc 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"jtagboot=echo TFTPing FIT to RAM... && " \
"tftpboot ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"usbboot=if usb start; then " \
"echo Copying FIT from USB to RAM... && " \
"fatload usb 0 ${load_addr} ${fit_image} && " \
"load usb 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"fi\0"
"fi\0" \
DFU_ALT_INFO
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
@ -181,6 +237,7 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
#define CONFIG_CMD_CLK
@ -198,7 +255,7 @@
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
#define CONFIG_SYS_MALLOC_LEN 0x400000
#define CONFIG_SYS_MALLOC_LEN 0xC00000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \