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powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCs

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The workaround for ESDHC111 should also be applied on
P2040/P3041/P5010/P5020 SoCs.

Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Lei Xu 2011-04-19 15:28:41 +08:00 committed by Kumar Gala
parent 86221f09fb
commit 300097669c
1 changed files with 4 additions and 0 deletions
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4
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -266,6 +266,7 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
@ -279,6 +280,7 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4
@ -323,6 +325,7 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_PPC_P5020)
#define CONFIG_MAX_CPUS 2
@ -336,6 +339,7 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#else
#error Processor type not defined for this platform