mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
ARM: dts: rockchip: update rk3xxx.dtsi
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. This file has recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3xxx-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Johan Jonker
Kever Yang
parent
571f679d1a
commit
2ee023d293
4 changed files with 181 additions and 74 deletions
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@ -12,6 +12,10 @@
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model = "Radxa Rock";
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compatible = "radxa,rock", "rockchip,rk3188";
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aliases {
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mmc0 = &mmc0;
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};
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chosen {
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/* stdout-path = &uart2; */
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stdout-path = "serial2:115200n8";
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@ -8,6 +8,7 @@
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3188-cru.h>
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#include "rk3xxx.dtsi"
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#include "rk3xxx-u-boot.dtsi"
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/ {
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compatible = "rockchip,rk3188";
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35
arch/arm/dts/rk3xxx-u-boot.dtsi
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35
arch/arm/dts/rk3xxx-u-boot.dtsi
Normal file
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@ -0,0 +1,35 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/ {
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noc: syscon@10128000 {
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compatible = "rockchip,rk3188-noc", "syscon";
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reg = <0x10128000 0x2000>;
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u-boot,dm-spl;
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};
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dmc: dmc@20020000 {
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/* unreviewed u-boot-specific binding */
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compatible = "rockchip,rk3188-dmc", "syscon";
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reg = <0x20020000 0x3fc
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0x20040000 0x294>;
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clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;
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clock-names = "pclk_ddrupctl", "pclk_publ";
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rockchip,cru = <&cru>;
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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rockchip,noc = <&noc>;
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u-boot,dm-spl;
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};
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};
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&grf {
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u-boot,dm-spl;
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};
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&pmu {
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u-boot,dm-spl;
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};
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&uart2 {
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clock-frequency = <24000000>;
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};
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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@ -6,9 +6,12 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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@ -18,9 +21,6 @@
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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mshc0 = &emmc;
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mshc1 = &mmc0;
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mshc2 = &mmc1;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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@ -29,47 +29,6 @@
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spi1 = &spi1;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dmac1_s: dma-controller@20018000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20018000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMA1>;
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clock-names = "apb_pclk";
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};
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dmac1_ns: dma-controller@2001c000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x2001c000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMA1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dmac2: dma-controller@20078000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20078000 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMA2>;
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clock-names = "apb_pclk";
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};
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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@ -77,7 +36,30 @@
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clock-output-names = "xin24m";
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};
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L2: l2-cache-controller@10138000 {
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gpu: gpu@10090000 {
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compatible = "arm,mali-400";
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reg = <0x10090000 0x10000>;
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clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
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clock-names = "bus", "core";
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assigned-clocks = <&cru ACLK_GPU>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_GPU>;
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status = "disabled";
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};
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vpu: video-codec@10104000 {
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compatible = "rockchip,rk3066-vpu";
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reg = <0x10104000 0x800>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vepu", "vdpu";
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clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
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<&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
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clock-names = "aclk_vdpu", "hclk_vdpu",
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"aclk_vepu", "hclk_vepu";
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};
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L2: cache-controller@10138000 {
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compatible = "arm,pl310-cache";
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reg = <0x10138000 0x1000>;
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cache-unified;
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@ -92,14 +74,14 @@
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global_timer: global-timer@1013c200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1013c200 0x20>;
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interrupts = <GIC_PPI 11 0x304>;
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interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&cru CORE_PERI>;
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};
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local_timer: local-timer@1013c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1013c600 0x20>;
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interrupts = <GIC_PPI 13 0x304>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&cru CORE_PERI>;
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};
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@ -133,10 +115,44 @@
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status = "disabled";
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};
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noc: syscon@10128000 {
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u-boot,dm-spl;
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compatible = "rockchip,rk3188-noc", "syscon";
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reg = <0x10128000 0x2000>;
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qos_gpu: qos@1012d000 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012d000 0x20>;
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};
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qos_vpu: qos@1012e000 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012e000 0x20>;
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};
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qos_lcdc0: qos@1012f000 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012f000 0x20>;
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};
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qos_cif0: qos@1012f080 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012f080 0x20>;
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};
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qos_ipp: qos@1012f100 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012f100 0x20>;
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};
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qos_lcdc1: qos@1012f180 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012f180 0x20>;
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};
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qos_cif1: qos@1012f200 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012f200 0x20>;
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};
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qos_rga: qos@1012f280 {
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compatible = "rockchip,rk3066-qos", "syscon";
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reg = <0x1012f280 0x20>;
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};
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usb_otg: usb@10180000 {
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@ -149,7 +165,6 @@
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g-np-tx-fifo-size = <16>;
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g-rx-fifo-size = <275>;
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g-tx-fifo-size = <256 128 128 64 64 32>;
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g-use-dma;
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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status = "disabled";
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@ -184,60 +199,99 @@
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status = "disabled";
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};
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mmc0: dwmmc@10214000 {
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mmc0: mmc@10214000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x10214000 0x1000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
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clock-names = "biu", "ciu";
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dmas = <&dmac2 1>;
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dma-names = "rx-tx";
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fifo-depth = <256>;
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resets = <&cru SRST_SDMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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mmc1: dwmmc@10218000 {
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mmc1: mmc@10218000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x10218000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
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clock-names = "biu", "ciu";
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dmas = <&dmac2 3>;
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dma-names = "rx-tx";
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fifo-depth = <256>;
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resets = <&cru SRST_SDIO>;
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reset-names = "reset";
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status = "disabled";
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};
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emmc: dwmmc@1021c000 {
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emmc: mmc@1021c000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x1021c000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
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clock-names = "biu", "ciu";
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dmas = <&dmac2 4>;
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dma-names = "rx-tx";
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fifo-depth = <256>;
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resets = <&cru SRST_EMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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nfc: nand-controller@10500000 {
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compatible = "rockchip,rk2928-nfc";
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reg = <0x10500000 0x4000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_NANDC0>;
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clock-names = "ahb";
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status = "disabled";
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};
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pmu: pmu@20004000 {
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compatible = "rockchip,rk3066-pmu", "syscon";
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compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
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reg = <0x20004000 0x100>;
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u-boot,dm-spl;
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reboot-mode {
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compatible = "syscon-reboot-mode";
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offset = <0x40>;
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mode-normal = <BOOT_NORMAL>;
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mode-recovery = <BOOT_RECOVERY>;
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mode-bootloader = <BOOT_FASTBOOT>;
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mode-loader = <BOOT_BL_DOWNLOAD>;
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};
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};
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grf: grf@20008000 {
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compatible = "syscon";
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compatible = "syscon", "simple-mfd";
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reg = <0x20008000 0x200>;
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u-boot,dm-spl;
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};
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dmc: dmc@20020000 {
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/* unreviewed u-boot-specific binding */
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compatible = "rockchip,rk3188-dmc", "syscon";
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rockchip,cru = <&cru>;
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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rockchip,noc = <&noc>;
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reg = <0x20020000 0x3fc
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0x20040000 0x294>;
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clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;
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clock-names = "pclk_ddrupctl", "pclk_publ";
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u-boot,dm-spl;
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dmac1_s: dma-controller@20018000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20018000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMA1>;
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clock-names = "apb_pclk";
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};
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dmac1_ns: dma-controller@2001c000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x2001c000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMA1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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i2c0: i2c@2002d000 {
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@ -361,7 +415,6 @@
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clock-frequency = <24000000>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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status = "disabled";
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@ -385,6 +438,8 @@
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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@ -413,4 +468,16 @@
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dma-names = "tx", "rx";
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status = "disabled";
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};
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dmac2: dma-controller@20078000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20078000 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMA2>;
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clock-names = "apb_pclk";
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};
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};
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