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https://github.com/AsahiLinux/u-boot
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mpc83xx: Add NAND boot support for MPC8315E-RDB boards
The core support for NAND booting is there already, so this patch
is pretty straightforward.
There is one trick though: top level Makefile expects nand_spl to
be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code
from mpc8313erdb boards, and so to not duplicate the code we just
symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
o silence make during ln echo
o update documentation
o and avoid:
$ ./MAKEALL MPC8315ERDB_NAND
Configuring for MPC8315ERDB board...
sdram.o: In function `fixed_sdram':
/home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay'
by renaming udelay -> __udelay in the spirit of commit
3eb90bad65 "Generic udelay() with watchdog
support".
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Anton Vorontsov
Kim Phillips
parent
6ca9da4d42
commit
2e95004deb
7 changed files with 167 additions and 23 deletions
1
MAKEALL
1
MAKEALL
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@ -362,6 +362,7 @@ LIST_83xx=" \
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MPC8313ERDB_33 \
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MPC8313ERDB_NAND_66 \
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MPC8315ERDB \
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MPC8315ERDB_NAND \
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MPC8323ERDB \
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MPC832XEMDS \
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MPC832XEMDS_ATM \
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6
Makefile
6
Makefile
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@ -2261,8 +2261,12 @@ MPC8313ERDB_NAND_66_config: unconfig
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echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
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fi ;
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MPC8315ERDB_NAND_config \
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MPC8315ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
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@if [ "$(findstring _NAND_,$@)" ] ; then \
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ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \
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fi ;
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@$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
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MPC8323ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
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@ -1 +1,9 @@
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ifndef NAND_SPL
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ifeq ($(CONFIG_MK_NAND), y)
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TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
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endif
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endif
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ifndef TEXT_BASE
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TEXT_BASE = 0xFE000000
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endif
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@ -32,6 +32,8 @@
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#include <mpc83xx.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <ns16550.h>
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#include <nand.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -45,6 +47,8 @@ int board_early_init_f(void)
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return 0;
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}
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#ifndef CONFIG_NAND_SPL
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static u8 read_board_info(void)
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{
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u8 val8;
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@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis)
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cpu_eth_init(bis); /* Initialize TSECs first */
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return pci_eth_init(bis);
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}
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#else /* CONFIG_NAND_SPL */
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int checkboard(void)
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{
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puts("Board: Freescale MPC8315ERDB\n");
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return 0;
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}
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void board_init_f(ulong bootflag)
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{
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board_early_init_f();
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NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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puts("NAND boot... ");
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init_timebase();
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initdram(0);
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (gd->flags & GD_FLG_SILENT)
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return;
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if (c == '\n')
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
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}
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#endif /* CONFIG_NAND_SPL */
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@ -54,6 +54,7 @@ static void resume_from_sleep(void)
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* This is useful for faster booting in configs where the RAM is unlikely
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* to be changed, or for things like NAND booting where space is tight.
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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static long fixed_sdram(void)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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@ -68,7 +69,7 @@ static long fixed_sdram(void)
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
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* or the DDR2 controller may fail to initialize correctly.
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*/
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udelay(50000);
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__udelay(50000);
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im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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@ -100,6 +101,12 @@ static long fixed_sdram(void)
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return msize;
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}
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#else
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static long fixed_sdram(void)
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{
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return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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}
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#endif /* CONFIG_SYS_RAMBOOT */
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phys_size_t initdram(int board_type)
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{
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@ -15,6 +15,18 @@ Freescale MPC8315ERDB Board
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4321 4321
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(where the '*' indicates the position of the tab of the switch.)
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To boot the image at the beginning of NAND flash, use these
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DIP switch settings for S3 S4:
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+------+ +------+
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| * | | *** |
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| *** | | * |
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+------+ ON +------+ ON
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4321 4321
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(where the '*' indicates the position of the tab of the switch.)
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When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
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2. Memory Map
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The memory map looks like this:
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@ -26,6 +38,9 @@ Freescale MPC8315ERDB Board
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0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
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0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
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When booting from NAND, NAND flash is CS0 and NOR flash
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is CS1.
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3. Definitions
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3.1 Explanation of NEW definitions in:
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@ -43,13 +58,15 @@ Freescale MPC8315ERDB Board
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export CROSS_COMPILE=your-cross-compiler-prefix-
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make distclean
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make MPC8315ERDB_config
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make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
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make all
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5. Downloading and Flashing Images
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5.1 Reflash U-boot Image using U-boot
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NOR flash:
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tftp 40000 u-boot.bin
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protect off all
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erase fe000000 fe1fffff
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@ -60,6 +77,15 @@ Freescale MPC8315ERDB Board
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You have to supply the correct byte count with 'xxxx'
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from the TFTP result log.
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NAND flash:
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=>tftpboot $loadaddr <filename>
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=>nand erase 0 0x80000
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=>nand write $loadaddr 0 0x80000
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...where 0x80000 is the filesize rounded up to
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the next 0x20000 increment.
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5.2 Downloading and Booting Linux Kernel
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Ensure that all networking-related environment variables are set
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@ -76,5 +102,4 @@ Freescale MPC8315ERDB Board
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6 Notes
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Booting from NAND flash is not yet supported.
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The console baudrate for MPC8315ERDB is 115200bps.
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@ -25,6 +25,11 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_MK_NAND
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#define CONFIG_NAND_U_BOOT 1
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#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000
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#endif
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/*
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* High Level Configuration Options
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*/
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@ -51,20 +56,29 @@
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HRCWL_SVCOD_DIV_2 |\
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HRCWL_CSB_TO_CLKIN_2X1 |\
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HRCWL_CORE_TO_CSB_3X1)
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#define CONFIG_SYS_HRCW_HIGH (\
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#define CONFIG_SYS_HRCW_HIGH_BASE (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_RGMII |\
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HRCWH_TSEC2M_IN_RGMII |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LALE_NORMAL)
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
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HRCWH_FROM_0XFFF00100 |\
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HRCWH_ROM_LOC_NAND_SP_8BIT |\
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HRCWH_RL_EXT_NAND)
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#else
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#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY)
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#endif
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/*
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* System IO Config
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*/
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@ -79,6 +93,10 @@
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
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#endif
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/*
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* Arbiter Setup
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*/
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@ -161,12 +179,6 @@
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*/
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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@ -200,10 +212,10 @@
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
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#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
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#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
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| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
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| BR_V ) /* valid */
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#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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@ -223,18 +235,31 @@
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/*
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* NAND Flash on the Local Bus
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*/
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#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_NAND_BASE 0xFFF00000
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#else
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#define CONFIG_SYS_NAND_BASE 0xE0600000
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#endif
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE 1
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
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#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
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#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
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#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V ) /* valid */
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#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
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#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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@ -243,9 +268,31 @@
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| OR_FCM_EHTR )
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/* 0xFFFF8396 */
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#ifdef CONFIG_NAND_U_BOOT
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
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#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
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#else
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
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#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
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#endif
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
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#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
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#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
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#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
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!defined(CONFIG_NAND_SPL)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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/*
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* Serial Port
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*/
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@ -254,7 +301,7 @@
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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@ -408,7 +455,16 @@
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#if defined(CONFIG_NAND_U_BOOT)
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_OFFSET (512 * 1024)
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#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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CONFIG_ENV_RANGE)
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#elif !defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
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@ -442,7 +498,7 @@
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PCI
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
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#undef CONFIG_CMD_SAVEENV
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#undef CONFIG_CMD_LOADS
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#endif
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@ -504,7 +560,8 @@
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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