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Merge branch '2019-05-04-master-imports'

Browse source 
- Remove dead code from davinci
- Migrate CONFIG_SUPPORT_EMMC_BOOT
This commit is contained in:
Tom Rini 2019-05-04 19:58:09 -04:00
commit 2dc426418f
137 changed files with 84 additions and 1665 deletions
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3
README
View file

@ -1120,9 +1120,6 @@ The following options need to be configured:
CONFIG_SH_MMCIF_CLK
Define the clock frequency for MMCIF
CONFIG_SUPPORT_EMMC_BOOT
Enable some additional features of the eMMC boot partitions.
- USB Device Firmware Update (DFU) class support:
CONFIG_DFU_OVER_USB
This enables the USB portion of the DFU USB class

1
arch/arm/mach-davinci/Makefile
View file

@ -12,7 +12,6 @@ obj-$(CONFIG_SOC_DM365) += dm365.o
obj-$(CONFIG_SOC_DM644X) += dm644x.o
obj-$(CONFIG_SOC_DM646X) += dm646x.o
obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o

116
arch/arm/mach-davinci/cpu.c
View file

@ -27,25 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
/* SOC-specific pll info */
#ifdef CONFIG_SOC_DM355
#define ARM_PLLDIV PLLC_PLLDIV1
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_SOC_DM644X
#define ARM_PLLDIV PLLC_PLLDIV2
#define DSP_PLLDIV PLLC_PLLDIV1
#define DDR_PLLDIV PLLC_PLLDIV2
#endif
#ifdef CONFIG_SOC_DM646X
#define DSP_PLLDIV PLLC_PLLDIV1
#define ARM_PLLDIV PLLC_PLLDIV2
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_SOC_DA8XX
unsigned int sysdiv[9] = {
PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
@ -110,103 +91,6 @@ int set_cpu_clk_info(void)
return 0;
}
#else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(volatile void *pllbase, unsigned offset)
{
u32 div;
div = REG(pllbase + offset);
return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
}
static inline unsigned pll_prediv(volatile void *pllbase)
{
#ifdef CONFIG_SOC_DM355
/* this register read seems to fail on pll0 */
if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
return 8;
else
return pll_div(pllbase, PLLC_PREDIV);
#elif defined(CONFIG_SOC_DM365)
return pll_div(pllbase, PLLC_PREDIV);
#endif
return 1;
}
static inline unsigned pll_postdiv(volatile void *pllbase)
{
#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
return pll_div(pllbase, PLLC_POSTDIV);
#elif defined(CONFIG_SOC_DM6446)
if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
return pll_div(pllbase, PLLC_POSTDIV);
#endif
return 1;
}
static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
{
volatile void *pllbase = (volatile void *) pll_addr;
#ifdef CONFIG_SOC_DM646X
unsigned base = CONFIG_REFCLK_FREQ / 1000;
#else
unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
#endif
/* the PLL might be bypassed */
if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
base /= pll_prediv(pllbase);
#if defined(CONFIG_SOC_DM365)
base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
#else
base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
#endif
base /= pll_postdiv(pllbase);
}
return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
}
#ifdef DAVINCI_DM6467EVM
unsigned int davinci_arm_clk_get()
{
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
}
#endif
#if defined(CONFIG_SOC_DM365)
unsigned int davinci_clk_get(unsigned int div)
{
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
}
#endif
int set_cpu_clk_info(void)
{
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
#if defined(CONFIG_SOC_DM365)
pllbase = DAVINCI_PLL_CNTRL1_BASE;
#endif
gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
#ifdef DSP_PLLDIV
gd->bd->bi_dsp_freq =
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
#else
gd->bd->bi_dsp_freq = 0;
#endif
pllbase = DAVINCI_PLL_CNTRL1_BASE;
#if defined(CONFIG_SOC_DM365)
pllbase = DAVINCI_PLL_CNTRL0_BASE;
#endif
gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
return 0;
}
#endif /* !CONFIG_SOC_DA8XX */
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()

29
arch/arm/mach-davinci/dm355.c
View file

@ -1,29 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SoC-specific code for tms320dm355 and similar chips
*
* Copyright (C) 2009 David Brownell
*/
#include <common.h>
#include <asm/arch/hardware.h>
void davinci_enable_uart0(void)
{
lpsc_on(DAVINCI_LPSC_UART0);
/* Bringup UART0 out of reset */
REG(UART0_PWREMU_MGMT) = 0x00006001;
}
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
/* Enable I2C pin Mux */
REG(PINMUX3) |= (1 << 20) | (1 << 19);
}
#endif

19
arch/arm/mach-davinci/dm365.c
View file

@ -1,19 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SoC-specific code for tms320dm365 and similar chips
*/
#include <common.h>
#include <asm/arch/hardware.h>
void davinci_enable_uart0(void)
{
lpsc_on(DAVINCI_LPSC_UART0);
}
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
}
#endif

459
arch/arm/mach-davinci/dm365_lowlevel.c
View file

@ -1,459 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SoC-specific lowlevel code for tms320dm365 and similar chips
* Actually used for booting from NAND with nand_spl.
*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*/
#include <common.h>
#include <nand.h>
#include <ns16550.h>
#include <post.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/dm365_lowlevel.h>
#include <asm/arch/hardware.h>
void dm365_waitloop(unsigned long loopcnt)
{
unsigned long i;
for (i = 0; i < loopcnt; i++)
asm(" NOP");
}
int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
{
unsigned int clksrc = 0x0;
/* Power up the PLL */
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
setbits_le32(&dv_pll0_regs->pllctl,
clksrc << PLLCTL_CLOCK_MODE_SHIFT);
/*
* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
* through MMR
*/
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
/* Set PLLEN=0 => PLL BYPASS MODE */
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
dm365_waitloop(150);
/* PLLRST=1(reset assert) */
setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
dm365_waitloop(300);
/*Bring PLL out of Reset*/
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
/* Program the Multiper and Pre-Divider for PLL1 */
writel(pllmult, &dv_pll0_regs->pllm);
writel(prediv, &dv_pll0_regs->prediv);
/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
&dv_pll0_regs->secctl);
/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
/* Program the PostDiv for PLL1 */
writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
/* Post divider setting for PLL1 */
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
dm365_waitloop(300);
/* Set the GOSET bit */
writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
dm365_waitloop(300);
/* Wait for PLL to LOCK */
while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
== PLL0_LOCK))
;
/* Enable the PLL Bit of PLLCTL*/
setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
return 0;
}
int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
{
unsigned int clksrc = 0x0;
/* Power up the PLL*/
clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
/*
* Select the Clock Mode as Onchip Oscilator or External Clock on
* MXI pin
* VDB has input on MXI pin
*/
clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
setbits_le32(&dv_pll1_regs->pllctl,
clksrc << PLLCTL_CLOCK_MODE_SHIFT);
/*
* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
* through MMR
*/
clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
/* Set PLLEN=0 => PLL BYPASS MODE */
clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
dm365_waitloop(50);
/* PLLRST=1(reset assert) */
setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
dm365_waitloop(300);
/* Bring PLL out of Reset */
clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
/* Program the Multiper and Pre-Divider for PLL2 */
writel(pllm, &dv_pll1_regs->pllm);
writel(prediv, &dv_pll1_regs->prediv);
writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
&dv_pll1_regs->secctl);
/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
/* Post divider setting for PLL2 */
writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
/* GoCmd for PostDivider to take effect */
writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
dm365_waitloop(150);
/* Wait for PLL to LOCK */
while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
== PLL1_LOCK))
;
dm365_waitloop(4100);
/* Enable the PLL2 */
setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
/* do this after PLL's have been set up */
writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
&dv_sys_module_regs->peri_clkctl);
return 0;
}
int dm365_ddr_setup(void)
{
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
clrbits_le32(&dv_sys_module_regs->vtpiocr,
VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
/* Set bit CLRZ (bit 13) */
setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
/* Check VTP READY Status */
while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
;
/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
/* Set bit LOCK(bit7) */
setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
/*
* Powerdown VTP as it is locked (bit 6)
* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
*/
setbits_le32(&dv_sys_module_regs->vtpiocr,
VPTIO_IOPWRDN | VPTIO_PWRDN);
/* Wait for calibration to complete */
dm365_waitloop(150);
/* Set the DDR2 to synreset, then enable it again */
lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
/* Program SDRAM Bank Config Register */
writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
&dv_ddr2_regs_ctrl->sdbcr);
writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
&dv_ddr2_regs_ctrl->sdbcr);
/* Program SDRAM Timing Control Register1 */
writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
/* Program SDRAM Timing Control Register2 */
writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
/* Program SDRAM Refresh Control Register */
writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
return 0;
}
static void dm365_vpss_sync_reset(void)
{
unsigned int PdNum = 0;
/* VPSS_CLKMD 1:1 */
setbits_le32(&dv_sys_module_regs->vpss_clkctl,
VPSS_CLK_CTL_VPSS_CLKMD);
/* LPSC SyncReset DDR Clock Enable */
writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
writel((1 << PdNum), &dv_psc_regs->ptcmd);
while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
;
while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
PSC_MD_STATE_MSK) == PSC_SYNCRESET))
;
}
static void dm365_por_reset(void)
{
struct davinci_timer *wdog =
(struct davinci_timer *)DAVINCI_WDOG_BASE;
if (readl(&dv_pll0_regs->rstype) &
(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
dm365_vpss_sync_reset();
writel(DV_TMPBUF_VAL, TMPBUF);
setbits_le32(TMPSTATUS, FLAG_PORRST);
writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
while (1);
}
}
static void dm365_wdt_reset(void)
{
struct davinci_timer *wdog =
(struct davinci_timer *)DAVINCI_WDOG_BASE;
if (readl(TMPBUF) != DV_TMPBUF_VAL) {
writel(DV_TMPBUF_VAL, TMPBUF);
setbits_le32(TMPSTATUS, FLAG_PORRST);
setbits_le32(TMPSTATUS, FLAG_FLGOFF);
dm365_waitloop(100);
dm365_vpss_sync_reset();
writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
while (1);
}
}
static void dm365_wdt_flag_on(void)
{
/* VPSS_CLKMD 1:2 */
clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
VPSS_CLK_CTL_VPSS_CLKMD);
writel(0, TMPBUF);
setbits_le32(TMPSTATUS, FLAG_FLGON);
}
void dm365_psc_init(void)
{
unsigned char i = 0;
unsigned char lpsc_start;
unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
unsigned int PdNum = 0;
lpscmin = 0;
lpscmax = 2;
for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
if (lpscgroup == 0) {
/* Enabling LPSC 3 to 28 SCR first */
lpsc_start = DAVINCI_LPSC_VPSSMSTR;
lpsc_end = DAVINCI_LPSC_TIMER1;
} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
lpsc_start = DAVINCI_LPSC_CFG5;
lpsc_end = DAVINCI_LPSC_VPSSMASTER;
} else {
lpsc_start = DAVINCI_LPSC_MJCP;
lpsc_end = DAVINCI_LPSC_HDVICP;
}
/* NEXT=0x3, Enable LPSC's */
for (i = lpsc_start; i <= lpsc_end; i++)
setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
/*
* Program goctl to start transition sequence for LPSCs
* CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
* Domain 0 Modules
*/
writel((1 << PdNum), &dv_psc_regs->ptcmd);
/*
* Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
*/
while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
== 0))
;
/* Wait for MODSTAT = ENABLE from LPSC's */
for (i = lpsc_start; i <= lpsc_end; i++)
while (!((readl(&dv_psc_regs->mdstat[i]) &
PSC_MD_STATE_MSK) == PSC_ENABLE))
;
}
}
static void dm365_emif_init(void)
{
writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
return;
}
void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value)
{
clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
}
__attribute__((weak))
void board_gpio_init(void)
{
return;
}
#if defined(CONFIG_POST)
int post_log(char *format, ...)
{
return 0;
}
#endif
void dm36x_lowlevel_init(ulong bootflag)
{
struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
(struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
DAVINCI_UART_CTRL_BASE);
/* Mask all interrupts */
writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
writel(0x0, &dv_aintc_regs->eabase);
writel(0x0, &dv_aintc_regs->eint0);
writel(0x0, &dv_aintc_regs->eint1);
/* Clear all interrupts */
writel(0xffffffff, &dv_aintc_regs->fiq0);
writel(0xffffffff, &dv_aintc_regs->fiq1);
writel(0xffffffff, &dv_aintc_regs->irq0);
writel(0xffffffff, &dv_aintc_regs->irq1);
dm365_por_reset();
dm365_wdt_reset();
/* System PSC setup - enable all */
dm365_psc_init();
/* Setup Pinmux */
dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
/* PLL setup */
dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
CONFIG_SYS_DM36x_PLL1_PREDIV);
dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
CONFIG_SYS_DM36x_PLL2_PREDIV);
/* GPIO setup */
board_gpio_init();
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
/*
* Fix Power and Emulation Management Register
* see sprufh2.pdf page 38 Table 22
*/
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart_ctrl_regs->pwremu_mgmt);
puts("ddr init\n");
dm365_ddr_setup();
puts("emif init\n");
dm365_emif_init();
dm365_wdt_flag_on();
#if defined(CONFIG_POST)
/*
* Do memory tests, calls arch_memory_failure_handle()
* if error detected.
*/
memory_post_test(0);
#endif
}

80
arch/arm/mach-davinci/dm644x.c
View file

@ -1,80 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SoC-specific code for tms320dm644x chips
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2004 Texas Instruments.
*/
#include <common.h>
#include <asm/arch/hardware.h>
#define PINMUX0_EMACEN (1 << 31)
#define PINMUX0_AECS5 (1 << 11)
#define PINMUX0_AECS4 (1 << 10)
#define PINMUX1_I2C (1 << 7)
#define PINMUX1_UART1 (1 << 1)
#define PINMUX1_UART0 (1 << 0)
void davinci_enable_uart0(void)
{
lpsc_on(DAVINCI_LPSC_UART0);
/* Bringup UART0 out of reset */
REG(UART0_PWREMU_MGMT) = 0x00006001;
/* Enable UART0 MUX lines */
REG(PINMUX1) |= PINMUX1_UART0;
}
#ifdef CONFIG_DRIVER_TI_EMAC
void davinci_enable_emac(void)
{
lpsc_on(DAVINCI_LPSC_EMAC);
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
lpsc_on(DAVINCI_LPSC_MDIO);
/* Enable GIO3.3V cells used for EMAC */
REG(VDD3P3V_PWDN) = 0;
/* Enable EMAC. */
REG(PINMUX0) |= PINMUX0_EMACEN;
}
#endif
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
/* Enable I2C pin Mux */
REG(PINMUX1) |= PINMUX1_I2C;
}
#endif
void davinci_errata_workarounds(void)
{
/*
* Workaround for TMS320DM6446 errata 1.3.22:
* PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
* Revision(s) Affected: 1.3 and earlier
*/
REG(PSC_SILVER_BULLET) = 0;
/*
* Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
* as suggested in TMS320DM6446 errata 2.1.2:
*
* On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
* low priority modules can occupy the bus and prevent high priority
* modules like the VPSS from getting the required DDR2 throughput.
* A hex value of 0x20 should provide a good ARM (cache enabled)
* performance and still allow good utilization by the VPSS or other
* modules.
*/
REG(VBPR) = 0x20;
}

25
arch/arm/mach-davinci/dm646x.c
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SoC-specific code for TMS320DM646x chips
*/
#include <asm/arch/hardware.h>
void davinci_enable_uart0(void)
{
lpsc_on(DAVINCI_DM646X_LPSC_UART0);
}
#ifdef CONFIG_DRIVER_TI_EMAC
void davinci_enable_emac(void)
{
lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
}
#endif
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_DM646X_LPSC_I2C);
}
#endif

127
arch/arm/mach-davinci/dp83848.c
View file

@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* National Semiconductor DP83848 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* --------------------------------------------------------
*/
#include <common.h>
#include <net.h>
#include <dp83848.h>
#include <asm/arch/emac_defs.h>
#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_CMD_NET
int dp83848_is_phy_connected(int phy_addr)
{
u_int16_t id1, id2;
if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
return(0);
if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
return(0);
if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
return(1);
return(0);
}
int dp83848_get_link_speed(int phy_addr)
{
u_int16_t tmp;
volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
return(0);
if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
return(0);
if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
if (tmp & DP83848_DUPLEX) {
/* set DM644x EMAC for Full Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
/*set DM644x EMAC for Half Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
return(1);
}
int dp83848_init_phy(int phy_addr)
{
int ret = 1;
if (!dp83848_get_link_speed(phy_addr)) {
/* Try another time */
udelay(100000);
ret = dp83848_get_link_speed(phy_addr);
}
/* Disable PHY Interrupts */
davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
return(ret);
}
int dp83848_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/* Set the Auto_negotiation Advertisement Register
* MII advertising for Next page, 100BaseTxFD and HD,
* 10BaseTFD and HD, IEEE 802.3
*/
tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
/* Read Control Register */
if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
return(0);
tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/* Restart Auto_negotiation */
tmp |= DP83848_RESTART_AUTONEG;
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/*check AutoNegotiate complete */
udelay(10000);
if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
return(0);
if (!(tmp & DP83848_AUTONEG_COMP))
return(0);
return (dp83848_get_link_speed(phy_addr));
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

41
arch/arm/mach-davinci/et1011c.c
View file

@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <common.h>
#include <net.h>
#include <miiphy.h>
#include <asm/arch/emac_defs.h>
#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_CMD_NET
/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
#define MII_PHY_CONFIG_REG 22
/* PHY Config bits */
#define PHY_SYS_CLK_EN (1 << 4)
int et1011c_get_link_speed(int phy_addr)
{
u_int16_t data;
if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
/* Enable 125MHz clock sourced from PHY */
davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
data | PHY_SYS_CLK_EN);
return (1);
}
return (0);
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

4
arch/arm/mach-davinci/include/mach/davinci_misc.h
View file

@ -40,13 +40,11 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
int n_items);
#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
#if defined(CONFIG_DRIVER_TI_EMAC)
void davinci_emac_mii_mode_sel(int mode_sel);
#endif
#if defined(CONFIG_SOC_DA8XX)
void irq_init(void);
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items);
#endif
#endif /* __MISC_H */

56
arch/arm/mach-davinci/include/mach/emac_defs.h
View file

@ -23,71 +23,15 @@
#include <asm/arch/hardware.h>
#ifdef CONFIG_SOC_DM365
#define EMAC_BASE_ADDR (0x01d07000)
#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
#define DAVINCI_EMAC_VERSION2
#elif defined(CONFIG_SOC_DA8XX)
#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
#define DAVINCI_EMAC_VERSION2
#else
#define EMAC_BASE_ADDR (0x01c80000)
#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
#define EMAC_MDIO_BASE_ADDR (0x01c84000)
#endif
#ifdef CONFIG_SOC_DM646X
#define DAVINCI_EMAC_VERSION2
#define DAVINCI_EMAC_GIG_ENABLE
#endif
#ifdef CONFIG_SOC_DM646X
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 76500000
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
#elif defined(CONFIG_SOC_DM365)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 121500000
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
#elif defined(CONFIG_SOC_DA8XX)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
#else
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
#endif
#define PHY_KSZ8873 (0x00221450)
int ksz8873_is_phy_connected(int phy_addr);
int ksz8873_get_link_speed(int phy_addr);
int ksz8873_init_phy(int phy_addr);
int ksz8873_auto_negotiate(int phy_addr);
#define PHY_LXT972 (0x001378e2)
int lxt972_is_phy_connected(int phy_addr);
int lxt972_get_link_speed(int phy_addr);
int lxt972_init_phy(int phy_addr);
int lxt972_auto_negotiate(int phy_addr);
#define PHY_DP83848 (0x20005c90)
int dp83848_is_phy_connected(int phy_addr);
int dp83848_get_link_speed(int phy_addr);
int dp83848_init_phy(int phy_addr);
int dp83848_auto_negotiate(int phy_addr);
#define PHY_ET1011C (0x282f013)
int et1011c_get_link_speed(int phy_addr);
#endif /* _DM644X_EMAC_H_ */

14
arch/arm/mach-davinci/include/mach/gpio.h
View file

@ -5,21 +5,12 @@
#ifndef _GPIO_DEFS_H_
#define _GPIO_DEFS_H_
#ifndef CONFIG_SOC_DA8XX
#define DAVINCI_GPIO_BINTEN 0x01C67008
#define DAVINCI_GPIO_BANK01 0x01C67010
#define DAVINCI_GPIO_BANK23 0x01C67038
#define DAVINCI_GPIO_BANK45 0x01C67060
#define DAVINCI_GPIO_BANK67 0x01C67088
#else /* CONFIG_SOC_DA8XX */
#define DAVINCI_GPIO_BINTEN 0x01E26008
#define DAVINCI_GPIO_BANK01 0x01E26010
#define DAVINCI_GPIO_BANK23 0x01E26038
#define DAVINCI_GPIO_BANK45 0x01E26060
#define DAVINCI_GPIO_BANK67 0x01E26088
#define DAVINCI_GPIO_BANK8 0x01E260B0
#endif /* CONFIG_SOC_DA8XX */
#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
@ -31,10 +22,7 @@
#define gpio_status() gpio_info()
#endif
#define GPIO_NAME_SIZE 20
#if defined(CONFIG_SOC_DM644X)
/* GPIO0 to GPIO53, omit the V3.3 volts one */
#define MAX_NUM_GPIOS 70
#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
#if !defined(CONFIG_SOC_DA850)
#define MAX_NUM_GPIOS 128
#else
#define MAX_NUM_GPIOS 144

216
arch/arm/mach-davinci/include/mach/hardware.h
View file

@ -23,89 +23,6 @@ typedef volatile unsigned int dv_reg;
typedef volatile unsigned int * dv_reg_p;
#endif
/*
* Base register addresses
*
* NOTE: some of these DM6446-specific addresses DO NOT WORK
* on other DaVinci chips. Double check them before you try
* using the addresses ... or PSC module identifiers, etc.
*/
#ifndef CONFIG_SOC_DA8XX
#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
#define DAVINCI_UART0_BASE (0x01c20000)
#define DAVINCI_UART1_BASE (0x01c20400)
#define DAVINCI_TIMER3_BASE (0x01c20800)
#define DAVINCI_I2C_BASE (0x01c21000)
#define DAVINCI_TIMER0_BASE (0x01c21400)
#define DAVINCI_TIMER1_BASE (0x01c21800)
#define DAVINCI_WDOG_BASE (0x01c21c00)
#define DAVINCI_PWM0_BASE (0x01c22000)
#define DAVINCI_PWM1_BASE (0x01c22400)
#define DAVINCI_PWM2_BASE (0x01c22800)
#define DAVINCI_TIMER4_BASE (0x01c23800)
#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
#define DAVINCI_ARM_INTC_BASE (0x01c48000)
#define DAVINCI_USB_OTG_BASE (0x01c64000)
#define DAVINCI_CFC_ATA_BASE (0x01c66000)
#define DAVINCI_SPI_BASE (0x01c66800)
#define DAVINCI_GPIO_BASE (0x01c67000)
#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
#if !defined(CONFIG_SOC_DM646X)
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
#endif
#define DAVINCI_DDR_BASE (0x80000000)
#ifdef CONFIG_SOC_DM644X
#define DAVINCI_UART2_BASE 0x01c20800
#define DAVINCI_UHPI_BASE 0x01c67800
#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
#define DAVINCI_IMCOP_BASE 0x01cc0000
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
#define DAVINCI_VLYNQ_BASE 0x01e01000
#define DAVINCI_ASP_BASE 0x01e02000
#define DAVINCI_MMC_SD_BASE 0x01e10000
#define DAVINCI_MS_BASE 0x01e20000
#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
#elif defined(CONFIG_SOC_DM355)
#define DAVINCI_MMC_SD1_BASE 0x01e00000
#define DAVINCI_ASP0_BASE 0x01e02000
#define DAVINCI_ASP1_BASE 0x01e04000
#define DAVINCI_UART2_BASE 0x01e06000
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
#define DAVINCI_MMC_SD0_BASE 0x01e11000
#elif defined(CONFIG_SOC_DM365)
#define DAVINCI_MMC_SD1_BASE 0x01d00000
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
#define DAVINCI_MMC_SD0_BASE 0x01d11000
#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
#define DAVINCI_SPI0_BASE 0x01c66000
#define DAVINCI_SPI1_BASE 0x01c66800
#elif defined(CONFIG_SOC_DM646X)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
#endif
#else /* CONFIG_SOC_DA8XX */
#define DAVINCI_UART0_BASE 0x01c42000
#define DAVINCI_UART1_BASE 0x01d0c000
#define DAVINCI_UART2_BASE 0x01d0d000
@ -162,66 +79,11 @@ typedef volatile unsigned int * dv_reg_p;
#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1
#ifndef CONFIG_SOC_DA8XX
#define DAVINCI_LPSC_VPSSMSTR 0
#define DAVINCI_LPSC_VPSSSLV 1
#define DAVINCI_LPSC_TPCC 2
#define DAVINCI_LPSC_TPTC0 3
#define DAVINCI_LPSC_TPTC1 4
#define DAVINCI_LPSC_EMAC 5
#define DAVINCI_LPSC_EMAC_WRAPPER 6
#define DAVINCI_LPSC_MDIO 7
#define DAVINCI_LPSC_IEEE1394 8
#define DAVINCI_LPSC_USB 9
#define DAVINCI_LPSC_ATA 10
#define DAVINCI_LPSC_VLYNQ 11
#define DAVINCI_LPSC_UHPI 12
#define DAVINCI_LPSC_DDR_EMIF 13
#define DAVINCI_LPSC_AEMIF 14
#define DAVINCI_LPSC_MMC_SD 15
#define DAVINCI_LPSC_MEMSTICK 16
#define DAVINCI_LPSC_McBSP 17
#define DAVINCI_LPSC_I2C 18
#define DAVINCI_LPSC_UART0 19
#define DAVINCI_LPSC_UART1 20
#define DAVINCI_LPSC_UART2 21
#define DAVINCI_LPSC_SPI 22
#define DAVINCI_LPSC_PWM0 23
#define DAVINCI_LPSC_PWM1 24
#define DAVINCI_LPSC_PWM2 25
#define DAVINCI_LPSC_GPIO 26
#define DAVINCI_LPSC_TIMER0 27
#define DAVINCI_LPSC_TIMER1 28
#define DAVINCI_LPSC_TIMER2 29
#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
#define DAVINCI_LPSC_ARM 31
#define DAVINCI_LPSC_SCR2 32
#define DAVINCI_LPSC_SCR3 33
#define DAVINCI_LPSC_SCR4 34
#define DAVINCI_LPSC_CROSSBAR 35
#define DAVINCI_LPSC_CFG27 36
#define DAVINCI_LPSC_CFG3 37
#define DAVINCI_LPSC_CFG5 38
#define DAVINCI_LPSC_GEM 39
#define DAVINCI_LPSC_IMCOP 40
#define DAVINCI_LPSC_VPSSMASTER 47
#define DAVINCI_LPSC_MJCP 50
#define DAVINCI_LPSC_HDVICP 51
#define DAVINCI_DM646X_LPSC_EMAC 14
#define DAVINCI_DM646X_LPSC_UART0 26
#define DAVINCI_DM646X_LPSC_I2C 31
#define DAVINCI_DM646X_LPSC_TIMER0 34
#else /* CONFIG_SOC_DA8XX */
#define DAVINCI_LPSC_TPCC 0
#define DAVINCI_LPSC_TPTC0 1
#define DAVINCI_LPSC_TPTC1 2
@ -283,8 +145,6 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
#endif /* CONFIG_SOC_DA8XX */
#ifndef __ASSEMBLY__
void lpsc_on(unsigned int id);
void lpsc_syncreset(unsigned int id);
@ -296,30 +156,6 @@ void davinci_enable_emac(void);
void davinci_enable_i2c(void);
void davinci_errata_workarounds(void);
#ifndef CONFIG_SOC_DA8XX
/* Some PSC defines */
#define PSC_CHP_SHRTSW (0x01c40038)
#define PSC_GBLCTL (0x01c41010)
#define PSC_EPCPR (0x01c41070)
#define PSC_EPCCR (0x01c41078)
#define PSC_PTCMD (0x01c41120)
#define PSC_PTSTAT (0x01c41128)
#define PSC_PDSTAT (0x01c41200)
#define PSC_PDSTAT1 (0x01c41204)
#define PSC_PDCTL (0x01c41300)
#define PSC_PDCTL1 (0x01c41304)
#define PSC_MDCTL_BASE (0x01c41a00)
#define PSC_MDSTAT_BASE (0x01c41800)
#define VDD3P3V_PWDN (0x01c40048)
#define UART0_PWREMU_MGMT (0x01c20030)
#define PSC_SILVER_BULLET (0x01c41a20)
#else /* CONFIG_SOC_DA8XX */
#define PSC_ENABLE 0x3
#define PSC_DISABLE 0x2
#define PSC_SYNCRESET 0x1
@ -354,41 +190,9 @@ struct davinci_psc_regs {
#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
#endif /* CONFIG_SOC_DA8XX */
#define PSC_MDSTAT_STATE 0x3f
#define PSC_MDCTL_NEXT 0x07
#ifndef CONFIG_SOC_DA8XX
/* Miscellania... */
#define VBPR (0x20000020)
/* NOTE: system control modules are *highly* chip-specific, both
* as to register content (e.g. for muxing) and which registers exist.
*/
#define PINMUX0 0x01c40000
#define PINMUX1 0x01c40004
#define PINMUX2 0x01c40008
#define PINMUX3 0x01c4000c
#define PINMUX4 0x01c40010
struct davinci_uart_ctrl_regs {
dv_reg revid1;
dv_reg res;
dv_reg pwremu_mgmt;
dv_reg mdr;
};
#define DAVINCI_UART_CTRL_BASE 0x28
/* UART PWREMU_MGMT definitions */
#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
#else /* CONFIG_SOC_DA8XX */
struct davinci_pllc_regs {
dv_reg revid;
dv_reg rsvd1[56];
@ -606,26 +410,6 @@ static inline enum davinci_clk_ids get_async3_src(void)
DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
}
#endif /* CONFIG_SOC_DA8XX */
#if defined(CONFIG_SOC_DM365)
#include <asm/arch/aintc_defs.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pll_defs.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/syscfg_defs.h>
#include <asm/arch/timer_defs.h>
#define TMPBUF 0x00017ff8
#define TMPSTATUS 0x00017ff0
#define DV_TMPBUF_VAL 0x591b3ed7
#define FLAG_PORRST 0x00000001
#define FLAG_WDTRST 0x00000002
#define FLAG_FLGON 0x00000004
#define FLAG_FLGOFF 0x00000010
#endif
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_ARCH_HARDWARE_H */

4
arch/arm/mach-davinci/include/mach/i2c_defs.h
View file

@ -8,10 +8,6 @@
#ifndef _I2C_DEFS_H_
#define _I2C_DEFS_H_
#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
#else
#define I2C_BASE 0x01c22000
#endif
#endif

49
arch/arm/mach-davinci/include/mach/syscfg_defs.h
View file

@ -1,49 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*/
#ifndef _DV_SYSCFG_DEFS_H_
#define _DV_SYSCFG_DEFS_H_
#ifndef CONFIG_SOC_DA8XX
/* System Control Module register structure for DM365 */
struct dv_sys_module_regs {
unsigned int pinmux[5]; /* 0x00 */
unsigned int bootcfg; /* 0x14 */
unsigned int arm_intmux; /* 0x18 */
unsigned int edma_evtmux; /* 0x1C */
unsigned int ddr_slew; /* 0x20 */
unsigned int clkout; /* 0x24 */
unsigned int device_id; /* 0x28 */
unsigned int vdac_config; /* 0x2C */
unsigned int timer64_ctl; /* 0x30 */
unsigned int usbbphy_ctl; /* 0x34 */
unsigned int misc; /* 0x38 */
unsigned int mstpri[2]; /* 0x3C */
unsigned int vpss_clkctl; /* 0x44 */
unsigned int peri_clkctl; /* 0x48 */
unsigned int deepsleep; /* 0x4C */
unsigned int dft_enable; /* 0x50 */
unsigned int debounce[8]; /* 0x54 */
unsigned int vtpiocr; /* 0x74 */
unsigned int pupdctl0; /* 0x78 */
unsigned int pupdctl1; /* 0x7C */
unsigned int hdimcopbt; /* 0x80 */
unsigned int pll0_config; /* 0x84 */
unsigned int pll1_config; /* 0x88 */
};
#define VPTIO_RDY (1 << 15)
#define VPTIO_IOPWRDN (1 << 14)
#define VPTIO_CLRZ (1 << 13)
#define VPTIO_LOCK (1 << 7)
#define VPTIO_PWRDN (1 << 6)
#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
#define dv_sys_module_regs \
((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
#endif /* !CONFIG_SOC_DA8XX */
#endif /* _DV_SYSCFG_DEFS_H_ */

52
arch/arm/mach-davinci/ksz8873.c
View file

@ -1,52 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Micrel KSZ8873 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2011 Heiko Schocher <hsdenx.de>
*
* based on:
* National Semiconductor DP83848 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* --------------------------------------------------------
*/
#include <common.h>
#include <miiphy.h>
#include <net.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "../../../drivers/net/ti/davinci_emac.h"
int ksz8873_is_phy_connected(int phy_addr)
{
u_int16_t dummy;
return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
}
int ksz8873_get_link_speed(int phy_addr)
{
emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
/* we always have a link to the switch, 100 FD */
writel((EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
&emac->MACCONTROL);
return 1;
}
int ksz8873_init_phy(int phy_addr)
{
return 1;
}
int ksz8873_auto_negotiate(int phy_addr)
{
return dp83848_get_link_speed(phy_addr);
}

112
arch/arm/mach-davinci/lxt972.c
View file

@ -1,112 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Intel LXT971/LXT972 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* --------------------------------------------------------
*/
#include <common.h>
#include <net.h>
#include <miiphy.h>
#include <lxt971a.h>
#include <asm/arch/emac_defs.h>
#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_CMD_NET
int lxt972_is_phy_connected(int phy_addr)
{
u_int16_t id1, id2;
if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
return(0);
if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
return(0);
if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
return(1);
return(0);
}
int lxt972_get_link_speed(int phy_addr)
{
u_int16_t stat1, tmp;
volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
return(0);
if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
return(0);
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
return(0);
tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
/* Read back */
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
/* set DM644x EMAC for Full Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
/*set DM644x EMAC for Half Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
return(1);
}
int lxt972_init_phy(int phy_addr)
{
int ret = 1;
if (!lxt972_get_link_speed(phy_addr)) {
/* Try another time */
ret = lxt972_get_link_speed(phy_addr);
}
/* Disable PHY Interrupts */
davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
return(ret);
}
int lxt972_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp |= BMCR_ANRESTART;
davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
/*check AutoNegotiate complete */
udelay (10000);
if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return(0);
if (!(tmp & BMSR_ANEGCOMPLETE))
return(0);
return (lxt972_get_link_speed(phy_addr));
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

5
arch/arm/mach-davinci/misc.c
View file

@ -68,7 +68,6 @@ err:
/*
* Set the mii mode as MII or RMII
*/
#if defined(CONFIG_SOC_DA8XX)
void davinci_emac_mii_mode_sel(int mode_sel)
{
int val;
@ -80,7 +79,7 @@ void davinci_emac_mii_mode_sel(int mode_sel)
val |= (1 << 8);
writel(val, &davinci_syscfg_regs->cfgchip3);
}
#endif
/*
* If there is no MAC address in the environment, then it will be initialized
* (silently) from the value in the EEPROM.
@ -106,7 +105,6 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
}
#endif /* CONFIG_DRIVER_TI_EMAC */
#if defined(CONFIG_SOC_DA8XX)
void irq_init(void)
{
/*
@ -135,4 +133,3 @@ int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
return 0;
}
#endif

76
arch/arm/mach-davinci/psc.c
View file

@ -33,19 +33,8 @@
static void lpsc_transition(unsigned int id, unsigned int state)
{
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
#ifdef CONFIG_SOC_DA8XX
struct davinci_psc_regs *psc_regs;
#endif
#ifndef CONFIG_SOC_DA8XX
if (id >= DAVINCI_LPSC_GEM)
return; /* Don't work on DSP Power Domain */
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
ptstat = REG_P(PSC_PTSTAT);
ptcmd = REG_P(PSC_PTCMD);
#else
if (id < DAVINCI_LPSC_PSC1_BASE) {
if (id >= PSC_PSC0_MODULE_ID_CNT)
return;
@ -62,7 +51,6 @@ static void lpsc_transition(unsigned int id, unsigned int state)
}
ptstat = &psc_regs->ptstat;
ptcmd = &psc_regs->ptcmd;
#endif
while (readl(ptstat) & 0x01)
continue;
@ -71,29 +59,6 @@ static void lpsc_transition(unsigned int id, unsigned int state)
return; /* Already in that state */
writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
switch (id) {
#ifdef CONFIG_SOC_DM644X
/* Special treatment for some modules as for sprue14 p.7.4.2 */
case DAVINCI_LPSC_VPSSSLV:
case DAVINCI_LPSC_EMAC:
case DAVINCI_LPSC_EMAC_WRAPPER:
case DAVINCI_LPSC_MDIO:
case DAVINCI_LPSC_USB:
case DAVINCI_LPSC_ATA:
case DAVINCI_LPSC_VLYNQ:
case DAVINCI_LPSC_UHPI:
case DAVINCI_LPSC_DDR_EMIF:
case DAVINCI_LPSC_AEMIF:
case DAVINCI_LPSC_MMC_SD:
case DAVINCI_LPSC_MEMSTICK:
case DAVINCI_LPSC_McBSP:
case DAVINCI_LPSC_GPIO:
writel(readl(mdctl) | 0x200, mdctl);
break;
#endif
}
writel(0x01, ptcmd);
while (readl(ptstat) & 0x01)
@ -116,44 +81,3 @@ void lpsc_disable(unsigned int id)
{
lpsc_transition(id, 0x0);
}
/* Not all DaVinci chips have a DSP power domain. */
#ifdef CONFIG_SOC_DM644X
/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
#if !defined(CONFIG_SYS_USE_DSPLINK)
void dsp_on(void)
{
int i;
if (REG(PSC_PDSTAT1) & 0x1f)
return; /* Already on */
REG(PSC_GBLCTL) |= 0x01;
REG(PSC_PDCTL1) |= 0x01;
REG(PSC_PDCTL1) &= ~0x100;
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
REG(PSC_PTCMD) = 0x02;
for (i = 0; i < 100; i++) {
if (REG(PSC_EPCPR) & 0x02)
break;
}
REG(PSC_CHP_SHRTSW) = 0x01;
REG(PSC_PDCTL1) |= 0x100;
REG(PSC_EPCCR) = 0x02;
for (i = 0; i < 100; i++) {
if (!(REG(PSC_PTSTAT) & 0x02))
break;
}
REG(PSC_GBLCTL) &= ~0x1f;
}
#endif /* CONFIG_SYS_USE_DSPLINK */
#endif /* have a DSP */

5
arch/arm/mach-davinci/spl.c
View file

@ -33,12 +33,7 @@ void putc(char c)
void spl_board_init(void)
{
#ifdef CONFIG_SOC_DM365
dm36x_lowlevel_init(0);
#endif
#ifdef CONFIG_SOC_DA8XX
arch_cpu_init();
#endif
preloader_console_init();
}

2
arch/arm/mach-exynos/Kconfig
View file

@ -116,7 +116,6 @@ config TARGET_SNOW
config TARGET_SPRING
bool "Spring board"
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
select SUPPORT_SPL
config TARGET_SMDK5420
@ -150,7 +149,6 @@ config TARGET_ESPRESSO7420
select OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS7420
select SPL_DISABLE_OF_CONTROL
select SUPPORT_SPL
endchoice

1
configs/am57xx_evm_defconfig
View file

@ -59,6 +59,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y

1
configs/am57xx_hs_evm_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y

1
configs/am57xx_hs_evm_usb_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y

1
configs/apalis-tk1_defconfig
View file

@ -34,6 +34,7 @@ CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
CONFIG_E1000=y
CONFIG_PCI=y

1
configs/apalis_imx6_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/arndale_defconfig
View file

@ -26,6 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y

1
configs/avnet_ultra96_rev1_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_I2C_MUX_PCA954x=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y

1
configs/cl-som-imx7_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0

1
configs/clearfog_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y

1
configs/cm_t54_defconfig
View file

@ -32,6 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SCSI_AHCI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=4

1
configs/colibri_imx6_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/colibri_imx7_emmc_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/display5_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y

1
configs/display5_factory_defconfig
View file

@ -64,6 +64,7 @@ CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y

1
configs/dms-ba16-1g_defconfig
View file

@ -32,6 +32,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0

1
configs/dms-ba16_defconfig
View file

@ -31,6 +31,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0

1
configs/dra7xx_evm_defconfig
View file

@ -65,6 +65,7 @@ CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y

1
configs/dra7xx_hs_evm_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y

1
configs/dra7xx_hs_evm_usb_defconfig
View file

@ -70,6 +70,7 @@ CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y

1
configs/edison_defconfig
View file

@ -30,6 +30,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_CPU=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_RTC_MC146818=y
CONFIG_USB_DWC3_GADGET=y

1
configs/ge_bx50v3_defconfig
View file

@ -42,6 +42,7 @@ CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y

1
configs/gwventana_emmc_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y

1
configs/gwventana_gw5904_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y

1
configs/gwventana_nand_defconfig
View file

@ -64,6 +64,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y

1
configs/imx6dl_mamoj_defconfig
View file

@ -32,6 +32,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/imx8mq_evk_defconfig
View file

@ -29,6 +29,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y

1
configs/imx8qxp_mek_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y

1
configs/liteboard_defconfig
View file

@ -38,6 +38,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y

1
configs/mt7623n_bpir2_defconfig
View file

@ -35,6 +35,7 @@ CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_PHY_FIXED=y

1
configs/mx6sabresd_defconfig
View file

@ -73,6 +73,7 @@ CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y

1
configs/mx7dsabresd_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y

1
configs/mx7dsabresd_qspi_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y

1
configs/mx7ulp_evk_defconfig
View file

@ -21,6 +21,7 @@ CONFIG_IMX_RGPIO2P=y
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y

1
configs/mx7ulp_evk_plugin_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_IMX_RGPIO2P=y
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y

1
configs/odroid-xu3_defconfig
View file

@ -34,6 +34,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x5000000

1
configs/omap5_uevm_defconfig
View file

@ -30,6 +30,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_TCA642X=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=3

1
configs/opos6uldev_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_SYSCON=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_PWRSEQ=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/peach-pi_defconfig
View file

@ -38,6 +38,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y

1
configs/peach-pit_defconfig
View file

@ -37,6 +37,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y

1
configs/pico-hobbit-imx6ul_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/pico-hobbit-imx7d_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y

1
configs/pico-imx6ul_defconfig
View file

@ -47,6 +47,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/pico-imx7d_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y

1
configs/pico-pi-imx6ul_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y

1
configs/pico-pi-imx7d_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y

1
configs/riotboard_defconfig
View file

@ -21,6 +21,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0

1
configs/riotboard_spl_defconfig
View file

@ -31,6 +31,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0

1
configs/smdk5250_defconfig
View file

@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y

1
configs/smdk5420_defconfig
View file

@ -28,6 +28,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y

1
configs/snow_defconfig
View file

@ -43,6 +43,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y

1
configs/spring_defconfig
View file

@ -43,6 +43,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y

1
configs/stm32mp15_basic_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY=y
CONFIG_PHY_STM32_USBPHYC=y

1
configs/stm32mp15_trusted_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY=y
CONFIG_PHY_STM32_USBPHYC=y

1
configs/uniphier_ld4_sld8_defconfig
View file

@ -40,6 +40,7 @@ CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y

1
configs/uniphier_v7_defconfig
View file

@ -39,6 +39,7 @@ CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y

1
configs/uniphier_v8_defconfig
View file

@ -34,6 +34,7 @@ CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y

1
configs/vinco_defconfig
View file

@ -27,6 +27,7 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000

1
configs/vining_2000_defconfig
View file

@ -33,6 +33,7 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y

1
configs/warp7_bl33_defconfig
View file

@ -29,6 +29,7 @@ CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y

1
configs/warp7_defconfig
View file

@ -38,6 +38,7 @@ CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y

1
configs/warp_defconfig
View file

@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

1
configs/xilinx_zynqmp_mini_emmc0_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_SPL_DM=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set

1
configs/xilinx_zynqmp_mini_emmc1_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_SPL_DM=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set

1
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y

1
configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MTD_DEVICE=y

1
configs/xpress_defconfig
View file

@ -25,6 +25,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y

1
configs/xpress_spl_defconfig
View file

@ -36,6 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y

1
configs/zc5202_defconfig
View file

@ -34,6 +34,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3

1
configs/zc5601_defconfig
View file

@ -33,6 +33,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3

6
drivers/mmc/Kconfig
View file

@ -78,6 +78,12 @@ config SUPPORT_EMMC_RPMB
Enable support for reading, writing and programming the
key for the Replay Protection Memory Block partition in eMMC.
config SUPPORT_EMMC_BOOT
bool "Support some additional features of the eMMC boot partitions"
help
Enable support for eMMC boot partitions. This also enables
extensions within the mmc command.
config MMC_IO_VOLTAGE
bool "Support IO voltage configuration"
help

39
drivers/mtd/nand/raw/davinci_nand.c
View file

@ -730,43 +730,6 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd)
return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
}
static void nand_flash_init(void)
{
/* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
* Instead, have your board_init() set EMIF timings, based on its
* knowledge of the clocks and what devices are hooked up ... and
* don't even do that unless no UBL handled it.
*/
#ifdef CONFIG_SOC_DM644X
u_int32_t acfg1 = 0x3ffffffc;
/*------------------------------------------------------------------*
* NAND FLASH CHIP TIMEOUT @ 459 MHz *
* *
* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
* *
*------------------------------------------------------------------*/
acfg1 = 0
| (0 << 31) /* selectStrobe */
| (0 << 30) /* extWait */
| (1 << 26) /* writeSetup 10 ns */
| (3 << 20) /* writeStrobe 40 ns */
| (1 << 17) /* writeHold 10 ns */
| (1 << 13) /* readSetup 10 ns */
| (5 << 7) /* readStrobe 60 ns */
| (1 << 4) /* readHold 10 ns */
| (3 << 2) /* turnAround ?? ns */
| (0 << 0) /* asyncSize 8-bit bus */
;
__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
/* NAND flash on CS2 */
__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
#endif
}
void davinci_nand_init(struct nand_chip *nand)
{
#if defined CONFIG_KEYSTONE_RBL_NAND
@ -820,8 +783,6 @@ void davinci_nand_init(struct nand_chip *nand)
nand->write_buf = nand_davinci_write_buf;
nand->dev_ready = nand_davinci_dev_ready;
nand_flash_init();
}
int board_nand_init(struct nand_chip *chip) __attribute__((weak));

55
drivers/net/ti/davinci_emac.c
View file

@ -816,55 +816,12 @@ int davinci_emac_initialize(void)
phy_id |= tmp & 0x0000ffff;
switch (phy_id) {
#ifdef PHY_KSZ8873
case PHY_KSZ8873:
sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = ksz8873_init_phy;
phy[i].is_phy_connected = ksz8873_is_phy_connected;
phy[i].get_link_speed = ksz8873_get_link_speed;
phy[i].auto_negotiate = ksz8873_auto_negotiate;
break;
#endif
#ifdef PHY_LXT972
case PHY_LXT972:
sprintf(phy[i].name, "LXT972 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = lxt972_init_phy;
phy[i].is_phy_connected = lxt972_is_phy_connected;
phy[i].get_link_speed = lxt972_get_link_speed;
phy[i].auto_negotiate = lxt972_auto_negotiate;
break;
#endif
#ifdef PHY_DP83848
case PHY_DP83848:
sprintf(phy[i].name, "DP83848 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = dp83848_init_phy;
phy[i].is_phy_connected = dp83848_is_phy_connected;
phy[i].get_link_speed = dp83848_get_link_speed;
phy[i].auto_negotiate = dp83848_auto_negotiate;
break;
#endif
#ifdef PHY_ET1011C
case PHY_ET1011C:
sprintf(phy[i].name, "ET1011C @ 0x%02x",
active_phy_addr[i]);
phy[i].init = gen_init_phy;
phy[i].is_phy_connected = gen_is_phy_connected;
phy[i].get_link_speed = et1011c_get_link_speed;
phy[i].auto_negotiate = gen_auto_negotiate;
break;
#endif
default:
sprintf(phy[i].name, "GENERIC @ 0x%02x",
active_phy_addr[i]);
phy[i].init = gen_init_phy;
phy[i].is_phy_connected = gen_is_phy_connected;
phy[i].get_link_speed = gen_get_link_speed;
phy[i].auto_negotiate = gen_auto_negotiate;
}
sprintf(phy[i].name, "GENERIC @ 0x%02x",
active_phy_addr[i]);
phy[i].init = gen_init_phy;
phy[i].is_phy_connected = gen_is_phy_connected;
phy[i].get_link_speed = gen_get_link_speed;
phy[i].auto_negotiate = gen_auto_negotiate;
debug("Ethernet PHY: %s\n", phy[i].name);

6
drivers/usb/musb/musb_hcd.c
View file

@ -327,9 +327,7 @@ static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
csr = readw(&musbr->txcsr);
csr |= MUSB_CSR0_TXPKTRDY;
#if !defined(CONFIG_SOC_DM365)
csr |= MUSB_CSR0_H_DIS_PING;
#endif
writew(csr, &musbr->txcsr);
result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
if (result < 0)
@ -352,9 +350,7 @@ static int ctrlreq_out_status_phase(struct usb_device *dev)
/* Set the StatusPkt bit */
csr = readw(&musbr->txcsr);
csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
#if !defined(CONFIG_SOC_DM365)
csr |= MUSB_CSR0_H_DIS_PING;
#endif
writew(csr, &musbr->txcsr);
/* Wait until TXPKTRDY bit is cleared */
@ -372,9 +368,7 @@ static int ctrlreq_in_status_phase(struct usb_device *dev)
/* Set the StatusPkt bit and ReqPkt bit */
csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
#if !defined(CONFIG_SOC_DM365)
csr |= MUSB_CSR0_H_DIS_PING;
#endif
writew(csr, &musbr->txcsr);
result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);

2
include/configs/advantech_dms-ba16.h
View file

@ -21,8 +21,6 @@
#define CONFIG_LOADCMD "fatload"
#define CONFIG_RFSPART "2"
#define CONFIG_SUPPORT_EMMC_BOOT
#include "mx6_common.h"
#include <linux/sizes.h>

2
include/configs/am57xx_evm.h
View file

@ -63,8 +63,6 @@
#define CONFIG_NET_RETRY_COUNT 10
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define CONFIG_SUPPORT_EMMC_BOOT
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP

3
include/configs/apalis-tk1.h
View file

@ -18,9 +18,6 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SD/MMC support */
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)

2
include/configs/apalis_imx6.h
View file

@ -46,8 +46,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/*
* SATA Configs
*/

3
include/configs/arndale.h
View file

@ -14,9 +14,6 @@
#include "exynos5250-common.h"
#include <configs/exynos5-common.h>
/* SD/MMC configuration */
#define CONFIG_SUPPORT_EMMC_BOOT
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

Some files were not shown because too many files have changed in this diff Show more