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https://github.com/AsahiLinux/u-boot
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driver:i2c:s3c24x0: adapt driver to new i2c
This patch adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Heiko Schocher <hs@denx.de> CC: Inderpal Singh <inderpal.singh@linaro.org> CC: David Müller <d.mueller@elsoft.ch> CC: Chander Kashyap <k.chander@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
This commit is contained in:
Piotr Wilczek
Heiko Schocher
parent
f44483b57c
commit
2d8f1e2769
10 changed files with 169 additions and 120 deletions
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@ -150,8 +150,6 @@ int power_init_board(void)
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set_ps_hold_ctrl();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (pmic_init(I2C_PMIC))
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return -1;
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@ -57,15 +57,18 @@ int board_init(void)
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void i2c_init_board(void)
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{
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struct exynos4_gpio_part1 *gpio1 =
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(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
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int err;
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struct exynos4_gpio_part2 *gpio2 =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
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/* I2C_5 -> PMIC -> Adapter 0 */
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s5p_gpio_direction_output(&gpio1->b, 7, 1);
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s5p_gpio_direction_output(&gpio1->b, 6, 1);
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/* I2C_9 -> FG -> Adapter 1 */
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/* I2C_5 -> PMIC */
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err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
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if (err) {
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debug("I2C%d not configured\n", (I2C_5));
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return;
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}
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/* I2C_8 -> FG */
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s5p_gpio_direction_output(&gpio2->y4, 0, 1);
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s5p_gpio_direction_output(&gpio2->y4, 1, 1);
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}
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@ -290,10 +293,10 @@ int power_init_board(void)
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* The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
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* to logical I2C adapter 1
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*/
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ret = pmic_init(I2C_0);
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ret = pmic_init(I2C_5);
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ret |= pmic_init_max8997();
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ret |= power_fg_init(I2C_1);
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ret |= power_muic_init(I2C_0);
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ret |= power_fg_init(I2C_8);
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ret |= power_muic_init(I2C_5);
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ret |= power_bat_init(0);
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if (ret)
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return ret;
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@ -115,12 +115,17 @@ static void board_external_gpio_init(void)
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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static void board_init_i2c(void)
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{
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int err;
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gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
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gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
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/* I2C_7 */
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s5p_gpio_direction_output(&gpio1->d0, 2, 1);
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s5p_gpio_direction_output(&gpio1->d0, 3, 1);
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err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
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if (err) {
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debug("I2C%d not configured\n", (I2C_7));
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return;
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}
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/* I2C_8 */
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s5p_gpio_direction_output(&gpio1->f1, 4, 1);
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@ -132,6 +137,24 @@ static void board_init_i2c(void)
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}
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#endif
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#ifdef CONFIG_SYS_I2C_SOFT
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int get_soft_i2c_scl_pin(void)
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{
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if (I2C_ADAP_HWNR)
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return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
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else
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return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
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}
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int get_soft_i2c_sda_pin(void)
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{
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if (I2C_ADAP_HWNR)
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return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
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else
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return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
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}
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#endif
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int board_early_init_f(void)
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{
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check_hw_revision();
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@ -167,11 +190,11 @@ int power_init_board(void)
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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board_init_i2c();
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#endif
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pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */
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pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */
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pmic_init_max77686();
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pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
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power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
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power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */
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pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */
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power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */
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power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */
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power_bat_init(0);
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p_chrg = pmic_get("MAX77693_PMIC");
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@ -12,7 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
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obj-$(CONFIG_I2C_MV) += mv_i2c.o
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obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
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obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
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obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
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obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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@ -24,6 +23,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
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obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
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obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
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obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
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obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
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obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
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obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
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@ -23,8 +23,6 @@
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#include <i2c.h>
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#include "s3c24x0_i2c.h"
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#ifdef CONFIG_HARD_I2C
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#define I2C_WRITE 0
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#define I2C_READ 1
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@ -127,7 +125,6 @@
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* For SPL boot some boards need i2c before SDRAM is initialised so force
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* variables to live in SRAM
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*/
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static unsigned int g_current_bus __attribute__((section(".data")));
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static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
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__attribute__((section(".data")));
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@ -254,17 +251,17 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
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writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
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}
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static struct s3c24x0_i2c *get_base_i2c(void)
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static struct s3c24x0_i2c *get_base_i2c(int bus)
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{
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#ifdef CONFIG_EXYNOS4
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struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
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+ (EXYNOS4_I2C_SPACING
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* g_current_bus));
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* bus));
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return i2c;
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#elif defined CONFIG_EXYNOS5
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struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
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+ (EXYNOS5_I2C_SPACING
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* g_current_bus));
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* bus));
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return i2c;
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#else
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return s3c24x0_get_base_i2c();
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@ -298,7 +295,6 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
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writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
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}
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#ifdef CONFIG_I2C_MULTI_BUS
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static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
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{
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struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
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@ -330,7 +326,6 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
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}
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return -1;
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}
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#endif
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static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
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{
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@ -401,49 +396,18 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
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hsi2c_ch_init(i2c_bus);
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}
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/*
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* MULTI BUS I2C support
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*/
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#ifdef CONFIG_I2C_MULTI_BUS
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int i2c_set_bus_num(unsigned int bus)
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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i2c_bus = get_bus(bus);
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if (!i2c_bus)
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return -1;
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g_current_bus = bus;
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if (i2c_bus->is_highspeed) {
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if (hsi2c_get_clk_details(i2c_bus))
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return -1;
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hsi2c_ch_init(i2c_bus);
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} else {
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i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
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CONFIG_SYS_I2C_SLAVE);
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}
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return 0;
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}
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unsigned int i2c_get_bus_num(void)
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{
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return g_current_bus;
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}
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#endif
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void i2c_init(int speed, int slaveadd)
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static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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struct s3c24x0_i2c *i2c;
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struct s3c24x0_i2c_bus *bus;
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#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#endif
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ulong start_time = get_timer(0);
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/* By default i2c channel 0 is the current bus */
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g_current_bus = 0;
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i2c = get_base_i2c();
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i2c = get_base_i2c(adap->hwadapnr);
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/*
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* In case the previous transfer is still going, wait to give it a
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@ -505,6 +469,10 @@ void i2c_init(int speed, int slaveadd)
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}
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#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
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i2c_ch_init(i2c, speed, slaveadd);
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bus = &i2c_bus[adap->hwadapnr];
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bus->active = true;
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bus->regs = i2c;
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}
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/*
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@ -728,6 +696,29 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
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return rv;
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}
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static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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i2c_bus->clock_frequency = speed;
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if (i2c_bus->is_highspeed) {
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if (hsi2c_get_clk_details(i2c_bus))
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return -1;
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hsi2c_ch_init(i2c_bus);
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} else {
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i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
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CONFIG_SYS_I2C_S3C24X0_SLAVE);
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}
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return 0;
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}
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/*
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* cmd_type is 0 for write, 1 for read.
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*
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@ -840,13 +831,13 @@ bailout:
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return result;
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}
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int i2c_probe(uchar chip)
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static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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uchar buf[1];
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int ret;
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i2c_bus = get_bus(g_current_bus);
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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buf[0] = 0;
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@ -864,11 +855,11 @@ int i2c_probe(uchar chip)
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I2C_READ, chip << 1, 0, 0, buf, 1);
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}
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return ret != I2C_OK;
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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uchar xaddr[4];
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@ -902,7 +893,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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chip |= ((addr >> (alen * 8)) &
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CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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i2c_bus = get_bus(g_current_bus);
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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@ -922,7 +913,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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return 0;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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uchar xaddr[4];
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@ -955,7 +947,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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chip |= ((addr >> (alen * 8)) &
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CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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i2c_bus = get_bus(g_current_bus);
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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@ -1001,8 +993,8 @@ static void process_nodes(const void *blob, int node_list[], int count,
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bus->id = pinmux_decode_periph_id(blob, node);
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bus->clock_frequency = fdtdec_get_int(blob, node,
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"clock-frequency",
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CONFIG_SYS_I2C_SPEED);
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"clock-frequency",
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CONFIG_SYS_I2C_S3C24X0_SPEED);
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bus->node = node;
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bus->bus_num = i;
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exynos_pinmux_config(bus->id, 0);
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@ -1044,7 +1036,6 @@ int i2c_get_bus_num_fdt(int node)
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return -1;
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}
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#ifdef CONFIG_I2C_MULTI_BUS
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int i2c_reset_port_fdt(const void *blob, int node)
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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@ -1068,12 +1059,61 @@ int i2c_reset_port_fdt(const void *blob, int node)
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hsi2c_ch_init(i2c_bus);
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} else {
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i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
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CONFIG_SYS_I2C_SLAVE);
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CONFIG_SYS_I2C_S3C24X0_SLAVE);
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}
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return 0;
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}
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#endif
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#endif
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#endif /* CONFIG_HARD_I2C */
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/*
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* Register s3c24x0 i2c adapters
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*/
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U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
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s3c24x0_i2c_read, s3c24x0_i2c_write,
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s3c24x0_i2c_set_bus_speed,
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CONFIG_SYS_I2C_S3C24X0_SPEED,
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CONFIG_SYS_I2C_S3C24X0_SLAVE,
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0)
|
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U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE,
|
||||
1)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE,
|
||||
2)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE,
|
||||
3)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE,
|
||||
4)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE,
|
||||
5)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE,
|
||||
6)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE,
|
||||
7)
|
||||
|
|
|
|||
|
|
@ -73,12 +73,12 @@
|
|||
* the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
|
||||
* address 0x50 with 16bit addressing
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
/* we use the built-in I2C controller */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
|
|
|||
|
|
@ -214,13 +214,12 @@
|
|||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
|
||||
#define CONFIG_I2C_EDID
|
||||
|
||||
/* PMIC */
|
||||
|
|
|
|||
|
|
@ -249,13 +249,13 @@
|
|||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
|
||||
#define CONFIG_I2C_EDID
|
||||
|
||||
/* PMIC */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
*/
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* which is in a S5P Family */
|
||||
#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
|
||||
#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
|
||||
#define CONFIG_TRATS /* working with TRATS */
|
||||
#define CONFIG_TIZEN /* TIZEN lib */
|
||||
|
|
@ -268,31 +269,21 @@
|
|||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
|
||||
#define I2C_SOFT_DECLARATIONS2
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SOFT_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS 15
|
||||
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
/* I2C PMIC */
|
||||
#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
|
||||
#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
|
||||
|
||||
/* I2C FG */
|
||||
#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
|
||||
#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
|
||||
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
|
||||
#define I2C_INIT multi_i2c_init()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
|
||||
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
|
|
|
|||
|
|
@ -260,30 +260,25 @@
|
|||
#include <asm/arch/gpio.h>
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SOFT
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
|
||||
#define I2C_SOFT_DECLARATIONS2
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
|
||||
#define I2C_SOFT_DECLARATIONS3
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x00
|
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SOFT_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS 15
|
||||
|
||||
#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
|
||||
#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
|
||||
#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
|
||||
#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
|
||||
#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
|
||||
#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
|
||||
#define I2C_INIT multi_i2c_init()
|
||||
#ifndef __ASSEMBLY__
|
||||
int get_soft_i2c_scl_pin(void);
|
||||
int get_soft_i2c_sda_pin(void);
|
||||
#endif
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin()
|
||||
|
||||
/* POWER */
|
||||
#define CONFIG_POWER
|
||||
|
|
|
|||
Loading…
Reference in a new issue