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ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friends

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This patch changes all in32/out32 calls to use the recommended in_be32/
out_be32 macros instead.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-10-23 14:03:17 +02:00
parent 7d47cee2cc
commit 2d83476a4c
2 changed files with 74 additions and 73 deletions
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118
cpu/ppc4xx/4xx_enet.c
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@ -81,6 +81,7 @@
#include <common.h> #include <common.h>
#include <net.h> #include <net.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <commproc.h> #include <commproc.h>
#include <ppc4xx.h> #include <ppc4xx.h>
#include <ppc4xx_enet.h> #include <ppc4xx_enet.h>
@ -221,7 +222,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
unsigned long mfr; unsigned long mfr;
#endif #endif
out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* 1st reset MAL channel */ /* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */ /* Note: writing a 0 to a channel has no effect */
@ -250,7 +251,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
mtsdr(sdr_mfr, mfr); mtsdr(sdr_mfr, mfr);
#endif #endif
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
#if defined(CONFIG_440SPE) || \ #if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@ -353,8 +354,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
/* Ensure we setup mdio for this devnum and ONLY this devnum */ /* Ensure we setup mdio for this devnum and ONLY this devnum */
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
out32 (ZMII_FER, zmiifer); out_be32(ZMII_FER, zmiifer);
out32 (RGMII_FER, rmiifer); out_be32(RGMII_FER, rmiifer);
return ((int)pfc1); return ((int)pfc1);
} }
@ -372,31 +373,31 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
switch (pfc1) { switch (pfc1) {
case SDR0_PFC1_SELECT_CONFIG_2: case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */ /* 1 x GMII port */
out32 (ZMII_FER, 0x00); out_be32((void *)ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000037); out_be32((void *)RGMII_FER, 0x00000037);
bis->bi_phymode[0] = BI_PHYMODE_GMII; bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE; bis->bi_phymode[1] = BI_PHYMODE_NONE;
break; break;
case SDR0_PFC1_SELECT_CONFIG_4: case SDR0_PFC1_SELECT_CONFIG_4:
/* 2 x RGMII ports */ /* 2 x RGMII ports */
out32 (ZMII_FER, 0x00); out_be32((void *)ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000055); out_be32((void *)RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break; break;
case SDR0_PFC1_SELECT_CONFIG_6: case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */ /* 2 x SMII ports */
out32 (ZMII_FER, out_be32((void *)ZMII_FER,
((ZMII_FER_SMII) << ZMII_FER_V(0)) | ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
((ZMII_FER_SMII) << ZMII_FER_V(1))); ((ZMII_FER_SMII) << ZMII_FER_V(1)));
out32 (RGMII_FER, 0x00000000); out_be32((void *)RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_SMII; bis->bi_phymode[0] = BI_PHYMODE_SMII;
bis->bi_phymode[1] = BI_PHYMODE_SMII; bis->bi_phymode[1] = BI_PHYMODE_SMII;
break; break;
case SDR0_PFC1_SELECT_CONFIG_1_2: case SDR0_PFC1_SELECT_CONFIG_1_2:
/* only 1 x MII supported */ /* only 1 x MII supported */
out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
out32 (RGMII_FER, 0x00000000); out_be32((void *)RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_MII; bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE; bis->bi_phymode[1] = BI_PHYMODE_NONE;
break; break;
@ -405,9 +406,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
} }
/* Ensure we setup mdio for this devnum and ONLY this devnum */ /* Ensure we setup mdio for this devnum and ONLY this devnum */
zmiifer = in32 (ZMII_FER); zmiifer = in_be32((void *)ZMII_FER);
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
out32 (ZMII_FER, zmiifer); out_be32((void *)ZMII_FER, zmiifer);
return ((int)0x0); return ((int)0x0);
} }
@ -425,7 +426,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
switch (1) { switch (1) {
case 1: case 1:
/* 2 x RGMII ports */ /* 2 x RGMII ports */
out32 (RGMII_FER, 0x00000055); out_be32((void *)RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break; break;
@ -437,9 +438,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
} }
/* Ensure we setup mdio for this devnum and ONLY this devnum */ /* Ensure we setup mdio for this devnum and ONLY this devnum */
gmiifer = in32(RGMII_FER); gmiifer = in_be32((void *)RGMII_FER);
gmiifer |= (1 << (19-devnum)); gmiifer |= (1 << (19-devnum));
out32 (RGMII_FER, gmiifer); out_be32((void *)RGMII_FER, gmiifer);
return ((int)0x0); return ((int)0x0);
} }
@ -535,27 +536,27 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* NOTE: Therefore, disable all other EMACS, since we handle */ /* NOTE: Therefore, disable all other EMACS, since we handle */
/* NOTE: only one emac at a time */ /* NOTE: only one emac at a time */
reg = 0; reg = 0;
out32 (ZMII_FER, 0); out_be32((void *)ZMII_FER, 0);
udelay (100); udelay (100);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
#elif defined(CONFIG_440GP) #elif defined(CONFIG_440GP)
/* set RMII mode */ /* set RMII mode */
out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0);
#else #else
if ((devnum == 0) || (devnum == 1)) { if ((devnum == 0) || (devnum == 1)) {
out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
} else { /* ((devnum == 2) || (devnum == 3)) */ } else { /* ((devnum == 2) || (devnum == 3)) */
out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
(RGMII_FER_RGMII << RGMII_FER_V (3)))); (RGMII_FER_RGMII << RGMII_FER_V (3))));
} }
#endif #endif
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_405EX) #if defined(CONFIG_405EX)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
@ -573,11 +574,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
mtsdr(sdr_mfr, mfr); mtsdr(sdr_mfr, mfr);
#endif #endif
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
__asm__ volatile ("eieio");
failsafe = 1000; failsafe = 1000;
while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
udelay (1000); udelay (1000);
failsafe--; failsafe--;
} }
@ -610,7 +610,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
else else
mode_reg |= EMAC_M1_OBCI_GT100; mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
/* wait for PHY to complete auto negotiation */ /* wait for PHY to complete auto negotiation */
@ -768,11 +768,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#endif #endif
/* Set ZMII/RGMII speed according to the phy link speed */ /* Set ZMII/RGMII speed according to the phy link speed */
reg = in32 (ZMII_SSR); reg = in_be32(ZMII_SSR);
if ( (speed == 100) || (speed == 1000) ) if ( (speed == 100) || (speed == 1000) )
out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); out_be32(ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
else else
out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); out_be32(ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
if ((devnum == 2) || (devnum == 3)) { if ((devnum == 2) || (devnum == 3)) {
if (speed == 1000) if (speed == 1000)
@ -785,7 +785,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
printf("Error in RGMII Speed\n"); printf("Error in RGMII Speed\n");
return -1; return -1;
} }
out32 (RGMII_SSR, reg); out_be32(RGMII_SSR, reg);
} }
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
@ -801,7 +801,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
printf("Error in RGMII Speed\n"); printf("Error in RGMII Speed\n");
return -1; return -1;
} }
out32 (RGMII_SSR, reg); out_be32((void *)RGMII_SSR, reg);
#endif #endif
/* set the Mal configuration reg */ /* set the Mal configuration reg */
@ -912,7 +912,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
reg = reg << 8; reg = reg << 8;
reg |= dev->enetaddr[1]; reg |= dev->enetaddr[1];
out32 (EMAC_IAH + hw_p->hw_addr, reg); out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
reg = 0x00000000; reg = 0x00000000;
reg |= dev->enetaddr[2]; /* set low address */ reg |= dev->enetaddr[2]; /* set low address */
@ -923,7 +923,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
reg = reg << 8; reg = reg << 8;
reg |= dev->enetaddr[5]; reg |= dev->enetaddr[5];
out32 (EMAC_IAL + hw_p->hw_addr, reg); out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
switch (devnum) { switch (devnum) {
case 1: case 1:
@ -984,10 +984,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
/* set transmit enable & receive enable */ /* set transmit enable & receive enable */
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
/* set receive fifo to 4k and tx fifo to 2k */ /* set receive fifo to 4k and tx fifo to 2k */
mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
/* set speed */ /* set speed */
@ -1008,39 +1008,39 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (duplex == FULL) if (duplex == FULL)
mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
/* Enable broadcast and indvidual address */ /* Enable broadcast and indvidual address */
/* TBS: enabling runts as some misbehaved nics will send runts */ /* TBS: enabling runts as some misbehaved nics will send runts */
out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
/* we probably need to set the tx mode1 reg? maybe at tx time */ /* we probably need to set the tx mode1 reg? maybe at tx time */
/* set transmit request threshold register */ /* set transmit request threshold register */
out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */ /* set receive low/high water mark register */
#if defined(CONFIG_440) #if defined(CONFIG_440)
/* 440s has a 64 byte burst length */ /* 440s has a 64 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
#else #else
/* 405s have a 16 byte burst length */ /* 405s have a 16 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif /* defined(CONFIG_440) */ #endif /* defined(CONFIG_440) */
out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
/* Set fifo limit entry in tx mode 0 */ /* Set fifo limit entry in tx mode 0 */
out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
/* Frame gap set */ /* Frame gap set */
out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/* Set EMAC IER */ /* Set EMAC IER */
hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET) if (speed == _100BASET)
hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
if (hw_p->first_init == 0) { if (hw_p->first_init == 0) {
/* /*
@ -1098,8 +1098,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
__asm__ volatile ("eieio"); __asm__ volatile ("eieio");
out32 (EMAC_TXM0 + hw_p->hw_addr, out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
#ifdef INFO_4XX_ENET #ifdef INFO_4XX_ENET
hw_p->stats.pkts_tx++; hw_p->stats.pkts_tx++;
#endif #endif
@ -1109,7 +1109,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
*-----------------------------------------------------------------------*/ *-----------------------------------------------------------------------*/
time_start = get_timer (0); time_start = get_timer (0);
while (1) { while (1) {
temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
/* loop until either TINT turns on or 3 seconds elapse */ /* loop until either TINT turns on or 3 seconds elapse */
if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
/* transmit is done, so now check for errors /* transmit is done, so now check for errors
@ -1218,7 +1218,7 @@ int enetInt (struct eth_device *dev)
/* port by port dispatch of emac interrupts */ /* port by port dispatch of emac interrupts */
if (hw_p->devnum == 0) { if (hw_p->devnum == 0) {
if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) { if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr); emac_err (dev, emac_isr);
serviced = 1; serviced = 1;
@ -1237,7 +1237,7 @@ int enetInt (struct eth_device *dev)
#if !defined(CONFIG_440SP) #if !defined(CONFIG_440SP)
if (hw_p->devnum == 1) { if (hw_p->devnum == 1) {
if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) { if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr); emac_err (dev, emac_isr);
serviced = 1; serviced = 1;
@ -1255,7 +1255,7 @@ int enetInt (struct eth_device *dev)
#if defined (CONFIG_440GX) #if defined (CONFIG_440GX)
if (hw_p->devnum == 2) { if (hw_p->devnum == 2) {
if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) { if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr); emac_err (dev, emac_isr);
serviced = 1; serviced = 1;
@ -1273,7 +1273,7 @@ int enetInt (struct eth_device *dev)
if (hw_p->devnum == 3) { if (hw_p->devnum == 3) {
if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) { if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr); emac_err (dev, emac_isr);
serviced = 1; serviced = 1;
@ -1385,7 +1385,7 @@ int enetInt (struct eth_device *dev)
/* port by port dispatch of emac interrupts */ /* port by port dispatch of emac interrupts */
if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) { if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr); emac_err (dev, emac_isr);
serviced = 1; serviced = 1;
@ -1459,7 +1459,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr)
EMAC_4XX_HW_PST hw_p = dev->priv; EMAC_4XX_HW_PST hw_p = dev->priv;
printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
out32 (EMAC_ISR + hw_p->hw_addr, isr); out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
} }
/*-----------------------------------------------------------------------------+ /*-----------------------------------------------------------------------------+

29
cpu/ppc4xx/miiphy.c
View file

@ -44,6 +44,7 @@
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <ppc_asm.tmpl> #include <ppc_asm.tmpl>
#include <commproc.h> #include <commproc.h>
#include <ppc4xx_enet.h> #include <ppc4xx_enet.h>
@ -113,7 +114,7 @@ unsigned int miiphy_getemac_offset (void)
unsigned long eoffset; unsigned long eoffset;
/* Need to find out which mdi port we're using */ /* Need to find out which mdi port we're using */
zmii = in32 (ZMII_FER); zmii = in_be32((void *)ZMII_FER);
if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
/* using port 0 */ /* using port 0 */
@ -131,12 +132,12 @@ unsigned int miiphy_getemac_offset (void)
/* None of the mdi ports are enabled! */ /* None of the mdi ports are enabled! */
/* enable port 0 */ /* enable port 0 */
zmii |= ZMII_FER_MDI << ZMII_FER_V (0); zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
out32 (ZMII_FER, zmii); out_be32((void *)ZMII_FER, zmii);
eoffset = 0; eoffset = 0;
/* need to soft reset port 0 */ /* need to soft reset port 0 */
zmii = in32 (EMAC_M0); zmii = in_be32((void *)EMAC_M0);
zmii |= EMAC_M0_SRST; zmii |= EMAC_M0_SRST;
out32 (EMAC_M0, zmii); out_be32((void *)EMAC_M0, zmii);
} }
return (eoffset); return (eoffset);
@ -146,7 +147,7 @@ unsigned int miiphy_getemac_offset (void)
unsigned long rgmii; unsigned long rgmii;
int devnum = 1; int devnum = 1;
rgmii = in32(RGMII_FER); rgmii = in_be32((void *)RGMII_FER);
if (rgmii & (1 << (19 - devnum))) if (rgmii & (1 << (19 - devnum)))
return 0x100; return 0x100;
#endif #endif
@ -169,11 +170,11 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
i = 0; i = 0;
/* see if it is ready for sec */ /* see if it is ready for sec */
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
udelay (7); udelay (7);
if (i > 5) { if (i > 5) {
#ifdef ET_DEBUG #ifdef ET_DEBUG
sta_reg = in32 (EMAC_STACR + emac_reg); sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
printf ("read err 1\n"); printf ("read err 1\n");
#endif #endif
@ -203,12 +204,12 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
#endif #endif
sta_reg = sta_reg | (addr << 5); /* Phy address */ sta_reg = sta_reg | (addr << 5); /* Phy address */
sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
out32 (EMAC_STACR + emac_reg, sta_reg); out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
#ifdef ET_DEBUG #ifdef ET_DEBUG
printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif #endif
sta_reg = in32 (EMAC_STACR + emac_reg); sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG #ifdef ET_DEBUG
printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif #endif
@ -219,7 +220,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
return -1; return -1;
} }
i++; i++;
sta_reg = in32 (EMAC_STACR + emac_reg); sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG #ifdef ET_DEBUG
printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif #endif
@ -250,7 +251,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
/* see if it is ready for 1000 nsec */ /* see if it is ready for 1000 nsec */
i = 0; i = 0;
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
if (i > 5) if (i > 5)
return -1; return -1;
udelay (7); udelay (7);
@ -281,11 +282,11 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
memcpy (&sta_reg, &value, 2); /* put in data */ memcpy (&sta_reg, &value, 2); /* put in data */
out32 (EMAC_STACR + emac_reg, sta_reg); out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
/* wait for completion */ /* wait for completion */
i = 0; i = 0;
sta_reg = in32 (EMAC_STACR + emac_reg); sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG #ifdef ET_DEBUG
printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif #endif
@ -294,7 +295,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
if (i > 5) if (i > 5)
return -1; return -1;
i++; i++;
sta_reg = in32 (EMAC_STACR + emac_reg); sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG #ifdef ET_DEBUG
printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif #endif