mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-16 14:56:59 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-sh
This commit is contained in:
commit
2caea1ebee
24 changed files with 86 additions and 121 deletions
2
MAKEALL
2
MAKEALL
|
@ -749,7 +749,7 @@ LIST_sh3=" \
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|||
LIST_sh4=" \
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||||
ms7750se \
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ms7722se \
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Migo-R \
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MigoR \
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r7780mp \
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r2dplus \
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sh7763rdp \
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||||
|
|
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@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
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|||
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LIB = $(obj)lib$(BOARD).a
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OBJS := migo_r.o
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COBJS := migo_r.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
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@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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OBJS := mpr2.o
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COBJS := mpr2.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
|
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@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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OBJS := ms7720se.o
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COBJS := ms7720se.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
|
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@ -40,7 +40,6 @@ int checkboard(void)
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|||
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int board_init(void)
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{
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return 0;
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}
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|
|
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@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
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|||
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LIB = $(obj)lib$(BOARD).a
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OBJS := ms7722se.o
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COBJS := ms7722se.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
|
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007
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* Copyright (C) 2007,2008
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* Copyright (C) 2007
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|
@ -43,7 +43,7 @@ int board_init(void)
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return 0;
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}
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int dram_init (void)
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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|
@ -53,7 +53,7 @@ int dram_init (void)
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return 0;
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}
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void led_set_state (unsigned short value)
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void led_set_state(unsigned short value)
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{
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*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
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writew(value & 0xFF, LED_BASE);
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}
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|
|
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@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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OBJS := ms7750se.o
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COBJS := ms7750se.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
|
|
@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
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|||
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LIB = $(obj)lib$(BOARD).a
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OBJS := r2dplus.o
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COBJS := r2dplus.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
|
|
@ -24,6 +24,7 @@
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#include <common.h>
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#include <ide.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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int checkboard(void)
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|
@ -37,7 +38,7 @@ int board_init(void)
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return 0;
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}
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int dram_init (void)
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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||||
|
@ -52,25 +53,26 @@ int board_late_init(void)
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return 0;
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}
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#define FPGA_BASE 0xA4000000
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#define FPGA_CFCTL (FPGA_BASE + 0x04)
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#define FPGA_CFPOW (FPGA_BASE + 0x06)
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#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
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#define FPGA_BASE 0xA4000000
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#define FPGA_CFCTL (FPGA_BASE + 0x04)
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#define CFCTL_EN (0x432)
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#define FPGA_CFPOW (FPGA_BASE + 0x06)
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#define CFPOW_ON (0x02)
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#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
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#define CFCDINTCLR_EN (0x01)
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void ide_set_reset (int idereset)
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void ide_set_reset(int idereset)
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{
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/* if reset = 1 IDE reset will be asserted */
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if (idereset){
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(*(vu_short *)FPGA_CFCTL) = 0x432;
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(*(vu_short *)FPGA_CFPOW) |= 0x02;
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(*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
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if (idereset) {
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outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
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outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
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outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
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}
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}
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#if defined(CONFIG_PCI)
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static struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_sh7751_init( &hose );
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pci_sh7751_init(&hose);
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}
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#endif /* CONFIG_PCI */
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|
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@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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OBJS := r7780mp.o
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COBJS := r7780mp.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
|
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@ -38,12 +38,12 @@ int checkboard(void)
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int board_init(void)
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{
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/* SCIF Enable */
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*(vu_short*)PHCR = 0x0000;
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writew(0x0, PHCR);
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return 0;
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}
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int dram_init (void)
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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|
@ -53,29 +53,27 @@ int dram_init (void)
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return 0;
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}
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void led_set_state (unsigned short value)
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void led_set_state(unsigned short value)
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{
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}
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void ide_set_reset (int idereset)
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void ide_set_reset(int idereset)
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{
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/* if reset = 1 IDE reset will be asserted */
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if (idereset){
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(*(vu_short *)FPGA_CFCTL) = 0x432;
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if (idereset) {
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writew(0x432, FPGA_CFCTL);
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#if defined(CONFIG_R7780MP)
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(*(vu_short *)FPGA_CFPOW) |= 0x01;
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writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
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#else
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(*(vu_short *)FPGA_CFPOW) |= 0x02;
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writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
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#endif
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(*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
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writew(0x01, FPGA_CFCDINTCLR);
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}
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}
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#if defined(CONFIG_PCI)
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static struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_sh7780_init( &hose );
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pci_sh7780_init(&hose);
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}
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#endif
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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|||
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LIB = $(obj)lib$(BOARD).a
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OBJS := sh7763rdp.o
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COBJS := sh7763rdp.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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|
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@ -49,19 +49,20 @@ int board_init(void)
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{
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vu_short dat;
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*(vu_short *)(CPU_CMDREG) |= 0x0001;
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/* Enable mode */
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writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
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/* GPIO Setting (eth1) */
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dat = *(vu_short *)(PSEL1);
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*(vu_short *)PSEL1 = ((dat & ~0xff00) | 0x2400);
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*(vu_short *)PFCR = 0;
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*(vu_short *)PGCR = 0;
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*(vu_short *)PHCR = 0;
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dat = inw(PSEL1);
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writew(((dat & ~0xff00) | 0x2400), PSEL1);
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writew(0, PFCR);
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writew(0, PGCR);
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writew(0, PHCR);
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return 0;
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}
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int dram_init (void)
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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|
@ -71,6 +72,6 @@ int dram_init (void)
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return 0;
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}
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void led_set_state (unsigned short value)
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void led_set_state(unsigned short value)
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{
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}
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|
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@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).a
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SOBJS = start.o
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OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
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COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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|
|
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@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
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|||
LIB = $(obj)lib$(CPU).a
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SOBJS = start.o
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||||
OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
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COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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|
|
|
@ -45,10 +45,6 @@
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.10.100
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#define CONFIG_SERVERIP 192.168.10.77
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#define CONFIG_GATEWAYIP 192.168.10.77
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||||
#define CONFIG_VERSION_VARIABLE
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||||
#undef CONFIG_SHOW_BOOT_PROGRESS
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||||
|
|
|
@ -40,10 +40,6 @@
|
|||
#define CONFIG_BAUDRATE 115200
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||||
#define CONFIG_BOOTDELAY 3
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||||
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
|
||||
#define CONFIG_NETMASK 255.255.255.0
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||||
#define CONFIG_IPADDR 192.168.0.22
|
||||
#define CONFIG_SERVERIP 192.168.0.1
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||||
#define CONFIG_GATEWAYIP 192.168.0.1
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
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||||
#undef CONFIG_SHOW_BOOT_PROGRESS
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||||
|
|
|
@ -35,12 +35,6 @@
|
|||
#define CONFIG_BOOTARGS "console=ttySC0,115200"
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
/* Network setting */
|
||||
#define CONFIG_NETMASK 255.0.0.0
|
||||
#define CONFIG_IPADDR 10.0.192.51
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
#define CONFIG_GATEWAYIP 10.0.0.1
|
||||
|
||||
/* SDRAM */
|
||||
#define CFG_SDRAM_BASE (0x8C000000)
|
||||
#define CFG_SDRAM_SIZE (0x04000000)
|
||||
|
@ -60,45 +54,27 @@
|
|||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
|
||||
/* Address of u-boot image in Flash */
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
|
||||
#define CFG_MONITOR_LEN (128 * 1024)
|
||||
#define CFG_MONITOR_LEN (256 * 1024)
|
||||
/* Size of DRAM reserved for malloc() use */
|
||||
#define CFG_MALLOC_LEN (256 * 1024)
|
||||
#define CFG_MALLOC_LEN (1024 * 1024)
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_SIZE (256)
|
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/*
|
||||
* NOR Flash
|
||||
* NOR Flash ( Spantion S29GL256P )
|
||||
*/
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
|
||||
#if defined(CONFIG_R2DPLUS_OLD)
|
||||
#define CFG_FLASH_BASE (0xA0000000)
|
||||
#define CFG_MAX_FLASH_BANKS (1) /* Max number of
|
||||
* Flash memory banks
|
||||
*/
|
||||
#define CFG_MAX_FLASH_SECT 142
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#else /* CONFIG_R2DPLUS_OLD */
|
||||
|
||||
#define CFG_FLASH_BASE (0xA0000000)
|
||||
#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */
|
||||
#define CFG_MAX_FLASH_BANKS (2)
|
||||
#define CFG_MAX_FLASH_SECT 270
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
|
||||
CFG_FLASH_BASE + 0x100000,\
|
||||
CFG_FLASH_BASE + 0x400000,\
|
||||
CFG_FLASH_BASE + 0x700000, }
|
||||
#endif /* CONFIG_R2DPLUS_OLD */
|
||||
#define CFG_MAX_FLASH_BANKS (1)
|
||||
#define CFG_MAX_FLASH_SECT 256
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_FLASH_ERASE_TOUT 120000
|
||||
#define CFG_FLASH_WRITE_TOUT 500
|
||||
#define CFG_ENV_SECT_SIZE 0x40000
|
||||
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
|
||||
/*
|
||||
* SuperH Clock setting
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Configuation settings for the Renesas R7780MP board
|
||||
*
|
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
@ -31,7 +31,8 @@
|
|||
#define CONFIG_SH4A 1
|
||||
#define CONFIG_CPU_SH7780 1
|
||||
#define CONFIG_R7780MP 1
|
||||
#define __LITTLE_ENDIAN 1
|
||||
#define CFG_R7780MP_OLD_FLASH 1
|
||||
#define __LITTLE_ENDIAN__ 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
|
@ -59,12 +60,6 @@
|
|||
/* check for keypress on bootdelay==0 */
|
||||
/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
|
||||
|
||||
/* Network setting */
|
||||
#define CONFIG_NETMASK 255.0.0.0
|
||||
#define CONFIG_IPADDR 10.0.192.82
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
#define CONFIG_GATEWAYIP 10.0.0.1
|
||||
|
||||
#define CFG_SDRAM_BASE (0x08000000)
|
||||
#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
|
||||
|
||||
|
@ -80,22 +75,30 @@
|
|||
#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
|
||||
#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
|
||||
|
||||
/* NOR Flash (S29PL127J60TFI130) */
|
||||
/* Flash board support */
|
||||
#define CFG_FLASH_BASE (0xA0000000)
|
||||
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
|
||||
#define CFG_MAX_FLASH_BANKS (2)
|
||||
#define CFG_MAX_FLASH_SECT 270
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
|
||||
#ifdef CFG_R7780MP_OLD_FLASH
|
||||
/* NOR Flash (S29PL127J60TFI130) */
|
||||
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
|
||||
# define CFG_MAX_FLASH_BANKS (2)
|
||||
# define CFG_MAX_FLASH_SECT 270
|
||||
# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
|
||||
CFG_FLASH_BASE + 0x100000,\
|
||||
CFG_FLASH_BASE + 0x400000,\
|
||||
CFG_FLASH_BASE + 0x700000, }
|
||||
#else /* CFG_R7780MP_OLD_FLASH */
|
||||
/* NOR Flash (Spantion S29GL256P) */
|
||||
# define CFG_MAX_FLASH_BANKS (1)
|
||||
# define CFG_MAX_FLASH_SECT 256
|
||||
# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
#endif /* CFG_R7780MP_OLD_FLASH */
|
||||
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
|
||||
/* Address of u-boot image in Flash */
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
|
||||
#define CFG_MONITOR_LEN (112 * 1024)
|
||||
#define CFG_MONITOR_LEN (256 * 1024)
|
||||
/* Size of DRAM reserved for malloc() use */
|
||||
#define CFG_MALLOC_LEN (256 * 1024)
|
||||
#define CFG_MALLOC_LEN (1204 * 1024)
|
||||
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_SIZE (256)
|
||||
|
@ -110,7 +113,7 @@
|
|||
#define CFG_FLASH_EMPTY_INFO
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE (16 * 1024)
|
||||
#define CFG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_FLASH_ERASE_TOUT 120000
|
||||
|
@ -141,8 +144,10 @@
|
|||
#endif /* CONFIG_CMD_PCI */
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
/* #define CONFIG_NET_MULTI
|
||||
#define CONFIG_RTL8169 */
|
||||
/*
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_RTL8169
|
||||
*/
|
||||
/* AX88696L Support(NE2000 base chip) */
|
||||
#define CONFIG_DRIVER_NE2000
|
||||
#define CONFIG_DRIVER_AX88796L
|
||||
|
|
|
@ -38,11 +38,7 @@
|
|||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
|
||||
|
@ -66,12 +62,6 @@
|
|||
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
|
||||
settings for this board */
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_SH_ETHER 1
|
||||
#define CONFIG_SH_ETHER_USE_PORT (1)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
|
||||
#define CFG_RX_ETH_BUFFER (8)
|
||||
|
||||
/* SDRAM */
|
||||
#define CFG_SDRAM_BASE (0x8C000000)
|
||||
#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
|
||||
|
|
|
@ -26,7 +26,7 @@ SOBJS-y +=
|
|||
|
||||
COBJS-y += board.o
|
||||
COBJS-y += bootm.o
|
||||
#COBJS-y += time.o
|
||||
# COBJS-y += time.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
|
||||
|
|
|
@ -112,6 +112,7 @@ static int sh_mem_env_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
static int sh_net_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
@ -127,6 +128,7 @@ static int sh_net_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
typedef int (init_fnc_t) (void);
|
||||
|
||||
|
@ -170,8 +172,8 @@ void sh_generic_init (void)
|
|||
|
||||
bd_t *bd;
|
||||
init_fnc_t **init_fnc_ptr;
|
||||
char *s;
|
||||
int i;
|
||||
char *s;
|
||||
|
||||
memset (gd, 0, CFG_GBL_DATA_SIZE);
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processer.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
static void tmu_timer_start (unsigned int timer)
|
||||
{
|
||||
|
|
Loading…
Add table
Reference in a new issue