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arm: rmobile: lager: Change to maximum CPU frequency

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Maximum CPU clock of R8A7790 that are used in lager board is 1.4GHz.
This change to use the maximum clock in this board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu 2014-03-31 14:14:25 +09:00 committed by Nobuhiro Iwamatsu
parent b1f78a2ebd
commit 2c2c6ba6c6
1 changed files with 6 additions and 0 deletions
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6
board/renesas/lager/lager.c
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@ -24,15 +24,21 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void) void s_init(void)
{ {
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 stc;
/* Watchdog init */ /* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra); writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.4GHz */
stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS(Quality-of-Service) Init */ /* QoS(Quality-of-Service) Init */
qos_init(); qos_init();
} }