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https://github.com/AsahiLinux/u-boot
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blackfin: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
4d54b43a59
commit
2bf9557744
2 changed files with 0 additions and 151 deletions
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/*
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* Lockbox/Security Masks
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*/
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#ifndef __BFIN_PERIPHERAL_LOCKBOX__
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#define __BFIN_PERIPHERAL_LOCKBOX__
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#ifndef __ASSEMBLY__
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#include "bootrom.h"
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/* SESR argument structure. Expected to reside at 0xFF900018. */
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typedef struct SESR_args {
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unsigned short usFlags; /* security firmware flags */
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unsigned short usIRQMask; /* interrupt mask */
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unsigned long ulMessageSize; /* message length in bytes */
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unsigned long ulSFEntryPoint; /* entry point of secure function */
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unsigned long ulMessagePtr; /* pointer to the buffer containing
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the digital signature and message */
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unsigned long ulReserved1; /* reserved */
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unsigned long ulReserved2; /* reserved */
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} tSESR_args;
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/* Secure Entry Service Routine */
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static void (* const sesr)(void) = (void *)_BOOTROM_SESR;
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#endif
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/* SESR flags argument bitfields */
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#define SESR_FLAGS_STAY_AT_NMI 0x0000
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#define SESR_FLAGS_DROP_BELOW_NMI 0x0001
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#define SESR_FLAGS_NO_SF_DMA 0x0000
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#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002
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#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000
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#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x00000001 /* Emulation Disable */
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#define RSTDABL 0x00000002 /* Reset Disable */
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#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */
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#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */
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#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */
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#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */
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#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */
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#define EMUOVR 0x00004000 /* Emulation Override */
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#define OTPSEN 0x00008000 /* OTP Secrets Enable */
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#define L2DABL 0x00070000 /* L2 Memory Disable */
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/* Bit masks for SECURE_CONTROL */
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#define SECURE0 0x0001 /* SECURE 0 */
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#define SECURE1 0x0002 /* SECURE 1 */
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#define SECURE2 0x0004 /* SECURE 2 */
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#define SECURE3 0x0008 /* SECURE 3 */
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/* Bit masks for SECURE_STATUS */
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#define SECMODE 0x0003 /* Secured Mode Control State */
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#define NMI 0x0004 /* Non Maskable Interrupt */
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#define AFVALID 0x0008 /* Authentication Firmware Valid */
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#define AFEXIT 0x0010 /* Authentication Firmware Exit */
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#define SECSTAT 0x00e0 /* Secure Status */
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#endif
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@ -1,89 +0,0 @@
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/*
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* SPORT Masks
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*/
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#ifndef __BFIN_PERIPHERAL_SPORT__
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#define __BFIN_PERIPHERAL_SPORT__
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/* SPORTx_TCR1 Masks */
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#define TSPEN 0x0001 /* TX enable */
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#define ITCLK 0x0002 /* Internal TX Clock Select */
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#define TDTYPE 0x000C /* TX Data Formatting Select */
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#define DTYPE_NORM 0x0004 /* Data Format Normal */
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#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
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#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
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#define TLSBIT 0x0010 /* TX Bit Order */
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#define ITFS 0x0200 /* Internal TX Frame Sync Select */
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#define TFSR 0x0400 /* TX Frame Sync Required Select */
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#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
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#define LTFS 0x1000 /* Low TX Frame Sync Select */
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#define LATFS 0x2000 /* Late TX Frame Sync Select */
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#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
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/* SPORTx_TCR2 Masks */
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#define SLEN 0x001F /* TX Word Length */
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#define TXSE 0x0100 /* TX Secondary Enable */
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#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
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#define TRFST 0x0400 /* TX Right-First Data Order */
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/* SPORTx_RCR1 Masks */
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#define RSPEN 0x0001 /* RX enable */
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#define IRCLK 0x0002 /* Internal RX Clock Select */
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#define RDTYPE 0x000C /* RX Data Formatting Select */
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#define DTYPE_NORM 0x0004 /* Data Format Normal */
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#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
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#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
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#define RLSBIT 0x0010 /* RX Bit Order */
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#define IRFS 0x0200 /* Internal RX Frame Sync Select */
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#define RFSR 0x0400 /* RX Frame Sync Required Select */
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#define LRFS 0x1000 /* Low RX Frame Sync Select */
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#define LARFS 0x2000 /* Late RX Frame Sync Select */
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#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
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/* SPORTx_RCR2 Masks */
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#define SLEN 0x001F /* RX Word Length */
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#define RXSE 0x0100 /* RX Secondary Enable */
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#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
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#define RRFST 0x0400 /* Right-First Data Order */
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/* SPORTx_STAT Masks */
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#define RXNE 0x0001 /* RX FIFO Not Empty Status */
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#define RUVF 0x0002 /* RX Underflow Status */
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#define ROVF 0x0004 /* RX Overflow Status */
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#define TXF 0x0008 /* TX FIFO Full Status */
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#define TUVF 0x0010 /* TX Underflow Status */
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#define TOVF 0x0020 /* TX Overflow Status */
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#define TXHRE 0x0040 /* TX Hold Register Empty */
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/* SPORTx_MCMC1 Masks */
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#define WSIZE 0xF000 /* Multichannel Window Size Field */
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#define WOFF 0x03FF /* Multichannel Window Offset Field */
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/* SPORTx_MCMC2 Masks */
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#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
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#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
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#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
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#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
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#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
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#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
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#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
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#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
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#define MFD 0xF000 /* Multichannel Frame Delay */
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#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
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#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
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#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
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#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
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#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
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#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
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#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
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#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
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#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
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#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
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#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
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#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
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#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
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#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
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#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
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#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
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#endif
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