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83xx: add missing TIMING_CFG1_CASLAT_* defines
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -890,6 +890,8 @@
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#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
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#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
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#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
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#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
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#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
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/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
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*/
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