mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
rockchip: rk3288: Fix pinctrl for GPIO bank 0
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
parent
633fdab0cb
commit
2b51784aef
1 changed files with 19 additions and 2 deletions
|
@ -588,6 +588,7 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
|
||||||
struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
|
struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
|
||||||
uint shift, ind = index;
|
uint shift, ind = index;
|
||||||
uint mask;
|
uint mask;
|
||||||
|
uint value;
|
||||||
u32 *addr;
|
u32 *addr;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
|
@ -596,7 +597,18 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
|
||||||
&mask);
|
&mask);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
rk_clrsetreg(addr, mask << shift, muxval << shift);
|
|
||||||
|
/*
|
||||||
|
* PMU_GPIO0 registers cannot be selectively written so we cannot use
|
||||||
|
* rk_clrsetreg() here. However, the upper 16 bits are reserved and
|
||||||
|
* are ignored when written, so we can use the same code as for the
|
||||||
|
* other GPIO banks providing that we preserve the value of the other
|
||||||
|
* bits.
|
||||||
|
*/
|
||||||
|
value = readl(addr);
|
||||||
|
value &= ~(mask << shift);
|
||||||
|
value |= (mask << (shift + 16)) | (muxval << shift);
|
||||||
|
writel(value, addr);
|
||||||
|
|
||||||
/* Handle pullup/pulldown */
|
/* Handle pullup/pulldown */
|
||||||
if (flags) {
|
if (flags) {
|
||||||
|
@ -614,7 +626,12 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
|
||||||
addr = &priv->grf->gpio1_p[banknum - 1][ind];
|
addr = &priv->grf->gpio1_p[banknum - 1][ind];
|
||||||
debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
|
debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
|
||||||
shift);
|
shift);
|
||||||
rk_clrsetreg(addr, 3 << shift, val << shift);
|
|
||||||
|
/* As above, rk_clrsetreg() cannot be used here. */
|
||||||
|
value = readl(addr);
|
||||||
|
value &= ~(mask << shift);
|
||||||
|
value |= (3 << (shift + 16)) | (val << shift);
|
||||||
|
writel(value, addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
Loading…
Reference in a new issue