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ddr: marvell: a38x: fix memory cs size function

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commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
This commit is contained in:
Moti Buskila 2021-02-19 17:11:22 +01:00 committed by Stefan Roese
parent b85c6fb065
commit 2ab7bbf71e
2 changed files with 10 additions and 5 deletions
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9
drivers/ddr/marvell/a38x/mv_ddr_plat.c
View file

@ -4,6 +4,7 @@
*/ */
#include "ddr3_init.h" #include "ddr3_init.h"
#include "mv_ddr_common.h"
#include "mv_ddr_training_db.h" #include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h" #include "mv_ddr_regs.h"
#include "mv_ddr_sys_env_lib.h" #include "mv_ddr_sys_env_lib.h"
@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
return MV_BAD_VALUE; return MV_BAD_VALUE;
} }
*cs_size = cs_mem_size << 20; /* write cs size in bytes */ *cs_size = cs_mem_size;
return MV_OK; return MV_OK;
} }
@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
{ {
u32 reg, cs; u32 reg, cs;
uint64_t mem_total_size = 0; uint64_t mem_total_size = 0;
uint64_t cs_mem_size_mb = 0;
uint64_t cs_mem_size = 0; uint64_t cs_mem_size = 0;
uint64_t mem_total_size_c, cs_mem_size_c; uint64_t mem_total_size_c, cs_mem_size_c;
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
u32 physical_mem_size; u32 physical_mem_size;
u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE; u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
for (cs = 0; cs < MAX_CS_NUM; cs++) { for (cs = 0; cs < MAX_CS_NUM; cs++) {
if (cs_ena & (1 << cs)) { if (cs_ena & (1 << cs)) {
/* get CS size */ /* get CS size */
if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK) if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK)
return MV_FAIL; return MV_FAIL;
cs_mem_size = cs_mem_size_mb * _1M;
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
/* /*
@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
*/ */
mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff; mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff;
cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff; cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff;
/* if the sum less than 2 G - calculate the value */ /* if the sum less than 2 G - calculate the value */
if (mem_total_size_c + cs_mem_size_c < 0x10000) if (mem_total_size_c + cs_mem_size_c < 0x10000)
mem_total_size += cs_mem_size; mem_total_size += cs_mem_size;

6
drivers/ddr/marvell/a38x/xor.c
View file

@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void)
{ {
u32 cs_c, max_cs; u32 cs_c, max_cs;
u32 cs_ena = 0; u32 cs_ena = 0;
uint64_t total_mem_size, cs_mem_size = 0; uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
printf("DDR Training Sequence - Start scrubbing\n"); printf("DDR Training Sequence - Start scrubbing\n");
max_cs = mv_ddr_cs_num_get(); max_cs = mv_ddr_cs_num_get();
@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void)
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* all chip-selects are of same size */ /* all chip-selects are of same size */
ddr3_calc_mem_cs_size(0, &cs_mem_size); ddr3_calc_mem_cs_size(0, &cs_mem_size_mb);
#endif #endif
cs_mem_size = cs_mem_size_mb * _1M;
mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
total_mem_size = max_cs * cs_mem_size; total_mem_size = max_cs * cs_mem_size;
mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef); mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);