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arm: mvebu: Remove unused macro CONFIG_SYS_U_BOOT_OFFS
Macro CONFIG_SYS_U_BOOT_OFFS is set but not used anymore. Remove it. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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ad906753c2
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12 changed files with 2 additions and 51 deletions
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@ -69,12 +69,8 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
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#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x20000
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#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
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/* SPL related MMC defines */
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/* SPL related MMC defines */
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#define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#endif
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#endif
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@ -85,15 +85,9 @@
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_I2C
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#define CONFIG_SPL_I2C
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x30000
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#endif
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
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/* SPL related MMC defines */
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/* SPL related MMC defines */
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_U_BOOT_OFFS (168 << 10)
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#endif
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#endif
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@ -65,7 +65,4 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x20000
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#endif /* _CONFIG_DB_88F6720_H */
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#endif /* _CONFIG_DB_88F6720_H */
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@ -59,11 +59,6 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x24000
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#endif
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/*
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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* to enable certain macros
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@ -71,14 +71,8 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x24000
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#endif
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
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/* SPL related MMC defines */
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/* SPL related MMC defines */
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#define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#endif
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#endif
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@ -78,9 +78,6 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x20000
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SPD_EEPROM 0x4e
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#define CONFIG_SPD_EEPROM 0x4e
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#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
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#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
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@ -68,11 +68,6 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x24000
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#endif
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/* DS414 bus width is 32bits */
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/* DS414 bus width is 32bits */
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#define CONFIG_DDR_32BIT
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#define CONFIG_DDR_32BIT
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@ -69,12 +69,8 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
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#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x20000
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#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
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/* SPL related MMC defines */
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/* SPL related MMC defines */
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#define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#endif
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#endif
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@ -93,9 +93,6 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x1a000
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
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#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
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@ -45,14 +45,8 @@
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_DRIVERS_MISC
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#define CONFIG_SPL_DRIVERS_MISC
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#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
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/* SPL related SPI defines */
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# define CONFIG_SYS_U_BOOT_OFFS 0x24000
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#endif
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#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
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#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
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/* SPL related MMC defines */
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/* SPL related MMC defines */
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# define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
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# ifdef CONFIG_SPL_BUILD
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# ifdef CONFIG_SPL_BUILD
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# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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# endif
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# endif
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@ -97,7 +97,4 @@
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS 0x24000
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#endif /* _CONFIG_X530_H */
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#endif /* _CONFIG_X530_H */
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@ -3271,7 +3271,6 @@ CONFIG_SYS_USE_NAND
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CONFIG_SYS_USE_NANDFLASH
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CONFIG_SYS_USE_NANDFLASH
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CONFIG_SYS_USE_NORFLASH
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CONFIG_SYS_USE_NORFLASH
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CONFIG_SYS_USR_EXCEP
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CONFIG_SYS_USR_EXCEP
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CONFIG_SYS_U_BOOT_OFFS
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CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
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CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
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CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
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CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
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CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
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CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
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