arm: mvebu: Remove unused macro CONFIG_SYS_U_BOOT_OFFS

Macro CONFIG_SYS_U_BOOT_OFFS is set but not used anymore. Remove it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár 2021-07-23 11:14:32 +02:00 committed by Stefan Roese
parent ad906753c2
commit 2a85fdad3e
12 changed files with 2 additions and 51 deletions

View file

@ -69,12 +69,8 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) #if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x20000
#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related MMC defines */ /* SPL related MMC defines */
#define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif #endif

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@ -85,15 +85,9 @@
#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_I2C #define CONFIG_SPL_I2C
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x30000
#endif
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */ /* SPL related MMC defines */
#define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_OFFS (168 << 10)
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif #endif

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@ -65,7 +65,4 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x20000
#endif /* _CONFIG_DB_88F6720_H */ #endif /* _CONFIG_DB_88F6720_H */

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@ -59,11 +59,6 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x24000
#endif
/* /*
* mv-common.h should be defined after CMD configs since it used them * mv-common.h should be defined after CMD configs since it used them
* to enable certain macros * to enable certain macros

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@ -71,14 +71,8 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x24000
#endif
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */ /* SPL related MMC defines */
#define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif #endif

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@ -78,9 +78,6 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SPD_EEPROM 0x4e #define CONFIG_SPD_EEPROM 0x4e
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */

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@ -68,11 +68,6 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x24000
#endif
/* DS414 bus width is 32bits */ /* DS414 bus width is 32bits */
#define CONFIG_DDR_32BIT #define CONFIG_DDR_32BIT

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@ -69,12 +69,8 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) #if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x20000
#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related MMC defines */ /* SPL related MMC defines */
#define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif #endif

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@ -93,9 +93,6 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x1a000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */

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@ -45,14 +45,8 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SPL_DRIVERS_MISC #define CONFIG_SPL_DRIVERS_MISC
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
/* SPL related SPI defines */
# define CONFIG_SYS_U_BOOT_OFFS 0x24000
#endif
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC #ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
/* SPL related MMC defines */ /* SPL related MMC defines */
# define CONFIG_SYS_U_BOOT_OFFS (160 << 10)
# ifdef CONFIG_SPL_BUILD # ifdef CONFIG_SPL_BUILD
# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ # define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
# endif # endif

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@ -97,7 +97,4 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS 0x24000
#endif /* _CONFIG_X530_H */ #endif /* _CONFIG_X530_H */

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@ -3271,7 +3271,6 @@ CONFIG_SYS_USE_NAND
CONFIG_SYS_USE_NANDFLASH CONFIG_SYS_USE_NANDFLASH
CONFIG_SYS_USE_NORFLASH CONFIG_SYS_USE_NORFLASH
CONFIG_SYS_USR_EXCEP CONFIG_SYS_USR_EXCEP
CONFIG_SYS_U_BOOT_OFFS
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT