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sh: Add support Renesas SH7734

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Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu 2012-01-11 10:45:01 +09:00 committed by Nobuhiro Iwamatsu
parent 4398d55991
commit 2a57e7ec96
3 changed files with 55 additions and 0 deletions
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2
arch/sh/include/asm/cpu_sh4.h
View file

@ -46,6 +46,8 @@
# include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7724)
# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)

43
arch/sh/include/asm/cpu_sh7734.h Normal file
View file

@ -0,0 +1,43 @@
/*
* (C) Copyright 2008, 2011 Renesas Solutions Corp.
*
* SH7734 Internal I/O register
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_CPU_SH7734_H_
#define _ASM_CPU_SH7734_H_
#define CCR 0xFF00001C
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* SCIF */
#define SCIF0_BASE 0xFFE40000
#define SCIF1_BASE 0xFFE41000
#define SCIF2_BASE 0xFFE42000
#define SCIF3_BASE 0xFFE43000
#define SCIF4_BASE 0xFFE44000
#define SCIF5_BASE 0xFFE45000
/* Timer */
#define TSTR 0xFFD80004
#define TCNT0 0xFFD8000C
#define TCR0 0xFFD80010
#endif /* _ASM_CPU_SH7734_H_ */

10
drivers/serial/serial_sh.h
View file

@ -112,6 +112,15 @@ struct uart_port {
# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH7734)
# define SCSPTR0 0xFFE40020
# define SCSPTR1 0xFFE41020
# define SCSPTR2 0xFFE42020
# define SCSPTR3 0xFFE43020
# define SCSPTR4 0xFFE44020
# define SCSPTR5 0xFFE45020
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH4_202)
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
@ -216,6 +225,7 @@ struct uart_port {
defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7722) || \
defined(CONFIG_CPU_SH7734) || \
defined(CONFIG_CPU_SH7750S) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \