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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
mpc85xx, socrates: add DM PCI support
add DM PCI support on the socrates board. use PCIE_FSL now. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
parent
98beb60a2a
commit
2a51fe01be
4 changed files with 12 additions and 46 deletions
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@ -31,9 +31,7 @@
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struct law_entry law_table[] = {
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
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SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
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#if defined(CONFIG_SYS_FPGA_BASE)
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#if defined(CONFIG_SYS_FPGA_BASE)
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SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#endif
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#endif
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@ -50,7 +50,7 @@ int checkboard (void)
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}
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}
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putc('\n');
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putc('\n');
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#ifdef CONFIG_PCI
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#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
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/* Check the PCI_clk sel bit */
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/* Check the PCI_clk sel bit */
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if (in_be32(&gur->porpllsr) & (1<<15)) {
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if (in_be32(&gur->porpllsr) & (1<<15)) {
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src = "SYSCLK";
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src = "SYSCLK";
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@ -126,6 +126,10 @@ int misc_init_r (void)
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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}
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}
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#if defined(CONFIG_DM_PCI)
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pci_init();
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#endif
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return 0;
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return 0;
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}
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}
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@ -168,40 +172,6 @@ void local_bus_init (void)
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upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
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upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
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}
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}
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc85xxads_config_table[] = {
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{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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{}
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};
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#endif
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static struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc85xxads_config_table,
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#endif
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};
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#endif /* CONFIG_PCI */
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void pci_init_board (void)
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{
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#ifdef CONFIG_PCI
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pci_mpc85xx_init (&hose);
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#endif /* CONFIG_PCI */
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_R
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#ifdef CONFIG_BOARD_EARLY_INIT_R
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int board_early_init_r (void)
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int board_early_init_r (void)
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{
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{
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@ -14,6 +14,10 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_HUSH_PARSER=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_REGINFO=y
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CONFIG_CMD_REGINFO=y
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# CONFIG_BOOTM_NETBSD is not set
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# CONFIG_BOOTM_PLAN9 is not set
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# CONFIG_BOOTM_RTEMS is not set
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# CONFIG_BOOTM_VXWORKS is not set
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_I2C=y
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@ -44,6 +48,8 @@ CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_MARVELL=y
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CONFIG_MII=y
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CONFIG_MII=y
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CONFIG_TSEC_ENET=y
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CONFIG_TSEC_ENET=y
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CONFIG_DM_PCI=y
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CONFIG_PCI_MPC85XX=y
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CONFIG_DM_RTC=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_RX8025=y
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CONFIG_RTC_RX8025=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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@ -53,4 +59,5 @@ CONFIG_SYS_NS16550=y
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CONFIG_USB=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_DM_USB=y
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# CONFIG_USB_EHCI_HCD is not set
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# CONFIG_USB_EHCI_HCD is not set
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CONFIG_USB_OHCI_PCI=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_STORAGE=y
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@ -19,8 +19,6 @@
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/* High Level Configuration Options */
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/* High Level Configuration Options */
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#define CONFIG_SOCRATES 1
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#define CONFIG_SOCRATES 1
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#define CONFIG_PCI_INDIRECT_BRIDGE
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/*
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/*
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* Only possible on E500 Version 2 or newer cores.
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* Only possible on E500 Version 2 or newer cores.
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*/
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*/
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@ -156,7 +154,6 @@
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* General PCI
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* General PCI
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* Memory space is mapped 1-1.
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* Memory space is mapped 1-1.
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*/
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*/
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#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
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/* PCI is clocked by the external source at 33 MHz */
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/* PCI is clocked by the external source at 33 MHz */
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#define CONFIG_PCI_CLK_FREQ 33000000
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#define CONFIG_PCI_CLK_FREQ 33000000
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@ -167,10 +164,6 @@
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#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
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#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
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#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
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#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
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#if defined(CONFIG_PCI)
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3 1
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@ -292,8 +285,6 @@
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/* USB support */
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/* USB support */
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_PCI_OHCI 1
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#define CONFIG_PCI_OHCI 1
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#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
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#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
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#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
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#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
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