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arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration

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This patch fixes the DP audio and video PLL configurations for the
zynqmp-zcu102-revA evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b2eb87758e0cd4844e1754da8c58fce58d9cf683.1651740949.git.michal.simek@amd.com
This commit is contained in:
Neal Frager 2022-05-05 10:55:51 +02:00 committed by Michal Simek
parent a3659640e0
commit 2946c551f1
1 changed files with 2 additions and 2 deletions
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4
board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
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@ -85,8 +85,8 @@ static unsigned long psu_clock_init_data(void)
psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U); psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U); psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U); psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U);