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board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev
Starting with PCB revision 3 we can safely make use of higher RAM frequency again. Make use of the EEPROM detection to determine the revision and use the updated RAM timings for new SoMs. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de>
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@ -46,6 +46,67 @@ void spl_dram_init(void)
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if (!ret)
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phytec_print_som_info(NULL);
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ret = phytec_get_rev(NULL);
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if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
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dram_timing.ddrc_cfg[3].val = 0x1323;
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dram_timing.ddrc_cfg[4].val = 0x1e84800;
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dram_timing.ddrc_cfg[5].val = 0x7a0118;
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dram_timing.ddrc_cfg[8].val = 0xc00307a3;
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dram_timing.ddrc_cfg[9].val = 0xc50000;
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dram_timing.ddrc_cfg[10].val = 0xf4003f;
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dram_timing.ddrc_cfg[11].val = 0xf30000;
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dram_timing.ddrc_cfg[14].val = 0x2028222a;
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dram_timing.ddrc_cfg[15].val = 0x8083f;
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dram_timing.ddrc_cfg[16].val = 0xe0e000;
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dram_timing.ddrc_cfg[17].val = 0x12040a12;
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dram_timing.ddrc_cfg[18].val = 0x2050f0f;
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dram_timing.ddrc_cfg[19].val = 0x1010009;
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dram_timing.ddrc_cfg[20].val = 0x502;
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dram_timing.ddrc_cfg[21].val = 0x20800;
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dram_timing.ddrc_cfg[22].val = 0xe100002;
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dram_timing.ddrc_cfg[23].val = 0x120;
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dram_timing.ddrc_cfg[24].val = 0xc80064;
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dram_timing.ddrc_cfg[25].val = 0x3e8001e;
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dram_timing.ddrc_cfg[26].val = 0x3207a12;
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dram_timing.ddrc_cfg[28].val = 0x4a3820e;
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dram_timing.ddrc_cfg[30].val = 0x230e;
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dram_timing.ddrc_cfg[37].val = 0x799;
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dram_timing.ddrc_cfg[38].val = 0x9141d1c;
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dram_timing.ddrc_cfg[74].val = 0x302;
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dram_timing.ddrc_cfg[83].val = 0x599;
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dram_timing.ddrc_cfg[99].val = 0x302;
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dram_timing.ddrc_cfg[108].val = 0x599;
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dram_timing.ddrphy_cfg[66].val = 0x18;
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dram_timing.ddrphy_cfg[75].val = 0x1e3;
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dram_timing.ddrphy_cfg[77].val = 0x1e3;
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dram_timing.ddrphy_cfg[79].val = 0x1e3;
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dram_timing.ddrphy_cfg[145].val = 0x3e8;
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dram_timing.fsp_msg[0].drate = 4000;
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dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
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dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
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dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
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dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
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dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
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dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
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dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
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dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
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dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
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dram_timing.fsp_msg[3].drate = 4000;
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dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
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dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
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dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
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dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
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dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
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dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
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dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
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dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
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dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
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dram_timing.ddrphy_pie[480].val = 0x465;
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dram_timing.ddrphy_pie[481].val = 0xfa;
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dram_timing.ddrphy_pie[482].val = 0x9c4;
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dram_timing.fsp_table[0] = 4000;
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}
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out:
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ddr_init(&dram_timing);
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}
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