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arm: dts: k3-j721e-main: Add C66x DSP nodes

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The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2019-09-04 16:01:39 +05:30 committed by Tom Rini
parent 55f8eb3169
commit 293e39780d
2 changed files with 26 additions and 0 deletions
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2
arch/arm/dts/k3-j721e-common-proc-board.dts
View file

@ -20,6 +20,8 @@
remoteproc3 = &main_r5fss0_core1;
remoteproc4 = &main_r5fss1_core0;
remoteproc5 = &main_r5fss1_core1;
remoteproc6 = &c66_0;
remoteproc7 = &c66_1;
};
};

24
arch/arm/dts/k3-j721e-main.dtsi
View file

@ -304,4 +304,28 @@
loczrama = <1>;
};
};
c66_0: dsp@4d80800000 {
compatible = "ti,j721e-c66-dsp";
reg = <0x4d 0x80800000 0x00 0x00048000>,
<0x4d 0x80e00000 0x00 0x00008000>,
<0x4d 0x80f00000 0x00 0x00008000>;
reg-names = "l2sram", "l1pram", "l1dram";
ti,sci = <&dmsc>;
ti,sci-dev-id = <142>;
ti,sci-proc-ids = <0x03 0xFF>;
resets = <&k3_reset 142 1>;
};
c66_1: dsp@4d81800000 {
compatible = "ti,j721e-c66-dsp";
reg = <0x4d 0x81800000 0x00 0x00048000>,
<0x4d 0x81e00000 0x00 0x00008000>,
<0x4d 0x81f00000 0x00 0x00008000>;
reg-names = "l2sram", "l1pram", "l1dram";
ti,sci = <&dmsc>;
ti,sci-dev-id = <143>;
ti,sci-proc-ids = <0x04 0xFF>;
resets = <&k3_reset 143 1>;
};
};