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https://github.com/AsahiLinux/u-boot
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MX: Added Freescale Power Management Driver
The patch add supports for the Freescale's Power Management Controller (known as Atlas) used together with i.MX31/51 processors. It was tested with a MC13783 (MX31) and MC13892 (MX51). Signed-off-by: Stefano Babic <sbabic@denx.de>
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3 changed files with 329 additions and 0 deletions
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@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
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COBJS-$(CONFIG_NS87308) += ns87308.o
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COBJS-$(CONFIG_NS87308) += ns87308.o
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COBJS-$(CONFIG_STATUS_LED) += status_led.o
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COBJS-$(CONFIG_STATUS_LED) += status_led.o
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COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
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COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
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COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o
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COBJS := $(COBJS-y)
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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SRCS := $(COBJS:.o=.c)
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200
drivers/misc/fsl_pmic.c
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200
drivers/misc/fsl_pmic.c
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@ -0,0 +1,200 @@
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/*
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <spi.h>
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#include <asm/errno.h>
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#include <linux/types.h>
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#include <fsl_pmic.h>
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static struct spi_slave *slave;
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struct spi_slave *pmic_spi_probe(void)
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{
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return spi_setup_slave(CONFIG_FSL_PMIC_BUS,
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CONFIG_FSL_PMIC_CS,
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CONFIG_FSL_PMIC_CLK,
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CONFIG_FSL_PMIC_MODE);
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}
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void pmic_spi_free(struct spi_slave *slave)
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{
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if (slave)
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spi_free_slave(slave);
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}
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u32 pmic_reg(u32 reg, u32 val, u32 write)
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{
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u32 pmic_tx, pmic_rx;
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if (!slave) {
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slave = pmic_spi_probe();
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if (!slave)
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return -1;
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}
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if (reg > 63 || write > 1) {
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printf("<reg num> = %d is invalid. Should be less then 63\n",
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reg);
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return -1;
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}
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if (spi_claim_bus(slave))
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return -1;
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pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
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if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
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SPI_XFER_BEGIN | SPI_XFER_END)) {
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spi_release_bus(slave);
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return -1;
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}
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if (write) {
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pmic_tx &= ~(1 << 31);
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if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
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SPI_XFER_BEGIN | SPI_XFER_END)) {
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spi_release_bus(slave);
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return -1;
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}
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}
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spi_release_bus(slave);
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return pmic_rx;
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}
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void pmic_reg_write(u32 reg, u32 value)
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{
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pmic_reg(reg, value, 1);
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}
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u32 pmic_reg_read(u32 reg)
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{
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return pmic_reg(reg, 0, 0);
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}
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void pmic_show_pmic_info(void)
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{
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u32 rev_id;
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rev_id = pmic_reg_read(REG_IDENTIFICATION);
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printf("PMIC ID: 0x%08x [Rev: ", rev_id);
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switch (rev_id & 0x1F) {
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case 0x1:
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puts("1.0");
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break;
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case 0x9:
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puts("1.1");
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break;
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case 0xA:
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puts("1.2");
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break;
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case 0x10:
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puts("2.0");
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break;
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case 0x11:
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puts("2.1");
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break;
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case 0x18:
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puts("3.0");
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break;
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case 0x19:
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puts("3.1");
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break;
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case 0x1A:
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puts("3.2");
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break;
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case 0x2:
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puts("3.2A");
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break;
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case 0x1B:
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puts("3.3");
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break;
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case 0x1D:
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puts("3.5");
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break;
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default:
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puts("unknown");
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break;
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}
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puts("]\n");
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}
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static void pmic_dump(int numregs)
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{
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u32 val;
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int i;
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pmic_show_pmic_info();
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for (i = 0; i < numregs; i++) {
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val = pmic_reg_read(i);
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if (!(i % 8))
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printf ("\n0x%02x: ", i);
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printf("%08x ", val);
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}
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puts("\n");
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}
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int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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char *cmd;
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int nregs;
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u32 val;
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/* at least two arguments please */
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if (argc < 2) {
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cmd_usage(cmdtp);
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return 1;
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}
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cmd = argv[1];
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if (strcmp(cmd, "dump") == 0) {
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if (argc < 3) {
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cmd_usage(cmdtp);
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return 1;
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}
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nregs = simple_strtoul(argv[2], NULL, 16);
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pmic_dump(nregs);
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return 0;
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}
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if (strcmp(cmd, "write") == 0) {
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if (argc < 4) {
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cmd_usage(cmdtp);
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return 1;
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}
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nregs = simple_strtoul(argv[2], NULL, 16);
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val = simple_strtoul(argv[3], NULL, 16);
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pmic_reg_write(nregs, val);
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return 0;
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}
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/* No subcommand found */
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return 1;
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}
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U_BOOT_CMD(
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pmic, CONFIG_SYS_MAXARGS, 1, do_pmic,
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"Freescale PMIC (Atlas)",
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"dump [numregs] dump registers\n"
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"pmic write <reg> <value> - write register"
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);
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128
include/fsl_pmic.h
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128
include/fsl_pmic.h
Normal file
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@ -0,0 +1,128 @@
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/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_PMIC_H__
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#define __FSL_PMIC_H__
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/*
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* The registers of different PMIC has the same meaning
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* but the bit positions of the fields can differ or
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* some fields has a meaning only on some devices.
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* You have to check with the internal SPI bitmap
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* (see Freescale Documentation) to set the registers
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* for the device you are using
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*/
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enum {
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REG_INT_STATUS0 = 0,
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REG_INT_MASK0,
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REG_INT_SENSE0,
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REG_INT_STATUS1,
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REG_INT_MASK1,
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REG_INT_SENSE1,
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REG_PU_MODE_S,
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REG_IDENTIFICATION,
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REG_UNUSED0,
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REG_ACC0,
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REG_ACC1, /*10 */
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REG_UNUSED1,
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REG_UNUSED2,
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REG_POWER_CTL0,
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REG_POWER_CTL1,
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REG_POWER_CTL2,
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REG_REGEN_ASSIGN,
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REG_UNUSED3,
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REG_MEM_A,
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REG_MEM_B,
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REG_RTC_TIME, /*20 */
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REG_RTC_ALARM,
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REG_RTC_DAY,
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REG_RTC_DAY_ALARM,
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REG_SW_0,
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REG_SW_1,
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REG_SW_2,
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REG_SW_3,
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REG_SW_4,
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REG_SW_5,
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REG_SETTING_0, /*30 */
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REG_SETTING_1,
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REG_MODE_0,
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REG_MODE_1,
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REG_POWER_MISC,
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REG_UNUSED4,
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REG_UNUSED5,
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REG_UNUSED6,
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REG_UNUSED7,
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REG_UNUSED8,
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REG_UNUSED9, /*40 */
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REG_UNUSED10,
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REG_UNUSED11,
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REG_ADC0,
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REG_ADC1,
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REG_ADC2,
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REG_ADC3,
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REG_ADC4,
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REG_CHARGE,
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REG_USB0,
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REG_USB1, /*50 */
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REG_LED_CTL0,
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REG_LED_CTL1,
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REG_LED_CTL2,
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REG_LED_CTL3,
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REG_UNUSED12,
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REG_UNUSED13,
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REG_TRIM0,
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REG_TRIM1,
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REG_TEST0,
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REG_TEST1, /*60 */
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REG_TEST2,
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REG_TEST3,
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REG_TEST4,
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};
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/* REG_POWER_MISC */
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#define GPO1EN (1 << 6)
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#define GPO1STBY (1 << 7)
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#define GPO2EN (1 << 8)
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#define GPO2STBY (1 << 9)
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#define GPO3EN (1 << 10)
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#define GPO3STBY (1 << 11)
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#define GPO4EN (1 << 12)
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#define GPO4STBY (1 << 13)
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#define PWGT1SPIEN (1 << 15)
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#define PWGT2SPIEN (1 << 16)
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#define PWUP (1 << 21)
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/* Power Control 0 */
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#define COINCHEN (1 << 23)
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#define BATTDETEN (1 << 19)
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/* Interrupt status 1 */
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#define RTCRSTI (1 << 7)
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void pmic_show_pmic_info(void);
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void pmic_reg_write(u32 reg, u32 value);
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u32 pmic_reg_read(u32 reg);
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#endif
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