Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-12 07:57:21 +00:00
Code Issues Projects Releases Packages Wiki Activity

mxs: Explain why some mx23 DDR registers are not configured

Browse source 
Put an explanation in the source code as to why some DDR registers do not
need to be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2013-05-05 16:11:59 +00:00 committed by Stefano Babic
parent 0b323439a5
commit 286a88cf34
1 changed files with 9 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View file

@ -127,6 +127,15 @@ static void initialize_dram_values(void)
mxs_adjust_memory_params(dram_vals);
/*
* HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
* per FSL bootlets code.
*
* mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
* "reserved".
* HW_DRAM_CTL8 is setup as the last element.
* So skip the initialization of these HW_DRAM_CTL registers.
*/
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;