Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-11 15:37:23 +00:00
Code Issues Projects Releases Packages Wiki Activity

dm: ddr: socfpga: fix gen5 ddr driver to not use bss

Browse source 
This driver uses bss from SPL board_init_f(). Change it to move all the
data from bss to a common struct allocated on the stack (64 byte).

In addition to saving 28 bytes of bss, the code even gets 264 bytes
smaller.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Simon Goldschmidt 2019-07-11 21:18:12 +02:00 committed by Marek Vasut
parent b94655a4b7
commit 285b3cb939
2 changed files with 744 additions and 646 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1354
drivers/ddr/altera/sequencer.c
View file

File diff suppressed because it is too large Load diff

36
drivers/ddr/altera/sequencer.h
View file

@ -6,14 +6,16 @@
#ifndef _SEQUENCER_H_ #ifndef _SEQUENCER_H_
#define _SEQUENCER_H_ #define _SEQUENCER_H_
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \ #define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
/ rwcfg->mem_if_write_dqs_width) / seq->rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \ #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \
/ rwcfg->mem_if_write_dqs_width) seq->rwcfg->true_mem_data_mask_width \
/ seq->rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \ #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
/ rwcfg->mem_if_write_dqs_width) / seq->rwcfg->mem_if_write_dqs_width)
#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS) #define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
/ NUM_SHADOW_REGS)
#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
@ -256,6 +258,26 @@ struct socfpga_sdr {
u8 _align9[0xea4]; u8 _align9[0xea4];
}; };
struct socfpga_sdrseq {
const struct socfpga_sdram_rw_mgr_config *rwcfg;
const struct socfpga_sdram_io_config *iocfg;
const struct socfpga_sdram_misc_config *misccfg;
/* calibration steps requested by the rtl */
u16 dyn_calib_steps;
/*
* To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
* instead of static, we use boolean logic to select between
* non-skip and skip values
*
* The mask is set to include all bits when not-skipping, but is
* zero when skipping
*/
u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
struct gbl_type gbl;
struct param_type param;
};
int sdram_calibration_full(struct socfpga_sdr *sdr); int sdram_calibration_full(struct socfpga_sdr *sdr);
#endif /* _SEQUENCER_H_ */ #endif /* _SEQUENCER_H_ */