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https://github.com/AsahiLinux/u-boot
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[MIPS] asm headers' updates
Make some asm headers adjusted to the latest Linux kernel. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi
parent
e1390801a3
commit
282223a607
9 changed files with 418 additions and 345 deletions
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@ -1,18 +1,62 @@
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/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
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*
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) by Ralf Baechle
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* Copyright (C) 1996, 99, 2003 by Ralf Baechle
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*/
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#ifndef _MIPS_BYTEORDER_H
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#define _MIPS_BYTEORDER_H
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#ifndef _ASM_BYTEORDER_H
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#define _ASM_BYTEORDER_H
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#include <asm/types.h>
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#ifdef __GNUC__
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#ifdef CONFIG_CPU_MIPSR2
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static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
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{
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__asm__(
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" wsbh %0, %1 \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch__swab16(x) ___arch__swab16(x)
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static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
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{
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__asm__(
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" wsbh %0, %1 \n"
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" rotr %0, %0, 16 \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch__swab32(x) ___arch__swab32(x)
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#ifdef CONFIG_CPU_MIPS64_R2
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static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
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{
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__asm__(
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" dsbh %0, %1 \n"
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" dshd %0, %0 \n"
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" drotr %0, %0, 32 \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch__swab64(x) ___arch__swab64(x)
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#endif /* CONFIG_CPU_MIPS64_R2 */
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#endif /* CONFIG_CPU_MIPSR2 */
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#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
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# define __BYTEORDER_HAS_U64__
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# define __SWAB_64_THRU_32__
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@ -20,12 +64,12 @@
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#endif /* __GNUC__ */
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#if defined (__MIPSEB__)
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#if defined(__MIPSEB__)
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# include <linux/byteorder/big_endian.h>
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#elif defined (__MIPSEL__)
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#elif defined(__MIPSEL__)
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# include <linux/byteorder/little_endian.h>
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#else
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# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
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#endif
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#endif /* _MIPS_BYTEORDER_H */
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#endif /* _ASM_BYTEORDER_H */
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@ -1,10 +1,12 @@
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/*
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* cachectl.h -- defines for MIPS cache control system calls
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
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*/
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#ifndef __ASM_MIPS_CACHECTL
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#define __ASM_MIPS_CACHECTL
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#ifndef _ASM_CACHECTL
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#define _ASM_CACHECTL
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/*
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* Options for cacheflush system call
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@ -21,4 +23,4 @@
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#define CACHEABLE 0 /* make pages cacheable */
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#define UNCACHEABLE 1 /* make pages uncacheable */
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#endif /* __ASM_MIPS_CACHECTL */
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#endif /* _ASM_CACHECTL */
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@ -5,43 +5,81 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) Copyright 1996, 1997 by Ralf Baechle
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* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
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* (C) Copyright 1999 Silicon Graphics, Inc.
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*/
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#ifndef __ASM_MIPS_CACHEOPS_H
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#define __ASM_MIPS_CACHEOPS_H
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#ifndef __ASM_CACHEOPS_H
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#define __ASM_CACHEOPS_H
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/*
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* Cache Operations
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* Cache Operations available on all MIPS processors with R4000-style caches
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*/
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#define Index_Invalidate_I 0x00
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#define Index_Writeback_Inv_D 0x01
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#define Index_Invalidate_SI 0x02
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#define Index_Writeback_Inv_SD 0x03
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#define Index_Load_Tag_I 0x04
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#define Index_Load_Tag_D 0x05
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#define Index_Load_Tag_SI 0x06
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#define Index_Load_Tag_SD 0x07
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#define Index_Store_Tag_I 0x08
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#define Index_Store_Tag_D 0x09
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#define Index_Store_Tag_SI 0x0A
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#define Index_Store_Tag_SD 0x0B
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#define Create_Dirty_Excl_D 0x0d
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#define Create_Dirty_Excl_SD 0x0f
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#if defined(CONFIG_CPU_LOONGSON2)
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#define Hit_Invalidate_I 0x00
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#else
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#define Hit_Invalidate_I 0x10
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#endif
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#define Hit_Invalidate_D 0x11
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#define Hit_Invalidate_SI 0x12
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#define Hit_Invalidate_SD 0x13
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#define Fill 0x14
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#define Hit_Writeback_Inv_D 0x15
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/* 0x16 is unused */
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#define Hit_Writeback_Inv_SD 0x17
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/*
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* R4000-specific cacheops
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*/
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#define Create_Dirty_Excl_D 0x0d
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#define Fill 0x14
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#define Hit_Writeback_I 0x18
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#define Hit_Writeback_D 0x19
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/* 0x1a is unused */
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/*
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* R4000SC and R4400SC-specific cacheops
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*/
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#define Index_Invalidate_SI 0x02
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#define Index_Writeback_Inv_SD 0x03
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#define Index_Load_Tag_SI 0x06
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#define Index_Load_Tag_SD 0x07
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#define Index_Store_Tag_SI 0x0A
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#define Index_Store_Tag_SD 0x0B
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#define Create_Dirty_Excl_SD 0x0f
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#define Hit_Invalidate_SI 0x12
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#define Hit_Invalidate_SD 0x13
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#define Hit_Writeback_Inv_SD 0x17
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#define Hit_Writeback_SD 0x1b
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/* 0x1c is unused */
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/* 0x1e is unused */
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#define Hit_Set_Virtual_SI 0x1e
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#define Hit_Set_Virtual_SD 0x1f
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#endif /* __ASM_MIPS_CACHEOPS_H */
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/*
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* R5000-specific cacheops
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*/
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#define R5K_Page_Invalidate_S 0x17
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/*
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* RM7000-specific cacheops
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*/
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#define Page_Invalidate_T 0x16
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/*
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* R10000-specific cacheops
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*
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* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
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* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
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*/
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#define Index_Writeback_Inv_S 0x03
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#define Index_Load_Tag_S 0x07
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#define Index_Store_Tag_S 0x0B
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#define Hit_Invalidate_S 0x13
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#define Cache_Barrier 0x14
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#define Hit_Writeback_Inv_S 0x17
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#define Index_Load_Data_I 0x18
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#define Index_Load_Data_D 0x19
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#define Index_Load_Data_S 0x1b
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#define Index_Store_Data_I 0x1c
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#define Index_Store_Data_D 0x1d
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#define Index_Store_Data_S 0x1f
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#endif /* __ASM_CACHEOPS_H */
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@ -1,16 +1,15 @@
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/*
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* Various ISA level dependant constants.
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* Various ISA level dependent constants.
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* Most of the following constants reflect the different layout
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* of Coprocessor 0 registers.
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*
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* Copyright (c) 1998 Harald Koerfgen
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*/
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#include <linux/config.h>
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#ifndef __ASM_ISADEP_H
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#define __ASM_ISADEP_H
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#if defined(CONFIG_CPU_R3000)
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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/*
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* R2000 or R3000
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*/
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@ -4,9 +4,9 @@
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* for more details.
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*
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* Copyright (C) 1994 Waldorf GMBH
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PROCESSOR_H
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#define _ASM_PROCESSOR_H
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@ -15,92 +15,26 @@
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#include <asm/isadep.h>
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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#if !defined (_LANGUAGE_ASSEMBLY)
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#if 0
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#include <linux/threads.h>
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#endif
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#include <asm/cachectl.h>
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#include <asm/mipsregs.h>
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#include <asm/reg.h>
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#include <asm/system.h>
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struct mips_cpuinfo {
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unsigned long udelay_val;
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unsigned long *pgd_quick;
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unsigned long *pte_quick;
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unsigned long pgtable_cache_sz;
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};
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/*
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* Return current * instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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/*
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* System setup and hardware flags..
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* XXX: Should go into mips_cpuinfo.
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*/
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extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */
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extern void r3081_wait(void);
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extern void r4k_wait(void);
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extern char cyclecounter_available; /* only available from R4000 upwards. */
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extern void (*cpu_wait)(void);
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extern struct mips_cpuinfo boot_cpu_data;
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extern unsigned int vced_count, vcei_count;
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#ifdef CONFIG_SMP
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extern struct mips_cpuinfo cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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#else
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#define cpu_data &boot_cpu_data
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#define current_cpu_data boot_cpu_data
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#endif
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/*
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* Bus types (default is ISA, but people can check others with these..)
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* MCA_bus hardcoded to 0 for now.
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*
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* This needs to be extended since MIPS systems are being delivered with
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* numerous different types of bus systems.
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*/
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extern int EISA_bus;
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#define MCA_bus 0
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#define MCA_bus__is_a_macro /* for versions in ksyms.c */
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/*
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* MIPS has no problems with write protection
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*/
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#define wp_works_ok 1
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#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
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/* Lazy FPU handling on uni-processor */
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extern struct task_struct *last_task_used_math;
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/*
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* User space process size: 2GB. This is hardcoded into a few places,
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* so don't change it unless you know what you are doing. TASK_SIZE
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* for a 64 bit kernel expandable to 8192EB, of which the current MIPS
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* implementations will "only" be able to use 1TB ...
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*/
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#define TASK_SIZE (0x7fff8000UL)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
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/*
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* Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
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*/
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#define IO_BITMAP_SIZE 32
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#define NUM_FPU_REGS 32
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struct mips_fpu_hard_struct {
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double fp_regs[NUM_FPU_REGS];
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unsigned int control;
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};
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typedef __u64 fpureg_t;
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/*
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* It would be nice to add some more fields for emulator statistics, but there
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@ -108,25 +42,29 @@ struct mips_fpu_hard_struct {
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* be recalculated by hand. So the additional information will be private to
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* the FPU emulator for now. See asm-mips/fpu_emulator.h.
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*/
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typedef u64 fpureg_t;
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struct mips_fpu_soft_struct {
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fpureg_t regs[NUM_FPU_REGS];
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unsigned int sr;
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struct mips_fpu_struct {
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fpureg_t fpr[NUM_FPU_REGS];
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unsigned int fcr31;
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};
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union mips_fpu_union {
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struct mips_fpu_hard_struct hard;
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struct mips_fpu_soft_struct soft;
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};
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#define NUM_DSP_REGS 6
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#define INIT_FPU { \
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{{0,},} \
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}
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typedef __u32 dspreg_t;
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struct mips_dsp_state {
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dspreg_t dspr[NUM_DSP_REGS];
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unsigned int dspcontrol;
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};
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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#define ARCH_MIN_TASKALIGN 8
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struct mips_abi;
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/*
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* If you change thread_struct remember to change the #defines below too!
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*/
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@ -140,131 +78,36 @@ struct thread_struct {
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unsigned long cp0_status;
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/* Saved fpu/fpu emulator stuff. */
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union mips_fpu_union fpu;
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struct mips_fpu_struct fpu;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* Emulated instruction count */
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unsigned long emulated_fp;
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/* Saved per-thread scheduler affinity mask */
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cpumask_t user_cpus_allowed;
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#endif /* CONFIG_MIPS_MT_FPAFF */
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/* Saved state of the DSP ASE, if available. */
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struct mips_dsp_state dsp;
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/* Other stuff associated with the thread. */
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unsigned long cp0_badvaddr; /* Last user fault */
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unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
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unsigned long error_code;
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unsigned long trap_no;
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#define MF_FIXADE 1 /* Fix address errors in software */
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#define MF_LOGADE 2 /* Log address errors to syslog */
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unsigned long mflags;
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mm_segment_t current_ds;
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unsigned long irix_trampoline; /* Wheee... */
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unsigned long irix_oldctx;
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/*
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* These are really only needed if the full FPU emulator is configured.
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* Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the
|
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* fact that having offset.h rebuilt differently for different config
|
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* options would be asking for trouble.
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*
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* Saved EPC during delay-slot emulation (see math-emu/cp1emu.c)
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*/
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unsigned long dsemul_epc;
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/*
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* Pointer to instruction used to induce address error
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*/
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unsigned long dsemul_aerpc;
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struct mips_abi *abi;
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};
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#endif /* !defined (_LANGUAGE_ASSEMBLY) */
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#define INIT_THREAD { \
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/* \
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* saved main processor registers \
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*/ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, \
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/* \
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* saved cp0 stuff \
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*/ \
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0, \
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/* \
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* saved fpu/fpu emulator stuff \
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*/ \
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INIT_FPU, \
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/* \
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* Other stuff associated with the process \
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*/ \
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0, 0, 0, 0, \
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/* \
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* For now the default is to fix address errors \
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*/ \
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MF_FIXADE, { 0 }, 0, 0, \
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/* \
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* dsemul_epc and dsemul_aerpc should never be used uninitialized, \
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* but... \
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*/ \
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0 ,0 \
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}
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#ifdef __KERNEL__
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#define KERNEL_STACK_SIZE 8192
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|
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#if !defined (_LANGUAGE_ASSEMBLY)
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struct task_struct;
|
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|
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/* Free all resources held by a thread. */
|
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#define release_thread(thread) do { } while(0)
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|
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extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
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/* Prepare to copy thread state - unlazy all lazy status */
|
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#define prepare_to_copy(tsk) do { } while (0)
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|
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/* Copy and release all segment info associated with a VM */
|
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#define copy_segments(p, mm) do { } while(0)
|
||||
#define release_segments(mm) do { } while(0)
|
||||
|
||||
/*
|
||||
* Return saved PC of a blocked thread.
|
||||
*/
|
||||
extern inline unsigned long thread_saved_pc(struct thread_struct *t)
|
||||
{
|
||||
extern void ret_from_fork(void);
|
||||
|
||||
/* New born processes are a special case */
|
||||
if (t->reg31 == (unsigned long) ret_from_fork)
|
||||
return t->reg31;
|
||||
|
||||
return ((unsigned long *)t->reg29)[10];
|
||||
}
|
||||
|
||||
/*
|
||||
* Do necessary setup to start up a newly executed thread.
|
||||
*/
|
||||
#define start_thread(regs, new_pc, new_sp) do { \
|
||||
/* New thread looses kernel privileges. */ \
|
||||
regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\
|
||||
regs->cp0_epc = new_pc; \
|
||||
regs->regs[29] = new_sp; \
|
||||
current->thread.current_ds = USER_DS; \
|
||||
} while (0)
|
||||
|
||||
unsigned long get_wchan(struct task_struct *p);
|
||||
|
||||
#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
|
||||
#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
|
||||
#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
|
||||
#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
|
||||
|
||||
/* Allocation and freeing of basic task resources. */
|
||||
/*
|
||||
* NOTE! The task struct and the stack go together
|
||||
*/
|
||||
#define THREAD_SIZE (2*PAGE_SIZE)
|
||||
#define alloc_task_struct() \
|
||||
((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
|
||||
#define free_task_struct(p) free_pages((unsigned long)(p),1)
|
||||
#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
|
||||
|
||||
#define init_task (init_task_union.task)
|
||||
#define init_stack (init_task_union.stack)
|
||||
|
||||
#define cpu_relax() do { } while (0)
|
||||
|
||||
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
|
||||
#endif /* __KERNEL__ */
|
||||
#define cpu_relax() barrier()
|
||||
|
||||
/*
|
||||
* Return_address is a replacement for __builtin_return_address(count)
|
||||
|
|
@ -280,4 +123,20 @@ unsigned long get_wchan(struct task_struct *p);
|
|||
*/
|
||||
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_PREFETCH
|
||||
|
||||
#define ARCH_HAS_PREFETCH
|
||||
|
||||
static inline void prefetch(const void *addr)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" .set mips4 \n"
|
||||
" pref %0, (%1) \n"
|
||||
" .set mips0 \n"
|
||||
:
|
||||
: "i" (Pref_Load), "r" (addr));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_PROCESSOR_H */
|
||||
|
|
|
|||
|
|
@ -3,17 +3,12 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle
|
||||
*
|
||||
* Machine dependent structs and defines to help the user use
|
||||
* the ptrace system call.
|
||||
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
|
||||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_PTRACE_H
|
||||
#define _ASM_PTRACE_H
|
||||
|
||||
#include <asm/isadep.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
|
||||
#define FPR_BASE 32
|
||||
#define PC 64
|
||||
|
|
@ -23,63 +18,69 @@
|
|||
#define MMLO 68
|
||||
#define FPC_CSR 69
|
||||
#define FPC_EIR 70
|
||||
#define DSP_BASE 71 /* 3 more hi / lo register pairs */
|
||||
#define DSP_CONTROL 77
|
||||
#define ACX 78
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
/*
|
||||
* This struct defines the way the registers are stored on the stack during a
|
||||
* system call/exception. As usual the registers k0/k1 aren't being saved.
|
||||
*/
|
||||
struct pt_regs {
|
||||
#ifdef CONFIG_32BIT
|
||||
/* Pad bytes for argument save space on the stack. */
|
||||
unsigned long pad0[6];
|
||||
#endif
|
||||
|
||||
/* Saved main processor registers. */
|
||||
unsigned long regs[32];
|
||||
|
||||
/* Other saved registers. */
|
||||
unsigned long lo;
|
||||
unsigned long hi;
|
||||
|
||||
/*
|
||||
* saved cp0 registers
|
||||
*/
|
||||
unsigned long cp0_epc;
|
||||
unsigned long cp0_badvaddr;
|
||||
/* Saved special registers. */
|
||||
unsigned long cp0_status;
|
||||
unsigned long hi;
|
||||
unsigned long lo;
|
||||
#ifdef CONFIG_CPU_HAS_SMARTMIPS
|
||||
unsigned long acx;
|
||||
#endif
|
||||
unsigned long cp0_badvaddr;
|
||||
unsigned long cp0_cause;
|
||||
};
|
||||
|
||||
#endif /* !(_LANGUAGE_ASSEMBLY) */
|
||||
unsigned long cp0_epc;
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
unsigned long cp0_tcstatus;
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
} __attribute__ ((aligned (8)));
|
||||
|
||||
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
|
||||
/* #define PTRACE_GETREGS 12 */
|
||||
/* #define PTRACE_SETREGS 13 */
|
||||
/* #define PTRACE_GETFPREGS 14 */
|
||||
/* #define PTRACE_SETFPREGS 15 */
|
||||
#define PTRACE_GETREGS 12
|
||||
#define PTRACE_SETREGS 13
|
||||
#define PTRACE_GETFPREGS 14
|
||||
#define PTRACE_SETFPREGS 15
|
||||
/* #define PTRACE_GETFPXREGS 18 */
|
||||
/* #define PTRACE_SETFPXREGS 19 */
|
||||
|
||||
#define PTRACE_SETOPTIONS 21
|
||||
#define PTRACE_OLDSETOPTIONS 21
|
||||
|
||||
/* options set using PTRACE_SETOPTIONS */
|
||||
#define PTRACE_O_TRACESYSGOOD 0x00000001
|
||||
#define PTRACE_GET_THREAD_AREA 25
|
||||
#define PTRACE_SET_THREAD_AREA 26
|
||||
|
||||
#if 0 /* def _LANGUAGE_ASSEMBLY */
|
||||
#include <asm/offset.h>
|
||||
#endif
|
||||
/* Calls to trace a 64bit program from a 32bit program. */
|
||||
#define PTRACE_PEEKTEXT_3264 0xc0
|
||||
#define PTRACE_PEEKDATA_3264 0xc1
|
||||
#define PTRACE_POKETEXT_3264 0xc2
|
||||
#define PTRACE_POKEDATA_3264 0xc3
|
||||
#define PTRACE_GET_THREAD_AREA_3264 0xc4
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
#include <asm/isadep.h>
|
||||
|
||||
/*
|
||||
* Does the process account for user or for system time?
|
||||
*/
|
||||
#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->cp0_epc)
|
||||
|
||||
extern void show_regs(struct pt_regs *);
|
||||
#endif /* !(_LANGUAGE_ASSEMBLY) */
|
||||
#define profile_pc(regs) instruction_pointer(regs)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -7,48 +7,50 @@
|
|||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1995, 1999 by Ralf Baechle
|
||||
* Copyright (C) 1995, 1999 Silicon Graphics
|
||||
*/
|
||||
#ifndef __ASM_MIPS_REG_H
|
||||
#define __ASM_MIPS_REG_H
|
||||
|
||||
/*
|
||||
* This defines/structures correspond to the register layout on stack -
|
||||
* if the order here is changed, it needs to be updated in
|
||||
* include/asm-mips/stackframe.h
|
||||
*/
|
||||
#define EF_REG0 6
|
||||
#define EF_REG1 7
|
||||
#define EF_REG2 8
|
||||
#define EF_REG3 9
|
||||
#define EF_REG4 10
|
||||
#define EF_REG5 11
|
||||
#define EF_REG6 12
|
||||
#define EF_REG7 13
|
||||
#define EF_REG8 14
|
||||
#define EF_REG9 15
|
||||
#define EF_REG10 16
|
||||
#define EF_REG11 17
|
||||
#define EF_REG12 18
|
||||
#define EF_REG13 19
|
||||
#define EF_REG14 20
|
||||
#define EF_REG15 21
|
||||
#define EF_REG16 22
|
||||
#define EF_REG17 23
|
||||
#define EF_REG18 24
|
||||
#define EF_REG19 25
|
||||
#define EF_REG20 26
|
||||
#define EF_REG21 27
|
||||
#define EF_REG22 28
|
||||
#define EF_REG23 29
|
||||
#define EF_REG24 30
|
||||
#define EF_REG25 31
|
||||
#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
|
||||
|
||||
#define EF_R0 6
|
||||
#define EF_R1 7
|
||||
#define EF_R2 8
|
||||
#define EF_R3 9
|
||||
#define EF_R4 10
|
||||
#define EF_R5 11
|
||||
#define EF_R6 12
|
||||
#define EF_R7 13
|
||||
#define EF_R8 14
|
||||
#define EF_R9 15
|
||||
#define EF_R10 16
|
||||
#define EF_R11 17
|
||||
#define EF_R12 18
|
||||
#define EF_R13 19
|
||||
#define EF_R14 20
|
||||
#define EF_R15 21
|
||||
#define EF_R16 22
|
||||
#define EF_R17 23
|
||||
#define EF_R18 24
|
||||
#define EF_R19 25
|
||||
#define EF_R20 26
|
||||
#define EF_R21 27
|
||||
#define EF_R22 28
|
||||
#define EF_R23 29
|
||||
#define EF_R24 30
|
||||
#define EF_R25 31
|
||||
|
||||
/*
|
||||
* k0/k1 unsaved
|
||||
*/
|
||||
#define EF_REG28 34
|
||||
#define EF_REG29 35
|
||||
#define EF_REG30 36
|
||||
#define EF_REG31 37
|
||||
#define EF_R26 32
|
||||
#define EF_R27 33
|
||||
|
||||
#define EF_R28 34
|
||||
#define EF_R29 35
|
||||
#define EF_R30 36
|
||||
#define EF_R31 37
|
||||
|
||||
/*
|
||||
* Saved special registers
|
||||
|
|
@ -59,8 +61,66 @@
|
|||
#define EF_CP0_EPC 40
|
||||
#define EF_CP0_BADVADDR 41
|
||||
#define EF_CP0_STATUS 42
|
||||
#define EF_CP0_CAUSE 44
|
||||
#define EF_CP0_CAUSE 43
|
||||
#define EF_UNUSED0 44
|
||||
|
||||
#define EF_SIZE 180 /* size in bytes */
|
||||
#define EF_SIZE 180
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
||||
#define EF_R0 0
|
||||
#define EF_R1 1
|
||||
#define EF_R2 2
|
||||
#define EF_R3 3
|
||||
#define EF_R4 4
|
||||
#define EF_R5 5
|
||||
#define EF_R6 6
|
||||
#define EF_R7 7
|
||||
#define EF_R8 8
|
||||
#define EF_R9 9
|
||||
#define EF_R10 10
|
||||
#define EF_R11 11
|
||||
#define EF_R12 12
|
||||
#define EF_R13 13
|
||||
#define EF_R14 14
|
||||
#define EF_R15 15
|
||||
#define EF_R16 16
|
||||
#define EF_R17 17
|
||||
#define EF_R18 18
|
||||
#define EF_R19 19
|
||||
#define EF_R20 20
|
||||
#define EF_R21 21
|
||||
#define EF_R22 22
|
||||
#define EF_R23 23
|
||||
#define EF_R24 24
|
||||
#define EF_R25 25
|
||||
|
||||
/*
|
||||
* k0/k1 unsaved
|
||||
*/
|
||||
#define EF_R26 26
|
||||
#define EF_R27 27
|
||||
|
||||
#define EF_R28 28
|
||||
#define EF_R29 29
|
||||
#define EF_R30 30
|
||||
#define EF_R31 31
|
||||
|
||||
/*
|
||||
* Saved special registers
|
||||
*/
|
||||
#define EF_LO 32
|
||||
#define EF_HI 33
|
||||
|
||||
#define EF_CP0_EPC 34
|
||||
#define EF_CP0_BADVADDR 35
|
||||
#define EF_CP0_STATUS 36
|
||||
#define EF_CP0_CAUSE 37
|
||||
|
||||
#define EF_SIZE 304 /* size in bytes */
|
||||
|
||||
#endif /* CONFIG_64BIT */
|
||||
|
||||
#endif /* __ASM_MIPS_REG_H */
|
||||
|
|
|
|||
|
|
@ -1,52 +1,100 @@
|
|||
/*
|
||||
* include/asm-mips/regdefs.h
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994, 1995 by Ralf Baechle
|
||||
* Copyright (C) 1985 MIPS Computer Systems, Inc.
|
||||
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
|
||||
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_REGDEF_H
|
||||
#define _ASM_REGDEF_H
|
||||
|
||||
#ifndef __ASM_MIPS_REGDEF_H
|
||||
#define __ASM_MIPS_REGDEF_H
|
||||
#include <asm/sgidefs.h>
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI32
|
||||
|
||||
/*
|
||||
* Symbolic register names for 32 bit ABI
|
||||
*/
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $1 /* assembler temp - uppercase because of ".set at" */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* caller saved */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* caller saved */
|
||||
#define t9 $25
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel scratch */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $1 /* assembler temp - uppercase because of ".set at" */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* caller saved */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* caller saved */
|
||||
#define t9 $25
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel scratch */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define s8 $30 /* same like fp! */
|
||||
#define ra $31 /* return address */
|
||||
#define ra $31 /* return address */
|
||||
|
||||
#endif /* __ASM_MIPS_REGDEF_H */
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
|
||||
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $at /* assembler temp - uppercase because of ".set at" */
|
||||
#define v0 $2 /* return value - caller saved */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
|
||||
#define ta0 $8
|
||||
#define a5 $9
|
||||
#define ta1 $9
|
||||
#define a6 $10
|
||||
#define ta2 $10
|
||||
#define a7 $11
|
||||
#define ta3 $11
|
||||
#define t0 $12 /* caller saved */
|
||||
#define t1 $13
|
||||
#define t2 $14
|
||||
#define t3 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* caller saved */
|
||||
#define t9 $25 /* callee address for PIC/temp */
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel temporary */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer - caller saved for PIC */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define s8 $30 /* callee saved */
|
||||
#define ra $31 /* return address */
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
|
||||
|
||||
#endif /* _ASM_REGDEF_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $
|
||||
*
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
|
|
@ -10,6 +9,8 @@
|
|||
#ifndef _ASM_TYPES_H
|
||||
#define _ASM_TYPES_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef unsigned short umode_t;
|
||||
|
||||
/*
|
||||
|
|
@ -40,11 +41,17 @@ __extension__ typedef unsigned long long __u64;
|
|||
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* These aren't exported outside the kernel to avoid name space clashes
|
||||
*/
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define BITS_PER_LONG _MIPS_SZLONG
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef __signed char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
|
|
@ -68,9 +75,24 @@ typedef unsigned long long u64;
|
|||
|
||||
#endif
|
||||
|
||||
#define BITS_PER_LONG _MIPS_SZLONG
|
||||
#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
|
||||
|| defined(CONFIG_64BIT)
|
||||
typedef u64 dma_addr_t;
|
||||
#else
|
||||
typedef u32 dma_addr_t;
|
||||
#endif
|
||||
typedef u64 dma64_addr_t;
|
||||
|
||||
typedef unsigned long dma_addr_t;
|
||||
/*
|
||||
* Don't use phys_t. You've been warned.
|
||||
*/
|
||||
#ifdef CONFIG_64BIT_PHYS_ADDR
|
||||
typedef unsigned long long phys_t;
|
||||
#else
|
||||
typedef unsigned long phys_t;
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue