Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,

LS1043A, LS1046A, LS1088A, LS2088A.
 Switch to driver model for SATA on LS1021A and LS1043A.
 Add support for LS1012AFRWY rev C board.
 Enable SMMU for LS1043A.
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Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.

arch/arm/cpu/armv7/ls102xa/Makefile

@@ -10,7 +10,6 @@ obj-y	+= timer.o
 obj-y	+= fsl_epu.o
 obj-y	+= soc.o
 
-obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -73,6 +73,7 @@ static void __secure ls1_deepsleep_irq_cfg(void)
 	 * read, that is why we don't read it from register ippdexpcr1 itself.
 	 */
 	ippdexpcr1 = in_le32(&scfg->sparecr[7]);
+	out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
 
 	if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
 		pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
@@ -192,6 +193,9 @@ static void __secure ls1_deep_sleep(u32 entry_point)
 	setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
 	setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
 
+	/* Disable QE */
+	setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
+
 	ls1_deepsleep_irq_cfg();
 
 	psci_v7_flush_dcache_all();

arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c

@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <ahci.h>
-#include <scsi.h>
-
-/* port register default value */
-#define AHCI_PORT_PHY_1_CFG	0xa003fffe
-#define AHCI_PORT_PHY_2_CFG	0x28183414
-#define AHCI_PORT_PHY_3_CFG	0x0e080e06
-#define AHCI_PORT_PHY_4_CFG	0x064a080b
-#define AHCI_PORT_PHY_5_CFG	0x2aa86470
-#define AHCI_PORT_TRANS_CFG	0x08000029
-
-#define SATA_ECC_REG_ADDR	0x20220520
-#define SATA_ECC_DISABLE	0x00020000
-
-int ls1021a_sata_init(void)
-{
-	struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
-	out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
-#endif
-
-	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
-	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-	out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
-	out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
-	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-
-	ahci_init((void __iomem *)AHCI_BASE_ADDR);
-	scsi_scan(false);
-
-	return 0;
-}

arch/arm/cpu/armv8/fsl-layerscape/Makefile

@@ -29,6 +29,7 @@ endif
 ifneq ($(CONFIG_ARCH_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
+obj-y += icid.o ls1043_ids.o
 endif
 
 ifneq ($(CONFIG_ARCH_LS1012A),)

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -192,6 +192,16 @@ int get_dspi_freq(ulong dummy)
 	return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+	if (!gd->arch.sdhc_clk)
+		get_clocks();
+
+	return gd->arch.sdhc_clk;
+}
+#endif
+
 int get_serial_clock(void)
 {
 	return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
@@ -202,6 +212,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	switch (clk) {
 	case MXC_I2C_CLK:
 		return get_i2c_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+	case MXC_ESDHC_CLK:
+		return get_sdhc_freq(0);
+#endif
 	case MXC_DSPI_CLK:
 		return get_dspi_freq(0);
 	default:

arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c

@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+#include <fsl_sec.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+};
+#endif
+
+struct icid_id_table icid_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
+	SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
+#endif
+
+	SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
+
+	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+	SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
+
+	SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID),
+	SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID),
+	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+	SET_ETR_ICID(FSL_ETR_STREAM_ID),
+	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+	SET_QE_ICID(FSL_QE_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+	SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+	SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
+	SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
+	SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
+	SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
+	SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
+	SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
+	SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
+	SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
+	SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
+	SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct fman_icid_id_table fman_icid_tbl[] = {
+	/* port id, icid */
+	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END),
+};
+
+int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl);
+#endif

arch/arm/cpu/armv8/fsl-layerscape/ppa.c

@@ -99,7 +99,7 @@ int ppa_init(void)
 	cnt = DIV_ROUND_UP(fdt_header_len, 512);
 	debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
 	      __func__, dev, blk, cnt);
-	ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp);
+	ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp);
 	if (ret != cnt) {
 		free(fitp);
 		printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
@@ -123,7 +123,7 @@ int ppa_init(void)
 
 	blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9;
 	cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512);
-	ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, ppa_hdr_ddr);
+	ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_hdr_ddr);
 	if (ret != cnt) {
 		free(ppa_hdr_ddr);
 		printf("MMC/SD read of PPA header failed\n");
@@ -149,8 +149,7 @@ int ppa_init(void)
 	cnt = DIV_ROUND_UP(fw_length, 512);
 	debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
 	      __func__, dev, blk, cnt);
-	ret = mmc->block_dev.block_read(&mmc->block_dev,
+	ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr);
-					blk, cnt, ppa_fit_addr);
 	if (ret != cnt) {
 		free(ppa_fit_addr);
 		printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -634,7 +634,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a008997();
 	erratum_a009007();
 
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	set_icids();
 #endif
 }

arch/arm/dts/fsl-ls1043a-qds.dtsi

@@ -174,3 +174,7 @@
 &lpuart0 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};

arch/arm/dts/fsl-ls1043a.dtsi

@@ -70,6 +70,14 @@
 			status = "disabled";
 		};
 
+		esdhc: esdhc@1560000 {
+			compatible = "fsl,esdhc";
+			reg = <0x0 0x1560000 0x0 0x10000>;
+			interrupts = <0 62 0x4>;
+			big-endian;
+			bus-width = <4>;
+		};
+
 		ifc: ifc@1530000 {
 			compatible = "fsl,ifc", "simple-bus";
 			reg = <0x0 0x1530000 0x0 0x10000>;
@@ -279,5 +287,13 @@
 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
+
+		sata: sata@3200000 {
+			compatible = "fsl,ls1043a-ahci";
+			reg = <0x0 0x3200000 0x0 0x10000>;
+			interrupts = <0 69 4>;
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
 	};
 };

arch/arm/dts/fsl-ls1046a.dtsi

@@ -70,6 +70,14 @@
 			status = "disabled";
 		};
 
+		esdhc: esdhc@1560000 {
+			compatible = "fsl,esdhc";
+			reg = <0x0 0x1560000 0x0 0x10000>;
+			interrupts = <0 62 0x4>;
+			big-endian;
+			bus-width = <4>;
+		};
+
 		ifc: ifc@1530000 {
 			compatible = "fsl,ifc", "simple-bus";
 			reg = <0x0 0x1530000 0x0 0x10000>;

arch/arm/dts/fsl-ls1088a.dtsi

@@ -74,6 +74,15 @@
 		reg-names = "QuadSPI", "QuadSPI-memory";
 		num-cs = <4>;
 	};
+
+	esdhc: esdhc@2140000 {
+		compatible = "fsl,esdhc";
+		reg = <0x0 0x2140000 0x0 0x10000>;
+		interrupts = <0 28 0x4>; /* Level high type */
+		little-endian;
+		bus-width = <4>;
+	};
+
 	ifc: ifc@1530000 {
 		compatible = "fsl,ifc", "simple-bus";
 		reg = <0x0 0x2240000 0x0 0x20000>;

arch/arm/dts/fsl-ls2080a.dtsi

@@ -75,6 +75,14 @@
 		num-cs = <4>;
 	};
 
+	esdhc: esdhc@0 {
+		compatible = "fsl,esdhc";
+		reg = <0x0 0x2140000 0x0 0x10000>;
+		interrupts = <0 28 0x4>; /* Level high type */
+		little-endian;
+		bus-width = <4>;
+	};
+
 	usb0: usb3@3100000 {
 		compatible = "fsl,layerscape-dwc3";
 		reg = <0x0 0x3100000 0x0 0x10000>;

arch/arm/dts/ls1021a-qds.dtsi

@@ -212,3 +212,7 @@
 &uart1 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};

arch/arm/dts/ls1021a-twr.dtsi

@@ -103,3 +103,7 @@
 &uart1 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};

arch/arm/dts/ls1021a.dtsi

@@ -96,7 +96,6 @@
 			sdhci,auto-cmd12;
 			big-endian;
 			bus-width = <4>;
-			status = "disabled";
 		};
 
 		scfg: scfg@1570000 {
@@ -404,5 +403,12 @@
 			ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
 		};
+
+		sata: sata@3200000 {
+			compatible = "fsl,ls1021a-ahci";
+			reg = <0x3200000 0x10000>;
+			interrupts = <0 101 4>;
+			status = "disabled";
+		};
 	};
 };

arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -195,6 +195,7 @@
 /* SoC related */
 #ifdef CONFIG_ARCH_LS1043A
 #define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN			1
 #define CONFIG_SYS_NUM_FM1_DTSEC		7
 #define CONFIG_SYS_NUM_FM1_10GEC		1

arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h

@@ -68,6 +68,10 @@ void fdt_fixup_icid(void *blob);
 #define SET_DEBUG_ICID(streamid) \
 	SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
 
+#define SET_QE_ICID(streamid) \
+	SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
+		QE_BASE_ADDR)
+
 #define SET_QMAN_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
 		offsetof(struct ccsr_qman, liodnr) + \

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

@@ -85,6 +85,8 @@
 #define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1320000)
 #define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1330000)
 
+#define QE_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1400000)
+
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 
 #define EDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01c00000)

arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h

@@ -35,6 +35,9 @@
  *  -DPAA2
  *     -u-boot will allocate a range of stream IDs to be used by the Management
  *      Complex for containers and will set these values in the MC DPC image.
+ *     -u-boot will fixup the iommu-map property in the fsl-mc node in the
+ *      device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
+ *      for more info on the msi-map definition)
  *     -the MC is responsible for allocating and setting up 'isolation context
  *      IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
  *

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

@@ -86,6 +86,8 @@ struct sys_info {
 	unsigned long freq_localbus;
 };
 
+#define CCSR_DEVDISR1_QE	0x00000001
+
 /* Device Configuration and Pin Control */
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
@@ -389,33 +391,6 @@ struct ccsr_serdes {
 	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
 };
 
-
-
-/* AHCI (sata) register map */
-struct ccsr_ahci {
-	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
-	u32 pcfg;	/* port config */
-	u32 ppcfg;	/* port phy1 config */
-	u32 pp2c;	/* port phy2 config */
-	u32 pp3c;	/* port phy3 config */
-	u32 pp4c;	/* port phy4 config */
-	u32 pp5c;	/* port phy5 config */
-	u32 paxic;	/* port AXI config */
-	u32 axicc;	/* AXI cache control */
-	u32 axipc;	/* AXI PROT control */
-	u32 ptc;	/* port Trans Config */
-	u32 pts;	/* port Trans Status */
-	u32 plc;	/* port link config */
-	u32 plc1;	/* port link config1 */
-	u32 plc2;	/* port link config2 */
-	u32 pls;	/* port link status */
-	u32 pls1;	/* port link status1 */
-	u32 pcmdc;	/* port CMD config */
-	u32 ppcs;	/* port phy control status */
-	u32 pberr;	/* port 0/1 BIST error */
-	u32 cmds;	/* port 0/1 CMD status error */
-};
-
 #define RCPM_POWMGTCSR			0x130
 #define RCPM_POWMGTCSR_SERDES_PW	0x80000000
 #define RCPM_POWMGTCSR_LPM20_REQ	0x00100000

arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_SATA_H_
-#define __FSL_SATA_H_
-
-int ls1021a_sata_init(void);
-#endif

board/freescale/ls1012afrdm/ls1012afrdm.c

@@ -24,11 +24,15 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static inline int get_board_version(void)
 {
-	struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+	uint32_t val;
-	int val;
+#ifdef CONFIG_TARGET_LS1012AFRDM
+	val = 0;
+#else
+	struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
 
-	val = in_be32(&pgpio->gpdat);
+	val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
 
+#endif
 	return val;
 }
 
@@ -46,11 +50,11 @@ int checkboard(void)
 	puts("Version");
 
 	switch (rev) {
-	case BOARD_REV_A:
+	case BOARD_REV_A_B:
-		puts(": RevA ");
+		puts(": RevA/B ");
 		break;
-	case BOARD_REV_B:
+	case BOARD_REV_C:
-		puts(": RevB ");
+		puts(": RevC ");
 		break;
 	default:
 		puts(": unknown");
@@ -100,7 +104,7 @@ int dram_init(void)
 #ifdef CONFIG_TARGET_LS1012AFRWY
 	board_rev = get_board_version();
 
-	if (board_rev & BOARD_REV_B) {
+	if (board_rev == BOARD_REV_C) {
 		mparam.mdctl = 0x05180000;
 		gd->ram_size = SYS_SDRAM_SIZE_1024;
 	} else {

board/freescale/ls1021aiot/ls1021aiot.c

@@ -11,7 +11,6 @@
 
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_soc.h>
-#include <asm/arch/ls102xa_sata.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_immap.h>
@@ -206,10 +205,6 @@ int board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-#ifdef CONFIG_SCSI_AHCI_PLAT
-	ls1021a_sata_init();
-#endif
-
 	return 0;
 }
 #endif

board/freescale/ls1021aqds/ls1021aqds.c

@@ -11,7 +11,6 @@
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_devdis.h>
-#include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_csu.h>
@@ -362,9 +361,6 @@ int config_serdes_mux(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-#ifdef CONFIG_SCSI_AHCI_PLAT
-	ls1021a_sata_init();
-#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 	fsl_setenv_chain_of_trust();
 #endif

board/freescale/ls1021atwr/ls1021atwr.c

@@ -11,7 +11,6 @@
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_soc.h>
-#include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_csu.h>
@@ -556,9 +555,6 @@ void spl_board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-#ifdef CONFIG_SCSI_AHCI_PLAT
-	ls1021a_sata_init();
-#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 	fsl_setenv_chain_of_trust();
 #endif

board/freescale/ls1043aqds/ls1043aqds.c

@@ -14,6 +14,7 @@
 #include <asm/arch/fdt.h>
 #include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include <ahci.h>
 #include <hwconfig.h>
 #include <mmc.h>
@@ -353,6 +354,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_board_enet(blob);
 #endif
 
+	fdt_fixup_icid(blob);
+
 	reg = QIXIS_READ(brdcfg[0]);
 	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 

board/freescale/ls1043ardb/ls1043ardb.c

@@ -9,6 +9,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include <fdt_support.h>
 #include <hwconfig.h>
 #include <ahci.h>
@@ -177,6 +178,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_fman_ethernet(blob);
 #endif
 
+	fdt_fixup_icid(blob);
+
 	/*
 	 * qe-hdlc and usb multi-use the pins,
 	 * when set hwconfig to qe-hdlc, delete usb node.

board/freescale/ls1088a/ls1088a.c

@@ -575,6 +575,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
 
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
 	fsl_fdt_fixup_flash(blob);
 
 #ifdef CONFIG_FSL_MC_ENET

board/freescale/ls2080a/ls2080a.c

@@ -127,6 +127,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	fdt_fixup_board_enet(blob);
 #endif

board/freescale/ls2080aqds/ls2080aqds.c

@@ -332,6 +332,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
 	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)

board/freescale/ls2080ardb/ls2080ardb.c

@@ -394,6 +394,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
 	fsl_fdt_fixup_dr_usb(blob, bd);
 
 	fsl_fdt_fixup_flash(blob);

configs/ls1021atwr_nor_SECURE_BOOT_defconfig

@@ -50,3 +50,5 @@ CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1021atwr_nor_defconfig

@@ -50,3 +50,10 @@ CONFIG_USB_STORAGE=y
 CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y

configs/ls1021atwr_nor_lpuart_defconfig

@@ -51,3 +51,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1021atwr_qspi_defconfig

@@ -57,3 +57,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1021atwr_sdcard_ifc_defconfig

@@ -61,3 +61,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1021atwr_sdcard_qspi_defconfig

@@ -67,3 +67,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043aqds_defconfig

@@ -47,3 +47,10 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y

configs/ls1043aqds_lpuart_defconfig

@@ -49,3 +49,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043aqds_nand_defconfig

@@ -62,3 +62,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043aqds_nor_ddr3_defconfig

@@ -48,3 +48,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043aqds_qspi_defconfig

@@ -46,3 +46,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043aqds_sdcard_ifc_defconfig

@@ -62,3 +62,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043aqds_sdcard_qspi_defconfig

@@ -59,3 +59,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043ardb_SECURE_BOOT_defconfig

@@ -45,3 +45,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043ardb_defconfig

@@ -43,3 +43,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043ardb_nand_SECURE_BOOT_defconfig

@@ -62,3 +62,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043ardb_nand_defconfig

@@ -60,3 +60,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1043ardb_sdcard_defconfig

@@ -58,3 +58,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046aqds_SECURE_BOOT_defconfig

@@ -49,3 +49,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046aqds_defconfig

@@ -49,3 +49,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046aqds_lpuart_defconfig

@@ -51,3 +51,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046aqds_nand_defconfig

@@ -56,3 +56,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046aqds_qspi_defconfig

@@ -49,3 +49,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046aqds_sdcard_ifc_defconfig

@@ -65,3 +65,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046aqds_sdcard_qspi_defconfig

@@ -64,3 +64,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046ardb_emmc_defconfig

@@ -60,3 +60,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

@@ -46,3 +46,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046ardb_qspi_defconfig

@@ -46,3 +46,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1046ardb_sdcard_defconfig

@@ -59,3 +59,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088aqds_defconfig

@@ -47,3 +47,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088aqds_qspi_SECURE_BOOT_defconfig

@@ -54,3 +54,5 @@ CONFIG_USB_GADGET=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088aqds_qspi_defconfig

@@ -52,3 +52,5 @@ CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088aqds_sdcard_ifc_defconfig

@@ -55,3 +55,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088aqds_sdcard_qspi_defconfig

@@ -61,3 +61,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088ardb_qspi_SECURE_BOOT_defconfig

@@ -55,3 +55,5 @@ CONFIG_USB_GADGET=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088ardb_qspi_defconfig

@@ -53,3 +53,5 @@ CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls1088ardb_sdcard_qspi_defconfig

@@ -62,3 +62,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080a_emu_defconfig

@@ -33,3 +33,5 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080a_simu_defconfig

@@ -36,3 +36,5 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080aqds_SECURE_BOOT_defconfig

@@ -54,3 +54,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080aqds_defconfig

@@ -53,3 +53,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080aqds_nand_defconfig

@@ -62,3 +62,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080aqds_qspi_defconfig

@@ -53,3 +53,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080aqds_sdcard_defconfig

@@ -60,3 +60,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080ardb_SECURE_BOOT_defconfig

@@ -55,3 +55,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080ardb_defconfig

@@ -54,3 +54,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2080ardb_nand_defconfig

@@ -58,3 +58,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2088ardb_qspi_SECURE_BOOT_defconfig

@@ -53,3 +53,5 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

configs/ls2088ardb_qspi_defconfig

@@ -55,3 +55,5 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y

drivers/Kconfig

@@ -74,6 +74,8 @@ source "drivers/power/Kconfig"
 
 source "drivers/pwm/Kconfig"
 
+source "drivers/qe/Kconfig"
+
 source "drivers/ram/Kconfig"
 
 source "drivers/remoteproc/Kconfig"

drivers/ata/sata_ceva.c

@@ -81,13 +81,24 @@
 #define CEVA_TRANS_CFG	0x08000029
 #define CEVA_AXICC_CFG	0x3fffffff
 
+/* for ls1021a */
+#define LS1021_AHCI_VEND_AXICC 0xC0
+#define LS1021_CEVA_PHY2_CFG	0x28183414
+#define LS1021_CEVA_PHY3_CFG	0x0e080e06
+#define LS1021_CEVA_PHY4_CFG	0x064a080b
+#define LS1021_CEVA_PHY5_CFG	0x2aa86470
+
 /* ecc addr-val pair */
 #define ECC_DIS_ADDR_CH2	0x80000000
-#define ECC_DIS_VAL_CH2	0x20140520
+#define ECC_DIS_VAL_CH2		0x20140520
+#define SATA_ECC_REG_ADDR	0x20220520
+#define SATA_ECC_DISABLE	0x00020000
 
 enum ceva_soc {
 	CEVA_1V84,
 	CEVA_LS1012A,
+	CEVA_LS1021A,
+	CEVA_LS1043A,
 };
 
 struct ceva_sata_priv {
@@ -113,7 +124,20 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
 		writel(tmp, base + AHCI_VEND_PTC);
 		break;
 
+	case CEVA_LS1021A:
+		writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
+		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+		writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
+		writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
+		writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
+		writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
+		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+		if (priv->flag & FLAG_COHERENT)
+			writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
+		break;
+
 	case CEVA_LS1012A:
+	case CEVA_LS1043A:
 		writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
 		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
 		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
@@ -144,6 +168,8 @@ static int sata_ceva_probe(struct udevice *dev)
 static const struct udevice_id sata_ceva_ids[] = {
 	{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
 	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
+	{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
+	{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
 	{ }
 };
 

drivers/misc/fsl_portals.c

@@ -49,7 +49,7 @@ void setup_qbman_portals(void)
 		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
 	}
 #else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	int i;
 
 	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
@@ -197,7 +197,7 @@ void fdt_fixup_qportals(void *blob)
 	char compat[64];
 	int compat_len;
 
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	int smmu_ph = fdt_get_smmu_phandle(blob);
 #endif
 
@@ -211,7 +211,8 @@ void fdt_fixup_qportals(void *blob)
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
 	while (off != -FDT_ERR_NOTFOUND) {
-#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1043A) || \
+defined(CONFIG_ARCH_LS1046A)
 #ifdef CONFIG_FSL_CORENET
 		u32 liodns[2];
 #endif
@@ -226,7 +227,7 @@ void fdt_fixup_qportals(void *blob)
 		int j;
 #endif
 
-#endif /* CONFIG_PPC || CONFIG_ARCH_LS1046A */
+#endif /* CONFIG_PPC || CONFIG_ARCH_LS1043A || CONFIG_ARCH_LS1046A */
 		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
 		if (err < 0)
 			goto err;
@@ -275,7 +276,7 @@ void fdt_fixup_qportals(void *blob)
 			goto err;
 #endif
 #else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 		if (smmu_ph >= 0) {
 			u32 icids[3];
 

drivers/net/fm/fm.c

@@ -402,7 +402,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 		printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
 				dev, blk, cnt);
 		mmc_init(mmc);
-		(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+		(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
 						addr);
 	}
 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)

drivers/net/fm/init.c

@@ -328,7 +328,8 @@ void fdt_fixup_fman_ethernet(void *blob)
 				ft_fixup_port(blob, &fm_info[i],
 					      "fsl,fman-1g-mac");
 		} else {
-			if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
+			if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec") &&
+			    ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
 				ft_fixup_port(blob, &fm_info[i],
 					      "fsl,fman-10g-mac");
 		}

drivers/net/fsl-mc/mc.c

@@ -2,6 +2,7 @@
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  */
 #include <common.h>
 #include <errno.h>
@@ -29,6 +30,7 @@
 #define MC_BOOT_ENV_VAR		"mcinitcmd"
 
 DECLARE_GLOBAL_DATA_PTR;
+static int mc_memset_resv_ram;
 static int mc_boot_status = -1;
 static int mc_dpl_applied = -1;
 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
@@ -278,6 +280,40 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
 				 MC_FIXUP_DPL);
 }
 
+void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
+{
+	u32 *prop;
+	u32 iommu_map[4];
+	int offset;
+	int lenp;
+
+	/* find fsl-mc node */
+	offset = fdt_path_offset(blob, "/soc/fsl-mc");
+	if (offset < 0)
+		offset = fdt_path_offset(blob, "/fsl-mc");
+	if (offset < 0) {
+		printf("%s: fsl-mc: ERR: fsl-mc node not found in DT, err %d\n",
+		       __func__, offset);
+		return;
+	}
+
+	prop = fdt_getprop_w(blob, offset, "iommu-map", &lenp);
+	if (!prop) {
+		debug("%s: fsl-mc: ERR: missing iommu-map in fsl-mc bus node\n",
+		      __func__);
+		return;
+	}
+
+	iommu_map[0] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
+	iommu_map[1] = *++prop;
+	iommu_map[2] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
+	iommu_map[3] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_END -
+		FSL_DPAA2_STREAM_ID_START + 1);
+
+	fdt_setprop_inplace(blob, offset, "iommu-map",
+			    iommu_map, sizeof(iommu_map));
+}
+
 static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
 				 struct eth_device *eth_dev)
 {
@@ -810,6 +846,11 @@ u64 mc_get_dram_addr(void)
 {
 	size_t mc_ram_size = mc_get_dram_block_size();
 
+	if (!mc_memset_resv_ram || (get_mc_boot_status() < 0)) {
+		mc_memset_resv_ram = 1;
+		memset((void *)gd->arch.resv_ram, 0, mc_ram_size);
+	}
+
 	return (gd->arch.resv_ram + mc_ram_size - 1) &
 		MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
 }

drivers/net/pfe_eth/pfe_mdio.c

@@ -162,7 +162,6 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv)
 	if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
 		sgmii_2500 = 1;
 
-	printf("%s %d\n", __func__, priv->gemac_port);
 
 	/* PCS configuration done with corresponding GEMAC */
 	bus.priv = gem_info[priv->gemac_port].gemac_base;

drivers/qe/Kconfig

@@ -0,0 +1,12 @@
+#
+# QUICC Engine Drivers
+#
+config U_QE
+	bool "Enable support for U QUICC Engine"
+	default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \
+		|| (TARGET_T1024QDS) \
+		|| (TARGET_T1024RDB) \
+		|| (TARGET_T1040QDS && !NOBQFMAN) \
+		|| (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT)
+	help
+	  Choose this option to add support for U QUICC Engine.

drivers/qe/qe.c

@@ -218,7 +218,7 @@ void u_qe_init(void)
 		printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
 		       dev, blk, cnt);
 		mmc_init(mmc);
-		(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+		(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
 						addr);
 	}
 #endif

include/configs/T102xQDS.h

@@ -659,7 +659,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_DPAA_FMAN
 
 #define CONFIG_QE
-#define CONFIG_U_QE
 /* Default address of microcode for the Linux FMan driver */
 #if defined(CONFIG_SPIFLASH)
 /*

include/configs/T102xRDB.h

@@ -669,7 +669,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_TARGET_T1024RDB
 #define CONFIG_QE
-#define CONFIG_U_QE
 #endif
 /* Default address of microcode for the Linux FMan driver */
 #if defined(CONFIG_SPIFLASH)

include/configs/T1040QDS.h

@@ -549,7 +549,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_DPAA_PME
 
 #define CONFIG_QE
-#define CONFIG_U_QE
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*

include/configs/ls1012afrwy.h

@@ -9,9 +9,9 @@
 #include "ls1012a_common.h"
 
 /* Board Rev*/
-#define BOARD_REV_A			0x0
+#define BOARD_REV_A_B			0x0
-#define BOARD_REV_B			0x200
+#define BOARD_REV_C			0x00080000
-
+#define BOARD_REV_MASK			0x001A0000
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1

include/configs/ls1021aqds.h

@@ -107,7 +107,6 @@ unsigned long get_board_ddr_clk(void);
 
 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 	!defined(CONFIG_QSPI_BOOT)
-#define CONFIG_U_QE
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #endif
 

include/configs/ls1021atwr.h

@@ -106,7 +106,6 @@
 
 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 	!defined(CONFIG_QSPI_BOOT)
-#define CONFIG_U_QE
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #endif
 

include/configs/ls1043ardb.h

@@ -268,13 +268,6 @@
 #endif
 #endif
 
-/* QE */
-#ifndef SPL_NO_QE
-#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
-#define CONFIG_U_QE
-#endif
-#endif
-
 /* SATA */
 #ifndef SPL_NO_SATA
 #ifndef CONFIG_CMD_EXT2

include/configs/ls1088ardb.h

@@ -455,8 +455,7 @@
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
-	func(SCSI, scsi, 0) \
+	func(SCSI, scsi, 0)
-	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #endif
 

include/configs/ls2080ardb.h

@@ -323,8 +323,7 @@ unsigned long get_board_sys_clk(void);
 #define BOOT_TARGET_DEVICES(func) \
 	func(USB, usb, 0) \
 	func(MMC, mmc, 0) \
-	func(SCSI, scsi, 0) \
+	func(SCSI, scsi, 0)
-	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 
 #ifdef CONFIG_QSPI_BOOT

include/fsl-mc/fsl_mc.h

@@ -51,6 +51,7 @@ struct mc_ccsr_registers {
 	u32 reg_error[];
 };
 
+void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
 int get_mc_boot_status(void);
 int get_dpl_apply_status(void);
 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET