mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
[Blackfin][PATCH] Add BF537 stamp board support
This commit is contained in:
parent
0d93de1144
commit
26bf7deca3
45 changed files with 12299 additions and 1 deletions
2
MAKEALL
2
MAKEALL
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@ -317,7 +317,7 @@ LIST_avr32="atstk1002"
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#########################################################################
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LIST_blackfin=" \
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bf533-ezkit bf533-stamp \
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bf533-ezkit bf533-stamp bf537-stamp \
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"
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#-----------------------------------------------------------------------
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8
Makefile
8
Makefile
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@ -180,6 +180,10 @@ ifeq ($(CPU),bf533)
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OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
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OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
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endif
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ifeq ($(CPU),bf537)
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OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
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OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
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endif
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OBJS := $(addprefix $(obj),$(OBJS))
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@ -2356,6 +2360,9 @@ bf533-ezkit_config: unconfig
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bf533-stamp_config: unconfig
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@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp
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bf537-stamp_config: unconfig
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@$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp
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#========================================================================
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# AVR32
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#========================================================================
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@ -2392,6 +2399,7 @@ clean:
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rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
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rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
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rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
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rm -f $(obj)board/bf537-stamp/u-boot.lds
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rm -f $(obj)include/bmp_logo.h
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rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
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58
board/bf537-stamp/Makefile
Normal file
58
board/bf537-stamp/Makefile
Normal file
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@ -0,0 +1,58 @@
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2007 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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u-boot.lds: u-boot.lds.S
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$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
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mv -f $@.tmp $@
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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437
board/bf537-stamp/bf537-stamp.c
Normal file
437
board/bf537-stamp/bf537-stamp.c
Normal file
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@ -0,0 +1,437 @@
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/*
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* U-boot - BF537.c
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*
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* Copyright (c) 2005 blackfin.uclinux.org
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <command.h>
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#include <asm/blackfin.h>
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#include <asm/io.h>
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#include "ether_bf537.h"
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#define POST_WORD_ADDR 0xFF903FFC
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/*
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* the bootldr command loads an address, checks to see if there
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* is a Boot stream that the on-chip BOOTROM can understand,
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* and loads it via the BOOTROM Callback. It is possible
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* to also add booting from SPI, or TWI, but this function does
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* not currently support that.
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*/
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int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr, entry;
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ulong *data;
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/* Get the address */
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if (argc < 2) {
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addr = load_addr;
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} else {
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addr = simple_strtoul(argv[1], NULL, 16);
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}
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/* Check if it is a LDR file */
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data = (ulong *) addr;
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if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) {
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/* We want to boot from FLASH or SDRAM */
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entry = _BOOTROM_BOOT_DXE_FLASH;
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printf("## Booting ldr image at 0x%08lx ...\n", addr);
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if (icache_status())
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icache_disable();
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if (dcache_status())
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dcache_disable();
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__asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n":
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:[a] "d"(addr),[b] "a"(entry)
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:"R7", "P0");
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} else {
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printf("## No ldr image at address 0x%08lx\n", addr);
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}
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return 0;
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}
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U_BOOT_CMD(bootldr, 2, 0, do_bootldr,
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"bootldr - boot ldr image from memory\n",
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"[addr]\n - boot ldr image stored in memory\n");
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int checkboard(void)
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{
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#if (BFIN_CPU == ADSP_BF534)
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printf("CPU: ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28);
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#elif (BFIN_CPU == ADSP_BF536)
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printf("CPU: ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28);
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#else
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printf("CPU: ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28);
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#endif
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printf("Board: ADI BF537 stamp board\n");
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printf(" Support: http://blackfin.uclinux.org/\n");
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return 0;
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}
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#if defined(CONFIG_BFIN_IDE)
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void cf_outb(unsigned char val, volatile unsigned char *addr)
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{
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*(addr) = val;
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sync();
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}
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unsigned char cf_inb(volatile unsigned char *addr)
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{
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volatile unsigned char c;
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c = *(addr);
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sync();
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return c;
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}
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void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
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{
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int i;
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for (i = 0; i < words; i++)
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*(sect_buf + i) = *(addr);
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sync();
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}
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void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
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{
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int i;
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for (i = 0; i < words; i++)
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*(addr) = *(sect_buf + i);
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sync();
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}
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#endif /* CONFIG_BFIN_IDE */
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long int initdram(int board_type)
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{
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef DEBUG
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int brate;
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char *tmp = getenv("baudrate");
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brate = simple_strtoul(tmp, NULL, 16);
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printf("Serial Port initialized with Baud rate = %x\n", brate);
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printf("SDRAM attributes:\n");
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printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
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"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
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3, 3, 6, 2, 3);
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printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
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printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
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#endif
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gd->bd->bi_memstart = CFG_SDRAM_BASE;
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gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
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return CFG_MAX_RAM_SIZE;
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}
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#if defined(CONFIG_MISC_INIT_R)
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/* miscellaneous platform dependent initialisations */
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int misc_init_r(void)
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{
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#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
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char nid[32];
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unsigned char *pMACaddr = (unsigned char *)0x203F0000;
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u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
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#if (CONFIG_COMMANDS & CFG_CMD_NET)
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/* The 0xFF check here is to make sure we don't use the address
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* in flash if it's simply been erased (aka all 0xFF values) */
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if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
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sprintf(nid, "%02x:%02x:%02x:%02x:%02x:%02x",
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pMACaddr[0], pMACaddr[1],
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pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
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setenv("ethaddr", nid);
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}
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if (getenv("ethaddr")) {
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SetupMacAddr(SrcAddr);
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}
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#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
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#endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
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#if defined(CONFIG_BFIN_IDE)
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#if defined(CONFIG_BFIN_TRUE_IDE)
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/* Enable ATASEL when in True IDE mode */
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printf("Using CF True IDE Mode\n");
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cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
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udelay(1000);
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#elif defined(CONFIG_BFIN_CF_IDE)
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/* Disable ATASEL when we're in Common Memory Mode */
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printf("Using CF Common Memory Mode\n");
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cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
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udelay(1000);
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#elif defined(CONFIG_BFIN_HDD_IDE)
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printf("Using HDD IDE Mode\n");
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#endif
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ide_init();
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#endif /* CONFIG_BFIN_IDE */
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return 0;
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}
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#endif /* CONFIG_MISC_INIT_R */
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#ifdef CONFIG_POST
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#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
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/* Using sw10-PF5 as the hotkey */
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int post_hotkeys_pressed(void)
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{
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return 0;
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}
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#else
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/* Using sw10-PF5 as the hotkey */
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int post_hotkeys_pressed(void)
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{
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int delay = 3;
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int i;
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unsigned short value;
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*pPORTF_FER &= ~PF5;
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*pPORTFIO_DIR &= ~PF5;
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*pPORTFIO_INEN |= PF5;
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printf("########Press SW10 to enter Memory POST########: %2d ", delay);
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while (delay--) {
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for (i = 0; i < 100; i++) {
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value = *pPORTFIO & PF5;
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if (value != 0) {
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break;
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}
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udelay(10000);
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}
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printf("\b\b\b%2d ", delay);
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}
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printf("\b\b\b 0");
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printf("\n");
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if (value == 0)
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return 0;
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else {
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printf("Hotkey has been pressed, Enter POST . . . . . .\n");
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return 1;
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}
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}
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#endif
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#endif
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#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
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void post_word_store(ulong a)
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{
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volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
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*save_addr = a;
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}
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ulong post_word_load(void)
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{
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volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
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return *save_addr;
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}
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#endif
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#ifdef CONFIG_POST
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int uart_post_test(int flags)
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{
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return 0;
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}
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#define BLOCK_SIZE 0x10000
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#define VERIFY_ADDR 0x2000000
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extern int erase_block_flash(int);
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extern int write_data(long lStart, long lCount, uchar * pnData);
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int flash_post_test(int flags)
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{
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unsigned short *pbuf, *temp;
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int offset, n, i;
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int value = 0;
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int result = 0;
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printf("\n");
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pbuf = (unsigned short *)VERIFY_ADDR;
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temp = pbuf;
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for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
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offset = (n - 7) * BLOCK_SIZE;
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printf("--------Erase block:%2d..", n);
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erase_block_flash(n);
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printf("OK\r");
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printf("--------Program block:%2d...", n);
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write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
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printf("OK\r");
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printf("--------Verify block:%2d...", n);
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for (i = 0; i < BLOCK_SIZE; i += 2) {
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if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
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*temp++) {
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value = 1;
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result = 1;
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}
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}
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if (value)
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printf("failed\n");
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else
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printf("OK %3d%%\r",
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(int)(
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(n + 1 -
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FLASH_START_POST_BLOCK) *
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100 / (FLASH_END_POST_BLOCK -
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FLASH_START_POST_BLOCK)));
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temp = pbuf;
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value = 0;
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}
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printf("\n");
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if (result)
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return -1;
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else
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return 0;
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}
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/****************************************************
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* LED1 ---- PF6 LED2 ---- PF7 *
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* LED3 ---- PF8 LED4 ---- PF9 *
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* LED5 ---- PF10 LED6 ---- PF11 *
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****************************************************/
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int led_post_test(int flags)
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{
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*pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
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*pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
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*pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
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*pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
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udelay(1000000);
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printf("LED1 on");
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*pPORTFIO |= PF6;
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udelay(1000000);
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printf("\b\b\b\b\b\b\b");
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printf("LED2 on");
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*pPORTFIO |= PF7;
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udelay(1000000);
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printf("\b\b\b\b\b\b\b");
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printf("LED3 on");
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*pPORTFIO |= PF8;
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udelay(1000000);
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printf("\b\b\b\b\b\b\b");
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printf("LED4 on");
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*pPORTFIO |= PF9;
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udelay(1000000);
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printf("\b\b\b\b\b\b\b");
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printf("LED5 on");
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*pPORTFIO |= PF10;
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udelay(1000000);
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printf("\b\b\b\b\b\b\b");
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printf("lED6 on");
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*pPORTFIO |= PF11;
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printf("\b\b\b\b\b\b\b ");
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return 0;
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}
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/************************************************
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* SW10 ---- PF5 SW11 ---- PF4 *
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* SW12 ---- PF3 SW13 ---- PF2 *
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************************************************/
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int button_post_test(int flags)
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{
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int i, delay = 5;
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unsigned short value = 0;
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int result = 0;
|
||||
|
||||
*pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
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||||
*pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
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*pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
|
||||
|
||||
printf("\n--------Press SW10: %2d ", delay);
|
||||
while (delay--) {
|
||||
for (i = 0; i < 100; i++) {
|
||||
value = *pPORTFIO & PF5;
|
||||
if (value != 0) {
|
||||
break;
|
||||
}
|
||||
udelay(10000);
|
||||
}
|
||||
printf("\b\b\b%2d ", delay);
|
||||
}
|
||||
if (value != 0)
|
||||
printf("\b\bOK");
|
||||
else {
|
||||
result = -1;
|
||||
printf("\b\bfailed");
|
||||
}
|
||||
|
||||
delay = 5;
|
||||
printf("\n--------Press SW11: %2d ", delay);
|
||||
while (delay--) {
|
||||
for (i = 0; i < 100; i++) {
|
||||
value = *pPORTFIO & PF4;
|
||||
if (value != 0) {
|
||||
break;
|
||||
}
|
||||
udelay(10000);
|
||||
}
|
||||
printf("\b\b\b%2d ", delay);
|
||||
}
|
||||
if (value != 0)
|
||||
printf("\b\bOK");
|
||||
else {
|
||||
result = -1;
|
||||
printf("\b\bfailed");
|
||||
}
|
||||
|
||||
delay = 5;
|
||||
printf("\n--------Press SW12: %2d ", delay);
|
||||
while (delay--) {
|
||||
for (i = 0; i < 100; i++) {
|
||||
value = *pPORTFIO & PF3;
|
||||
if (value != 0) {
|
||||
break;
|
||||
}
|
||||
udelay(10000);
|
||||
}
|
||||
printf("\b\b\b%2d ", delay);
|
||||
}
|
||||
if (value != 0)
|
||||
printf("\b\bOK");
|
||||
else {
|
||||
result = -1;
|
||||
printf("\b\bfailed");
|
||||
}
|
||||
|
||||
delay = 5;
|
||||
printf("\n--------Press SW13: %2d ", delay);
|
||||
while (delay--) {
|
||||
for (i = 0; i < 100; i++) {
|
||||
value = *pPORTFIO & PF2;
|
||||
if (value != 0) {
|
||||
break;
|
||||
}
|
||||
udelay(10000);
|
||||
}
|
||||
printf("\b\b\b%2d ", delay);
|
||||
}
|
||||
if (value != 0)
|
||||
printf("\b\bOK");
|
||||
else {
|
||||
result = -1;
|
||||
printf("\b\bfailed");
|
||||
}
|
||||
printf("\n");
|
||||
return result;
|
||||
}
|
||||
#endif
|
201
board/bf537-stamp/cmd_bf537led.c
Normal file
201
board/bf537-stamp/cmd_bf537led.c
Normal file
|
@ -0,0 +1,201 @@
|
|||
/*
|
||||
* U-boot - cmd_bf537led.c
|
||||
*
|
||||
* Copyright (C) 2006 Aaron Gage, Ocean Optics Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <command.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm-blackfin/string.h>
|
||||
#ifdef CONFIG_BF537_STAMP_LEDCMD
|
||||
|
||||
/* Define the command usage in a reusable way */
|
||||
#define USAGE_LONG \
|
||||
"led <number> <action>\n" \
|
||||
" <number> - Index (0-5) of LED to change, or \"all\"\n" \
|
||||
" <action> - Must be one of:\n" \
|
||||
" on off toggle\n"
|
||||
|
||||
/* Number of LEDs supported by the board */
|
||||
#define NUMBER_LEDS 6
|
||||
/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */
|
||||
#define LED_ALL_MASK 0x003F
|
||||
|
||||
void show_cmd_usage(void);
|
||||
void set_led_state(int index, int state);
|
||||
void configure_GPIO_to_output(int index);
|
||||
|
||||
/* Map of LEDs according to their GPIO ports. This can be rearranged or
|
||||
* otherwise changed to account for different GPIO configurations.
|
||||
*/
|
||||
int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 };
|
||||
|
||||
#define ACTION_TOGGLE -1
|
||||
#define ACTION_OFF 0
|
||||
#define ACTION_ON 1
|
||||
|
||||
#define LED_STATE_OFF 0
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
/* This is a trivial atoi implementation since we don't have one available */
|
||||
int atoi(char *string)
|
||||
{
|
||||
int length;
|
||||
int retval = 0;
|
||||
int i;
|
||||
int sign = 1;
|
||||
|
||||
length = strlen(string);
|
||||
for (i = 0; i < length; i++) {
|
||||
if (0 == i && string[0] == '-') {
|
||||
sign = -1;
|
||||
continue;
|
||||
}
|
||||
if (string[i] > '9' || string[i] < '0') {
|
||||
break;
|
||||
}
|
||||
retval *= 10;
|
||||
retval += string[i] - '0';
|
||||
}
|
||||
retval *= sign;
|
||||
return retval;
|
||||
}
|
||||
|
||||
int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int led_mask = 0;
|
||||
int led_current_state = 0;
|
||||
int action = ACTION_OFF;
|
||||
int temp;
|
||||
|
||||
if (3 != argc) {
|
||||
/* Not enough arguments, so just show usage information */
|
||||
show_cmd_usage();
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (strcmp(argv[1], "all") == 0) {
|
||||
led_mask = LED_ALL_MASK;
|
||||
} else {
|
||||
temp = atoi(argv[1]);
|
||||
if (temp < 0 || temp >= NUMBER_LEDS) {
|
||||
printf("Invalid LED number [%s]\n", argv[1]);
|
||||
show_cmd_usage();
|
||||
return 2;
|
||||
}
|
||||
led_mask |= (1 << temp);
|
||||
}
|
||||
|
||||
if (strcmp(argv[2], "off") == 0) {
|
||||
action = ACTION_OFF;
|
||||
} else if (strcmp(argv[2], "on") == 0) {
|
||||
action = ACTION_ON;
|
||||
} else if (strcmp(argv[2], "toggle") == 0) {
|
||||
action = ACTION_TOGGLE;
|
||||
} else {
|
||||
printf("Invalid action [%s]\n", argv[2]);
|
||||
show_cmd_usage();
|
||||
return 3;
|
||||
}
|
||||
|
||||
for (temp = 0; temp < NUMBER_LEDS; temp++) {
|
||||
if ((led_mask & (1 << temp)) > 0) {
|
||||
/*
|
||||
* It is possible that the user has wired one of PF6-PF11 to
|
||||
* something other than an LED, so this will only change a pin
|
||||
* to output if the user has indicated a state change. This may
|
||||
* happen a lot, but this way is safer than just setting all pins
|
||||
* to output.
|
||||
*/
|
||||
configure_GPIO_to_output(temp);
|
||||
|
||||
led_current_state =
|
||||
((*pPORTFIO & led_ports[temp]) >
|
||||
0) ? LED_STATE_ON : LED_STATE_OFF;
|
||||
/*
|
||||
printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp],
|
||||
led_current_state);
|
||||
printf("*pPORTFIO is %x\n", *pPORTFIO);
|
||||
*/
|
||||
if (ACTION_ON == action
|
||||
|| (ACTION_TOGGLE == action
|
||||
&& 0 == led_current_state)) {
|
||||
printf("Turning LED %d on\n", temp);
|
||||
set_led_state(temp, LED_STATE_ON);
|
||||
} else {
|
||||
printf("Turning LED %d off\n", temp);
|
||||
set_led_state(temp, LED_STATE_OFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The GPIO pins that go to the LEDs on the BF537 stamp must be configured
|
||||
* as output. This function simply configures them that way. This could
|
||||
* be done to all of the GPIO lines at once, but if a user is using a
|
||||
* custom board, this will try to be nice and only change the GPIO lines
|
||||
* that the user specifically names.
|
||||
*/
|
||||
void configure_GPIO_to_output(int index)
|
||||
{
|
||||
int port;
|
||||
|
||||
port = led_ports[index];
|
||||
|
||||
/* Clear the Port F Function Enable Register */
|
||||
*pPORTF_FER &= ~port;
|
||||
/* Set the Port F I/O direction register */
|
||||
*pPORTFIO_DIR |= port;
|
||||
/* Clear the Port F I/O Input Enable Register */
|
||||
*pPORTFIO_INEN &= ~port;
|
||||
}
|
||||
|
||||
/* Enforce the given state on the GPIO line for the indicated LED */
|
||||
void set_led_state(int index, int state)
|
||||
{
|
||||
int port;
|
||||
|
||||
port = led_ports[index];
|
||||
|
||||
if (LED_STATE_OFF == state) {
|
||||
/* Clear the bit to turn off the LED */
|
||||
*pPORTFIO &= ~port;
|
||||
} else {
|
||||
/* Set the bit to turn on the LED */
|
||||
*pPORTFIO |= port;
|
||||
}
|
||||
}
|
||||
|
||||
/* Display usage information */
|
||||
void show_cmd_usage()
|
||||
{
|
||||
printf("Usage:\n%s", USAGE_LONG);
|
||||
}
|
||||
|
||||
/* Register information for u-boot to find this command */
|
||||
U_BOOT_CMD(led, 3, 1, do_bf537led,
|
||||
"led- Control BF537 stamp LEDs\n", USAGE_LONG);
|
||||
|
||||
#endif
|
25
board/bf537-stamp/config.mk
Normal file
25
board/bf537-stamp/config.mk
Normal file
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
|
||||
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
|
||||
TEXT_BASE = 0x03FC0000
|
545
board/bf537-stamp/ether_bf537.c
Normal file
545
board/bf537-stamp/ether_bf537.c
Normal file
|
@ -0,0 +1,545 @@
|
|||
/*
|
||||
* ADI Blackfin 537 MAC Ethernet
|
||||
*
|
||||
* Copyright (c) 2005 Analog Device, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <net.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include "ether_bf537.h"
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
#include <post.h>
|
||||
#endif
|
||||
|
||||
#undef DEBUG_ETHERNET
|
||||
|
||||
#ifdef DEBUG_ETHERNET
|
||||
#define DEBUGF(fmt,args...) printf(fmt,##args)
|
||||
#else
|
||||
#define DEBUGF(fmt,args...)
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET)
|
||||
|
||||
#define RXBUF_BASE_ADDR 0xFF900000
|
||||
#define TXBUF_BASE_ADDR 0xFF800000
|
||||
#define TX_BUF_CNT 1
|
||||
|
||||
#define TOUT_LOOP 1000000
|
||||
|
||||
ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
|
||||
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
|
||||
static u16 txIdx; /* index of the current RX buffer */
|
||||
static u16 rxIdx; /* index of the current TX buffer */
|
||||
|
||||
u8 SrcAddr[6];
|
||||
u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
|
||||
|
||||
/* DMAx_CONFIG values at DMA Restart */
|
||||
const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 };
|
||||
|
||||
#if 0
|
||||
rxdmacfg.b_DMA_EN = 1; /* enabled */
|
||||
rxdmacfg.b_WNR = 1; /* write to memory */
|
||||
rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
|
||||
rxdmacfg.b_DMA2D = 0; /* N/A */
|
||||
rxdmacfg.b_RESTART= 0; /* N/A */
|
||||
rxdmacfg.b_DI_SEL = 0; /* N/A */
|
||||
rxdmacfg.b_DI_EN = 0; /* no interrupt */
|
||||
rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
|
||||
rxdmacfg.b_FLOW = 7; /* large desc flow */
|
||||
#endif
|
||||
|
||||
const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 };
|
||||
|
||||
#if 0
|
||||
txdmacfg.b_DMA_EN = 1; /* enabled */
|
||||
txdmacfg.b_WNR = 0; /* read from memory */
|
||||
txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
|
||||
txdmacfg.b_DMA2D = 0; /* N/A */
|
||||
txdmacfg.b_RESTART= 0; /* N/A */
|
||||
txdmacfg.b_DI_SEL = 0; /* N/A */
|
||||
txdmacfg.b_DI_EN = 0; /* no interrupt */
|
||||
txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
|
||||
txdmacfg.b_FLOW = 7; /* large desc flow */
|
||||
#endif
|
||||
|
||||
ADI_ETHER_BUFFER *SetupRxBuffer(int no);
|
||||
ADI_ETHER_BUFFER *SetupTxBuffer(int no);
|
||||
|
||||
static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd);
|
||||
static void bfin_EMAC_halt(struct eth_device *dev);
|
||||
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
|
||||
int length);
|
||||
static int bfin_EMAC_recv(struct eth_device *dev);
|
||||
|
||||
int bfin_EMAC_initialize(bd_t * bis)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
dev = (struct eth_device *)malloc(sizeof(*dev));
|
||||
if (dev == NULL)
|
||||
hang();
|
||||
|
||||
memset(dev, 0, sizeof(*dev));
|
||||
sprintf(dev->name, "BF537 ETHERNET");
|
||||
|
||||
dev->iobase = 0;
|
||||
dev->priv = 0;
|
||||
dev->init = bfin_EMAC_init;
|
||||
dev->halt = bfin_EMAC_halt;
|
||||
dev->send = bfin_EMAC_send;
|
||||
dev->recv = bfin_EMAC_recv;
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
|
||||
int length)
|
||||
{
|
||||
int i;
|
||||
int result = 0;
|
||||
unsigned int *buf;
|
||||
buf = (unsigned int *)packet;
|
||||
|
||||
if (length <= 0) {
|
||||
printf("Ethernet: bad packet size: %d\n", length);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
|
||||
printf("Ethernet: tx DMA error\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
|
||||
if (i > TOUT_LOOP) {
|
||||
puts("Ethernet: tx time out\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
txbuf[txIdx]->FrmData->NoBytes = length;
|
||||
memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
|
||||
txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
|
||||
*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
|
||||
*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
|
||||
*pEMAC_OPMODE |= TE;
|
||||
|
||||
for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
|
||||
if (i > TOUT_LOOP) {
|
||||
puts("Ethernet: tx error\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
result = txbuf[txIdx]->StatusWord;
|
||||
txbuf[txIdx]->StatusWord = 0;
|
||||
if ((txIdx + 1) >= TX_BUF_CNT)
|
||||
txIdx = 0;
|
||||
else
|
||||
txIdx++;
|
||||
out:
|
||||
DEBUGF("BFIN EMAC send: length = %d\n", length);
|
||||
return result;
|
||||
}
|
||||
|
||||
static int bfin_EMAC_recv(struct eth_device *dev)
|
||||
{
|
||||
int length = 0;
|
||||
|
||||
for (;;) {
|
||||
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
|
||||
length = -1;
|
||||
break;
|
||||
}
|
||||
if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
|
||||
printf("Ethernet: rx dma overrun\n");
|
||||
break;
|
||||
}
|
||||
if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
|
||||
printf("Ethernet: rx error\n");
|
||||
break;
|
||||
}
|
||||
length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
|
||||
if (length <= 4) {
|
||||
printf("Ethernet: bad frame\n");
|
||||
break;
|
||||
}
|
||||
NetRxPackets[rxIdx] =
|
||||
(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
|
||||
NetReceive(NetRxPackets[rxIdx], length - 4);
|
||||
*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
|
||||
rxbuf[rxIdx]->StatusWord = 0x00000000;
|
||||
if ((rxIdx + 1) >= PKTBUFSRX)
|
||||
rxIdx = 0;
|
||||
else
|
||||
rxIdx++;
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
/**************************************************************
|
||||
*
|
||||
* Ethernet Initialization Routine
|
||||
*
|
||||
*************************************************************/
|
||||
|
||||
static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd)
|
||||
{
|
||||
u32 opmode;
|
||||
int dat;
|
||||
int i;
|
||||
DEBUGF("Eth_init: ......\n");
|
||||
|
||||
txIdx = 0;
|
||||
rxIdx = 0;
|
||||
|
||||
/* Initialize System Register */
|
||||
if (SetupSystemRegs(&dat) < 0)
|
||||
return -1;
|
||||
|
||||
/* Initialize EMAC address */
|
||||
SetupMacAddr(SrcAddr);
|
||||
|
||||
/* Initialize TX and RX buffer */
|
||||
for (i = 0; i < PKTBUFSRX; i++) {
|
||||
rxbuf[i] = SetupRxBuffer(i);
|
||||
if (i > 0) {
|
||||
rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
|
||||
&(rxbuf[i]->Dma[0]);
|
||||
if (i == (PKTBUFSRX - 1))
|
||||
rxbuf[i]->Dma[1].NEXT_DESC_PTR =
|
||||
&(rxbuf[0]->Dma[0]);
|
||||
}
|
||||
}
|
||||
for (i = 0; i < TX_BUF_CNT; i++) {
|
||||
txbuf[i] = SetupTxBuffer(i);
|
||||
if (i > 0) {
|
||||
txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
|
||||
&(txbuf[i]->Dma[0]);
|
||||
if (i == (TX_BUF_CNT - 1))
|
||||
txbuf[i]->Dma[1].NEXT_DESC_PTR =
|
||||
&(txbuf[0]->Dma[0]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set RX DMA */
|
||||
*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
|
||||
*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
|
||||
|
||||
/* Wait MII done */
|
||||
PollMdcDone();
|
||||
|
||||
/* We enable only RX here */
|
||||
/* ASTP : Enable Automatic Pad Stripping
|
||||
PR : Promiscuous Mode for test
|
||||
PSF : Receive frames with total length less than 64 bytes.
|
||||
FDMODE : Full Duplex Mode
|
||||
LB : Internal Loopback for test
|
||||
RE : Receiver Enable */
|
||||
if (dat == FDMODE)
|
||||
opmode = ASTP | FDMODE | PSF;
|
||||
else
|
||||
opmode = ASTP | PSF;
|
||||
opmode |= RE;
|
||||
#ifdef CONFIG_BFIN_MAC_RMII
|
||||
opmode |= TE | RMII;
|
||||
#endif
|
||||
/* Turn on the EMAC */
|
||||
*pEMAC_OPMODE = opmode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bfin_EMAC_halt(struct eth_device *dev)
|
||||
{
|
||||
DEBUGF("Eth_halt: ......\n");
|
||||
/* Turn off the EMAC */
|
||||
*pEMAC_OPMODE = 0x00000000;
|
||||
/* Turn off the EMAC RX DMA */
|
||||
*pDMA1_CONFIG = 0x0000;
|
||||
*pDMA2_CONFIG = 0x0000;
|
||||
|
||||
}
|
||||
|
||||
void SetupMacAddr(u8 * MACaddr)
|
||||
{
|
||||
char *tmp, *end;
|
||||
int i;
|
||||
/* this depends on a little-endian machine */
|
||||
tmp = getenv("ethaddr");
|
||||
if (tmp) {
|
||||
for (i = 0; i < 6; i++) {
|
||||
MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
|
||||
if (tmp)
|
||||
tmp = (*end) ? end + 1 : end;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NETCONSOLE
|
||||
printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n",
|
||||
MACaddr[0], MACaddr[1],
|
||||
MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]);
|
||||
#endif
|
||||
*pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 |
|
||||
MACaddr[2] << 16 | MACaddr[3] << 24;
|
||||
*pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8;
|
||||
}
|
||||
}
|
||||
|
||||
void PollMdcDone(void)
|
||||
{
|
||||
/* poll the STABUSY bit */
|
||||
while (*pEMAC_STAADD & STABUSY) ;
|
||||
}
|
||||
|
||||
void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
|
||||
{
|
||||
PollMdcDone();
|
||||
|
||||
*pEMAC_STADAT = Data;
|
||||
|
||||
*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
|
||||
STAOP | STAIE | STABUSY;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* Read an off-chip register in a PHY through the MDC/MDIO port *
|
||||
*********************************************************************************/
|
||||
u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
|
||||
{
|
||||
u16 Data;
|
||||
|
||||
PollMdcDone();
|
||||
|
||||
*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
|
||||
STAIE | STABUSY;
|
||||
|
||||
PollMdcDone();
|
||||
|
||||
Data = (u16) * pEMAC_STADAT;
|
||||
|
||||
PHYregs[RegAddr] = Data; /* save shadow copy */
|
||||
|
||||
return Data;
|
||||
}
|
||||
|
||||
void SoftResetPHY(void)
|
||||
{
|
||||
u16 phydat;
|
||||
/* set the reset bit */
|
||||
WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
|
||||
/* and clear it again */
|
||||
WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
|
||||
do {
|
||||
/* poll until reset is complete */
|
||||
phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
|
||||
} while ((phydat & PHY_RESET) != 0);
|
||||
}
|
||||
|
||||
int SetupSystemRegs(int *opmode)
|
||||
{
|
||||
u16 sysctl, phydat;
|
||||
int count = 0;
|
||||
/* Enable PHY output */
|
||||
*pVR_CTL |= PHYCLKOE;
|
||||
/* MDC = 2.5 MHz */
|
||||
sysctl = SET_MDCDIV(24);
|
||||
/* Odd word alignment for Receive Frame DMA word */
|
||||
/* Configure checksum support and rcve frame word alignment */
|
||||
sysctl |= RXDWA | RXCKS;
|
||||
*pEMAC_SYSCTL = sysctl;
|
||||
/* auto negotiation on */
|
||||
/* full duplex */
|
||||
/* 100 Mbps */
|
||||
phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
|
||||
WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
|
||||
do {
|
||||
udelay(1000);
|
||||
phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
|
||||
if (count > 3000) {
|
||||
printf
|
||||
("Link is down, please check your network connection\n");
|
||||
return -1;
|
||||
}
|
||||
count++;
|
||||
} while (!(phydat & 0x0004));
|
||||
|
||||
phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
|
||||
|
||||
if ((phydat & 0x0100) || (phydat & 0x0040))
|
||||
*opmode = FDMODE;
|
||||
else
|
||||
*opmode = 0;
|
||||
|
||||
*pEMAC_MMC_CTL = RSTC | CROLL;
|
||||
|
||||
/* Initialize the TX DMA channel registers */
|
||||
*pDMA2_X_COUNT = 0;
|
||||
*pDMA2_X_MODIFY = 4;
|
||||
*pDMA2_Y_COUNT = 0;
|
||||
*pDMA2_Y_MODIFY = 0;
|
||||
|
||||
/* Initialize the RX DMA channel registers */
|
||||
*pDMA1_X_COUNT = 0;
|
||||
*pDMA1_X_MODIFY = 4;
|
||||
*pDMA1_Y_COUNT = 0;
|
||||
*pDMA1_Y_MODIFY = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ADI_ETHER_BUFFER *SetupRxBuffer(int no)
|
||||
{
|
||||
ADI_ETHER_FRAME_BUFFER *frmbuf;
|
||||
ADI_ETHER_BUFFER *buf;
|
||||
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
|
||||
int total_size = nobytes_buffer + RECV_BUFSIZE;
|
||||
|
||||
buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
|
||||
frmbuf =
|
||||
(ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
|
||||
nobytes_buffer);
|
||||
|
||||
memset(buf, 0x00, nobytes_buffer);
|
||||
buf->FrmData = frmbuf;
|
||||
memset(frmbuf, 0xfe, RECV_BUFSIZE);
|
||||
|
||||
/* set up first desc to point to receive frame buffer */
|
||||
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
|
||||
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
|
||||
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
|
||||
buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
|
||||
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
|
||||
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
|
||||
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
|
||||
|
||||
/* set up second desc to point to status word */
|
||||
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
|
||||
buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
|
||||
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
|
||||
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
|
||||
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
|
||||
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
|
||||
buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
|
||||
buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
ADI_ETHER_BUFFER *SetupTxBuffer(int no)
|
||||
{
|
||||
ADI_ETHER_FRAME_BUFFER *frmbuf;
|
||||
ADI_ETHER_BUFFER *buf;
|
||||
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
|
||||
int total_size = nobytes_buffer + RECV_BUFSIZE;
|
||||
|
||||
buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
|
||||
frmbuf =
|
||||
(ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
|
||||
nobytes_buffer);
|
||||
|
||||
memset(buf, 0x00, nobytes_buffer);
|
||||
buf->FrmData = frmbuf;
|
||||
memset(frmbuf, 0x00, RECV_BUFSIZE);
|
||||
|
||||
/* set up first desc to point to receive frame buffer */
|
||||
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
|
||||
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
|
||||
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
|
||||
buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
|
||||
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
|
||||
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
|
||||
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
|
||||
|
||||
/* set up second desc to point to status word */
|
||||
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
|
||||
buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
|
||||
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
|
||||
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
|
||||
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
|
||||
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
|
||||
buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
|
||||
buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
|
||||
int ether_post_test(int flags)
|
||||
{
|
||||
uchar buf[64];
|
||||
int i, value = 0;
|
||||
int length;
|
||||
|
||||
printf("\n--------");
|
||||
bfin_EMAC_init(NULL, NULL);
|
||||
/* construct the package */
|
||||
buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
|
||||
buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
|
||||
buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
|
||||
buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
|
||||
buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
|
||||
buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
|
||||
buf[12] = 0x08; /* Type: ARP */
|
||||
buf[13] = 0x06;
|
||||
buf[14] = 0x00; /* Hardware type: Ethernet */
|
||||
buf[15] = 0x01;
|
||||
buf[16] = 0x08; /* Protocal type: IP */
|
||||
buf[17] = 0x00;
|
||||
buf[18] = 0x06; /* Hardware size */
|
||||
buf[19] = 0x04; /* Protocol size */
|
||||
buf[20] = 0x00; /* Opcode: request */
|
||||
buf[21] = 0x01;
|
||||
|
||||
for (i = 0; i < 42; i++)
|
||||
buf[i + 22] = i;
|
||||
printf("--------Send 64 bytes......\n");
|
||||
bfin_EMAC_send(NULL, (volatile void *)buf, 64);
|
||||
for (i = 0; i < 100; i++) {
|
||||
udelay(10000);
|
||||
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
|
||||
value = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (value == 0) {
|
||||
printf("--------EMAC can't receive any data\n");
|
||||
eth_halt();
|
||||
return -1;
|
||||
}
|
||||
length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
|
||||
for (i = 0; i < length; i++) {
|
||||
if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
|
||||
printf("--------EMAC receive error data!\n");
|
||||
eth_halt();
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
printf("--------receive %d bytes, matched\n", length);
|
||||
bfin_EMAC_halt(NULL);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CFG_CMD_NET */
|
110
board/bf537-stamp/ether_bf537.h
Normal file
110
board/bf537-stamp/ether_bf537.h
Normal file
|
@ -0,0 +1,110 @@
|
|||
#define PHYADDR 0x01
|
||||
#define NO_PHY_REGS 0x20
|
||||
|
||||
#define DEFAULT_PHY_PHYID1 0x0007
|
||||
#define DEFAULT_PHY_PHYID2 0xC0A3
|
||||
#define PHY_MODECTL 0x00
|
||||
#define PHY_MODESTAT 0x01
|
||||
#define PHY_PHYID1 0x02
|
||||
#define PHY_PHYID2 0x03
|
||||
#define PHY_ANAR 0x04
|
||||
#define PHY_ANLPAR 0x05
|
||||
#define PHY_ANER 0x06
|
||||
|
||||
#define PHY_RESET 0x8000
|
||||
#define PHY_ANEG_EN 0x1000
|
||||
#define PHY_DUPLEX 0x0100
|
||||
#define PHY_SPD_SET 0x2000
|
||||
|
||||
#define RECV_BUFSIZE (0x614)
|
||||
|
||||
typedef volatile u32 reg32;
|
||||
typedef volatile u16 reg16;
|
||||
|
||||
typedef struct ADI_DMA_CONFIG_REG {
|
||||
u16 b_DMA_EN:1; /* 0 Enabled */
|
||||
u16 b_WNR:1; /* 1 Direction */
|
||||
u16 b_WDSIZE:2; /* 2:3 Transfer word size */
|
||||
u16 b_DMA2D:1; /* 4 DMA mode */
|
||||
u16 b_RESTART:1; /* 5 Retain FIFO */
|
||||
u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
|
||||
u16 b_DI_EN:1; /* 7 Data interrupt enabled */
|
||||
u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
|
||||
u16 b_FLOW:3; /* 12:14Flow */
|
||||
} ADI_DMA_CONFIG_REG;
|
||||
|
||||
typedef struct adi_ether_frame_buffer {
|
||||
u16 NoBytes; /* the no. of following bytes */
|
||||
u8 Dest[6]; /* destination MAC address */
|
||||
u8 Srce[6]; /* source MAC address */
|
||||
u16 LTfield; /* length/type field */
|
||||
u8 Data[0]; /* payload bytes */
|
||||
} ADI_ETHER_FRAME_BUFFER;
|
||||
/* 16 bytes/struct */
|
||||
|
||||
typedef struct dma_descriptor {
|
||||
struct dma_descriptor *NEXT_DESC_PTR;
|
||||
u32 START_ADDR;
|
||||
ADI_DMA_CONFIG_REG CONFIG;
|
||||
} DMA_DESCRIPTOR;
|
||||
/* 10 bytes/struct in 12 bytes */
|
||||
|
||||
typedef struct adi_ether_buffer {
|
||||
DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
|
||||
ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
|
||||
struct adi_ether_buffer *pNext; /* next buffer */
|
||||
struct adi_ether_buffer *pPrev; /* prev buffer */
|
||||
u16 IPHdrChksum; /* the IP header checksum */
|
||||
u16 IPPayloadChksum; /* the IP header and payload checksum */
|
||||
volatile u32 StatusWord; /* the frame status word */
|
||||
} ADI_ETHER_BUFFER;
|
||||
/* 40 bytes/struct in 44 bytes */
|
||||
|
||||
void SetupMacAddr(u8 * MACaddr);
|
||||
|
||||
void PollMdcDone(void);
|
||||
void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
|
||||
u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
|
||||
void SoftResetPHY(void);
|
||||
void DumpPHYRegs(void);
|
||||
|
||||
int SetupSystemRegs(int *opmode);
|
||||
|
||||
/**
|
||||
* is_zero_ether_addr - Determine if give Ethernet address is all zeros.
|
||||
* @addr: Pointer to a six-byte array containing the Ethernet address
|
||||
*
|
||||
* Return true if the address is all zeroes.
|
||||
*/
|
||||
static inline int is_zero_ether_addr(const u8 * addr)
|
||||
{
|
||||
return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
|
||||
}
|
||||
|
||||
/**
|
||||
* is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
|
||||
* @addr: Pointer to a six-byte array containing the Ethernet address
|
||||
*
|
||||
* Return true if the address is a multicast address.
|
||||
* By definition the broadcast address is also a multicast address.
|
||||
*/
|
||||
static inline int is_multicast_ether_addr(const u8 * addr)
|
||||
{
|
||||
return (0x01 & addr[0]);
|
||||
}
|
||||
|
||||
/**
|
||||
* is_valid_ether_addr - Determine if the given Ethernet address is valid
|
||||
* @addr: Pointer to a six-byte array containing the Ethernet address
|
||||
*
|
||||
* Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
|
||||
* a multicast address, and is not FF:FF:FF:FF:FF:FF.
|
||||
*
|
||||
* Return true if the address is valid.
|
||||
*/
|
||||
static inline int is_valid_ether_addr(const u8 * addr)
|
||||
{
|
||||
/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
|
||||
* explicitly check for it here. */
|
||||
return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
|
||||
}
|
123
board/bf537-stamp/flash-defines.h
Normal file
123
board/bf537-stamp/flash-defines.h
Normal file
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* U-boot - flash-defines.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __FLASHDEFINES_H__
|
||||
#define __FLASHDEFINES_H__
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#define V_ULONG(a) (*(volatile unsigned long *)( a ))
|
||||
#define V_BYTE(a) (*(volatile unsigned char *)( a ))
|
||||
#define TRUE 0x1
|
||||
#define FALSE 0x0
|
||||
#define BUFFER_SIZE 0x80000
|
||||
#define NO_COMMAND 0
|
||||
#define GET_CODES 1
|
||||
#define RESET 2
|
||||
#define WRITE 3
|
||||
#define FILL 4
|
||||
#define ERASE_ALL 5
|
||||
#define ERASE_SECT 6
|
||||
#define READ 7
|
||||
#define GET_SECTNUM 8
|
||||
#define FLASH_START_L 0x0000
|
||||
#define FLASH_START_H 0x2000
|
||||
#define FLASH_MAN_ST 2
|
||||
#define RESET_VAL 0xF0
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
int get_codes(void);
|
||||
int poll_toggle_bit(long lOffset);
|
||||
void reset_flash(void);
|
||||
int erase_flash(void);
|
||||
int erase_block_flash(int);
|
||||
void unlock_flash(long lOffset);
|
||||
int write_data(long lStart, long lCount, uchar * pnData);
|
||||
int read_flash(long nOffset, int *pnValue);
|
||||
int write_flash(long nOffset, int nValue);
|
||||
void get_sector_number(long lOffset, int *pnSector);
|
||||
int GetSectorProtectionStatus(flash_info_t * info, int nSector);
|
||||
int GetOffset(int nBlock);
|
||||
int AFP_NumSectors = 71;
|
||||
long AFP_SectorSize2 = 0x10000;
|
||||
int AFP_SectorSize1 = 0x2000;
|
||||
|
||||
#define NUM_SECTORS 71
|
||||
|
||||
#define WRITESEQ1 0x0AAA
|
||||
#define WRITESEQ2 0x0554
|
||||
#define WRITESEQ3 0x0AAA
|
||||
#define WRITESEQ4 0x0AAA
|
||||
#define WRITESEQ5 0x0554
|
||||
#define WRITESEQ6 0x0AAA
|
||||
#define WRITEDATA1 0xaa
|
||||
#define WRITEDATA2 0x55
|
||||
#define WRITEDATA3 0x80
|
||||
#define WRITEDATA4 0xaa
|
||||
#define WRITEDATA5 0x55
|
||||
#define WRITEDATA6 0x10
|
||||
#define PriFlashABegin 0
|
||||
#define SecFlashABegin 8
|
||||
#define SecFlashBBegin 36
|
||||
#define PriFlashAOff 0x0
|
||||
#define PriFlashBOff 0x100000
|
||||
#define SecFlashAOff 0x10000
|
||||
#define SecFlashBOff 0x280000
|
||||
#define INVALIDLOCNSTART 0x20270000
|
||||
#define INVALIDLOCNEND 0x20280000
|
||||
#define BlockEraseVal 0x30
|
||||
#define UNLOCKDATA1 0xaa
|
||||
#define UNLOCKDATA2 0x55
|
||||
#define UNLOCKDATA3 0xa0
|
||||
#define GETCODEDATA1 0xaa
|
||||
#define GETCODEDATA2 0x55
|
||||
#define GETCODEDATA3 0x90
|
||||
#define SecFlashASec1Off 0x200000
|
||||
#define SecFlashASec2Off 0x204000
|
||||
#define SecFlashASec3Off 0x206000
|
||||
#define SecFlashASec4Off 0x208000
|
||||
#define SecFlashAEndOff 0x210000
|
||||
#define SecFlashBSec1Off 0x280000
|
||||
#define SecFlashBSec2Off 0x284000
|
||||
#define SecFlashBSec3Off 0x286000
|
||||
#define SecFlashBSec4Off 0x288000
|
||||
#define SecFlashBEndOff 0x290000
|
||||
|
||||
#define SECT32 32
|
||||
#define SECT33 33
|
||||
#define SECT34 34
|
||||
#define SECT35 35
|
||||
#define SECT36 36
|
||||
#define SECT37 37
|
||||
#define SECT38 38
|
||||
#define SECT39 39
|
||||
|
||||
#define FLASH_SUCCESS 0
|
||||
#define FLASH_FAIL -1
|
||||
|
||||
#endif
|
403
board/bf537-stamp/flash.c
Normal file
403
board/bf537-stamp/flash.c
Normal file
|
@ -0,0 +1,403 @@
|
|||
/*
|
||||
* U-boot - flash.c Flash driver for PSD4256GV
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <malloc.h>
|
||||
#include <config.h>
|
||||
#include <asm/io.h>
|
||||
#include "flash-defines.h"
|
||||
|
||||
void flash_reset(void)
|
||||
{
|
||||
reset_flash();
|
||||
}
|
||||
|
||||
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
|
||||
{
|
||||
int id = 0, i = 0;
|
||||
static int FlagDev = 1;
|
||||
|
||||
id = get_codes();
|
||||
if (FlagDev) {
|
||||
FlagDev = 0;
|
||||
}
|
||||
info->flash_id = id;
|
||||
switch (bank_flag) {
|
||||
case 0:
|
||||
for (i = PriFlashABegin; i < SecFlashABegin; i++)
|
||||
info->start[i] = (baseaddr + (i * AFP_SectorSize1));
|
||||
for (i = SecFlashABegin; i < NUM_SECTORS; i++)
|
||||
info->start[i] =
|
||||
(baseaddr + SecFlashAOff +
|
||||
((i - SecFlashABegin) * AFP_SectorSize2));
|
||||
info->size = 0x400000;
|
||||
info->sector_count = NUM_SECTORS;
|
||||
break;
|
||||
case 1:
|
||||
info->start[0] = baseaddr + SecFlashASec1Off;
|
||||
info->start[1] = baseaddr + SecFlashASec2Off;
|
||||
info->start[2] = baseaddr + SecFlashASec3Off;
|
||||
info->start[3] = baseaddr + SecFlashASec4Off;
|
||||
info->size = 0x10000;
|
||||
info->sector_count = 4;
|
||||
break;
|
||||
case 2:
|
||||
info->start[0] = baseaddr + SecFlashBSec1Off;
|
||||
info->start[1] = baseaddr + SecFlashBSec2Off;
|
||||
info->start[2] = baseaddr + SecFlashBSec3Off;
|
||||
info->start[3] = baseaddr + SecFlashBSec4Off;
|
||||
info->size = 0x10000;
|
||||
info->sector_count = 4;
|
||||
break;
|
||||
}
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
unsigned long flash_init(void)
|
||||
{
|
||||
unsigned long size_b;
|
||||
int i;
|
||||
|
||||
size_b = 0;
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) {
|
||||
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b, size_b >> 20);
|
||||
}
|
||||
|
||||
/* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */
|
||||
(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
|
||||
(flash_info[0].start[2] - 1), &flash_info[0]);
|
||||
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
|
||||
(void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
return (size_b);
|
||||
}
|
||||
|
||||
void flash_print_info(flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id) {
|
||||
case (STM_ID_29W320EB & 0xFFFF):
|
||||
case (STM_ID_29W320DB & 0xFFFF):
|
||||
printf("ST Microelectronics ");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Vendor: (0x%08X) ", info->flash_id);
|
||||
break;
|
||||
}
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf("\n ");
|
||||
printf(" %08lX%s",
|
||||
info->start[i], info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int cnt = 0, i;
|
||||
int prot, sect;
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
if (prot)
|
||||
printf("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
else
|
||||
printf("\n");
|
||||
|
||||
cnt = s_last - s_first + 1;
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
|
||||
printf("Erasing Flash locations, Please Wait\n");
|
||||
for (i = s_first; i <= s_last; i++) {
|
||||
if (info->protect[i] == 0) { /* not protected */
|
||||
if (erase_block_flash(i) < 0) {
|
||||
printf("Error Sector erasing \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
}
|
||||
}
|
||||
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
if (cnt == FLASH_TOT_SECT) {
|
||||
printf("Erasing flash, Please Wait \n");
|
||||
if (erase_flash() < 0) {
|
||||
printf("Erasing flash failed \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
} else {
|
||||
printf("Erasing Flash locations, Please Wait\n");
|
||||
for (i = s_first; i <= s_last; i++) {
|
||||
if (info->protect[i] == 0) { /* not protected */
|
||||
if (erase_block_flash(i) < 0) {
|
||||
printf("Error Sector erasing \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
printf("\n");
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
int d;
|
||||
if (addr % 2) {
|
||||
read_flash(addr - 1 - CFG_FLASH_BASE, &d);
|
||||
d = (int)((d & 0x00FF) | (*src++ << 8));
|
||||
write_data(addr - 1, 2, (uchar *) & d);
|
||||
write_data(addr + 1, cnt - 1, src);
|
||||
} else
|
||||
write_data(addr, cnt, src);
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
int write_data(long lStart, long lCount, uchar * pnData)
|
||||
{
|
||||
long i = 0;
|
||||
unsigned long ulOffset = lStart - CFG_FLASH_BASE;
|
||||
int d;
|
||||
int nSector = 0;
|
||||
int flag = 0;
|
||||
|
||||
if (lCount % 2) {
|
||||
flag = 1;
|
||||
lCount = lCount - 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
|
||||
get_sector_number(ulOffset, &nSector);
|
||||
read_flash(ulOffset, &d);
|
||||
if (d != 0xffff) {
|
||||
printf
|
||||
("Flash not erased at offset 0x%x Please erase to reprogram \n",
|
||||
ulOffset);
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
unlock_flash(ulOffset);
|
||||
d = (int)(pnData[i] | pnData[i + 1] << 8);
|
||||
write_flash(ulOffset, d);
|
||||
if (poll_toggle_bit(ulOffset) < 0) {
|
||||
printf("Error programming the flash \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
if ((i > 0) && (!(i % AFP_SectorSize2)))
|
||||
printf(".");
|
||||
}
|
||||
if (flag) {
|
||||
get_sector_number(ulOffset, &nSector);
|
||||
read_flash(ulOffset, &d);
|
||||
if (d != 0xffff) {
|
||||
printf
|
||||
("Flash not erased at offset 0x%x Please erase to reprogram \n",
|
||||
ulOffset);
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
unlock_flash(ulOffset);
|
||||
d = (int)(pnData[i] | (d & 0xFF00));
|
||||
write_flash(ulOffset, d);
|
||||
if (poll_toggle_bit(ulOffset) < 0) {
|
||||
printf("Error programming the flash \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
}
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
int write_flash(long nOffset, int nValue)
|
||||
{
|
||||
long addr;
|
||||
|
||||
addr = (CFG_FLASH_BASE + nOffset);
|
||||
*(unsigned volatile short *)addr = nValue;
|
||||
sync();
|
||||
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
if (icache_status())
|
||||
udelay(CONFIG_CCLK_HZ / 1000000);
|
||||
#endif
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
int read_flash(long nOffset, int *pnValue)
|
||||
{
|
||||
unsigned short *pFlashAddr =
|
||||
(unsigned short *)(CFG_FLASH_BASE + nOffset);
|
||||
|
||||
*pnValue = *pFlashAddr;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
int poll_toggle_bit(long lOffset)
|
||||
{
|
||||
unsigned int u1, u2;
|
||||
volatile unsigned long *FB =
|
||||
(volatile unsigned long *)(CFG_FLASH_BASE + lOffset);
|
||||
while (1) {
|
||||
u1 = *(volatile unsigned short *)FB;
|
||||
u2 = *(volatile unsigned short *)FB;
|
||||
u1 ^= u2;
|
||||
if (!(u1 & 0x0040))
|
||||
break;
|
||||
if (!(u2 & 0x0020))
|
||||
continue;
|
||||
else {
|
||||
u1 = *(volatile unsigned short *)FB;
|
||||
u2 = *(volatile unsigned short *)FB;
|
||||
u1 ^= u2;
|
||||
if (!(u1 & 0x0040))
|
||||
break;
|
||||
else {
|
||||
reset_flash();
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
}
|
||||
}
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
void reset_flash(void)
|
||||
{
|
||||
write_flash(WRITESEQ1, RESET_VAL);
|
||||
/* Wait for 10 micro seconds */
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
int erase_flash(void)
|
||||
{
|
||||
write_flash(WRITESEQ1, WRITEDATA1);
|
||||
write_flash(WRITESEQ2, WRITEDATA2);
|
||||
write_flash(WRITESEQ3, WRITEDATA3);
|
||||
write_flash(WRITESEQ4, WRITEDATA4);
|
||||
write_flash(WRITESEQ5, WRITEDATA5);
|
||||
write_flash(WRITESEQ6, WRITEDATA6);
|
||||
|
||||
if (poll_toggle_bit(0x0000) < 0)
|
||||
return FLASH_FAIL;
|
||||
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
int erase_block_flash(int nBlock)
|
||||
{
|
||||
long ulSectorOff = 0x0;
|
||||
|
||||
if ((nBlock < 0) || (nBlock > AFP_NumSectors))
|
||||
return FALSE;
|
||||
|
||||
// figure out the offset of the block in flash
|
||||
if ((nBlock >= 0) && (nBlock < SecFlashABegin))
|
||||
ulSectorOff = nBlock * AFP_SectorSize1;
|
||||
|
||||
else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS))
|
||||
ulSectorOff =
|
||||
SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2;
|
||||
// no such sector
|
||||
else
|
||||
return FLASH_FAIL;
|
||||
|
||||
write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
|
||||
write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
|
||||
write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
|
||||
write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
|
||||
write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
|
||||
|
||||
write_flash(ulSectorOff, BlockEraseVal);
|
||||
|
||||
if (poll_toggle_bit(ulSectorOff) < 0)
|
||||
return FLASH_FAIL;
|
||||
printf(".");
|
||||
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
void unlock_flash(long ulOffset)
|
||||
{
|
||||
unsigned long ulOffsetAddr = ulOffset;
|
||||
ulOffsetAddr &= 0xFFFF0000;
|
||||
|
||||
write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
|
||||
write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
|
||||
write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
|
||||
}
|
||||
|
||||
int get_codes()
|
||||
{
|
||||
int dev_id = 0;
|
||||
|
||||
write_flash(WRITESEQ1, GETCODEDATA1);
|
||||
write_flash(WRITESEQ2, GETCODEDATA2);
|
||||
write_flash(WRITESEQ3, GETCODEDATA3);
|
||||
|
||||
read_flash(0x0402, &dev_id);
|
||||
dev_id &= 0x0000FFFF;
|
||||
|
||||
reset_flash();
|
||||
|
||||
return dev_id;
|
||||
}
|
||||
|
||||
void get_sector_number(long ulOffset, int *pnSector)
|
||||
{
|
||||
int nSector = 0;
|
||||
long lMainEnd = 0x400000;
|
||||
long lBootEnd = 0x10000;
|
||||
|
||||
// sector numbers for the FLASH A boot sectors
|
||||
if (ulOffset < lBootEnd) {
|
||||
nSector = (int)ulOffset / AFP_SectorSize1;
|
||||
}
|
||||
// sector numbers for the FLASH B boot sectors
|
||||
else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) {
|
||||
nSector = ((ulOffset / (AFP_SectorSize2)) + 7);
|
||||
}
|
||||
// if it is a valid sector, set it
|
||||
if ((nSector >= 0) && (nSector < AFP_NumSectors))
|
||||
*pnSector = nSector;
|
||||
|
||||
}
|
106
board/bf537-stamp/nand.c
Normal file
106
board/bf537-stamp/nand.c
Normal file
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
|
||||
#include <nand.h>
|
||||
|
||||
#define CONCAT(a,b,c,d) a ## b ## c ## d
|
||||
#define PORT(a,b) CONCAT(pPORT,a,b,)
|
||||
|
||||
#ifndef CONFIG_NAND_GPIO_PORT
|
||||
#define CONFIG_NAND_GPIO_PORT F
|
||||
#endif
|
||||
|
||||
/*
|
||||
* hardware specific access to control-lines
|
||||
*/
|
||||
static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
|
||||
{
|
||||
register struct nand_chip *this = mtd->priv;
|
||||
|
||||
switch (cmd) {
|
||||
|
||||
case NAND_CTL_SETCLE:
|
||||
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
|
||||
break;
|
||||
case NAND_CTL_CLRCLE:
|
||||
this->IO_ADDR_W = CFG_NAND_BASE;
|
||||
break;
|
||||
|
||||
case NAND_CTL_SETALE:
|
||||
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
|
||||
break;
|
||||
case NAND_CTL_CLRALE:
|
||||
this->IO_ADDR_W = CFG_NAND_BASE;
|
||||
break;
|
||||
case NAND_CTL_SETNCE:
|
||||
case NAND_CTL_CLRNCE:
|
||||
break;
|
||||
}
|
||||
|
||||
this->IO_ADDR_R = this->IO_ADDR_W;
|
||||
|
||||
/* Drain the writebuffer */
|
||||
sync();
|
||||
}
|
||||
|
||||
int bfin_device_ready(struct mtd_info *mtd)
|
||||
{
|
||||
int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
|
||||
sync();
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Board-specific NAND initialization. The following members of the
|
||||
* argument are board-specific (per include/linux/mtd/nand.h):
|
||||
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
|
||||
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
|
||||
* - hwcontrol: hardwarespecific function for accesing control-lines
|
||||
* - dev_ready: hardwarespecific function for accesing device ready/busy line
|
||||
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
|
||||
* only be provided if a hardware ECC is available
|
||||
* - eccmode: mode of ecc, see defines
|
||||
* - chip_delay: chip dependent delay for transfering data from array to
|
||||
* read regs (tR)
|
||||
* - options: various chip options. They can partly be set to inform
|
||||
* nand_scan about special functionality. See the defines for further
|
||||
* explanation
|
||||
* Members with a "?" were not set in the merged testing-NAND branch,
|
||||
* so they are not set here either.
|
||||
*/
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
|
||||
*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
|
||||
*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
|
||||
|
||||
nand->hwcontrol = bfin_hwcontrol;
|
||||
nand->eccmode = NAND_ECC_SOFT;
|
||||
nand->dev_ready = bfin_device_ready;
|
||||
nand->chip_delay = 30;
|
||||
}
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
|
322
board/bf537-stamp/post-memory.c
Normal file
322
board/bf537-stamp/post-memory.c
Normal file
|
@ -0,0 +1,322 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
|
||||
#include <post.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#if CONFIG_POST & CFG_POST_MEMORY
|
||||
#define CLKIN 25000000
|
||||
#define PATTERN1 0x5A5A5A5A
|
||||
#define PATTERN2 0xAAAAAAAA
|
||||
|
||||
#define CCLK_NUM 4
|
||||
#define SCLK_NUM 3
|
||||
|
||||
void post_out_buff(char *buff);
|
||||
int post_key_pressed(void);
|
||||
void post_init_pll(int mult, int div);
|
||||
int post_init_sdram(int sclk);
|
||||
void post_init_uart(int sclk);
|
||||
|
||||
const int pll[CCLK_NUM][SCLK_NUM][2] = {
|
||||
{{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */
|
||||
{{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */
|
||||
{{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */
|
||||
{{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */
|
||||
};
|
||||
const char *const log[CCLK_NUM][SCLK_NUM] = {
|
||||
{"CCLK-500Mhz SCLK-125Mhz: Writing...\0",
|
||||
"CCLK-500Mhz SCLK-100Mhz: Writing...\0",
|
||||
"CCLK-500Mhz SCLK- 50Mhz: Writing...\0",},
|
||||
{"CCLK-400Mhz SCLK-100Mhz: Writing...\0",
|
||||
"CCLK-400Mhz SCLK- 80Mhz: Writing...\0",
|
||||
"CCLK-400Mhz SCLK- 50Mhz: Writing...\0",},
|
||||
{"CCLK-200Mhz SCLK-100Mhz: Writing...\0",
|
||||
"CCLK-200Mhz SCLK- 50Mhz: Writing...\0",
|
||||
"CCLK-200Mhz SCLK- 40Mhz: Writing...\0",},
|
||||
{"CCLK-100Mhz SCLK-100Mhz: Writing...\0",
|
||||
"CCLK-100Mhz SCLK- 50Mhz: Writing...\0",
|
||||
"CCLK-100Mhz SCLK- 25Mhz: Writing...\0",},
|
||||
};
|
||||
|
||||
int memory_post_test(int flags)
|
||||
{
|
||||
int addr;
|
||||
int m, n;
|
||||
int sclk, sclk_temp;
|
||||
int ret = 1;
|
||||
|
||||
sclk_temp = CLKIN / 1000000;
|
||||
sclk_temp = sclk_temp * CONFIG_VCO_MULT;
|
||||
for (sclk = 0; sclk_temp > 0; sclk++)
|
||||
sclk_temp -= CONFIG_SCLK_DIV;
|
||||
sclk = sclk * 1000000;
|
||||
post_init_uart(sclk);
|
||||
if (post_key_pressed() == 0)
|
||||
return 0;
|
||||
|
||||
for (m = 0; m < CCLK_NUM; m++) {
|
||||
for (n = 0; n < SCLK_NUM; n++) {
|
||||
/* Calculate the sclk */
|
||||
sclk_temp = CLKIN / 1000000;
|
||||
sclk_temp = sclk_temp * pll[m][n][0];
|
||||
for (sclk = 0; sclk_temp > 0; sclk++)
|
||||
sclk_temp -= pll[m][n][1];
|
||||
sclk = sclk * 1000000;
|
||||
|
||||
post_init_pll(pll[m][n][0], pll[m][n][1]);
|
||||
post_init_sdram(sclk);
|
||||
post_init_uart(sclk);
|
||||
post_out_buff("\n\r\0");
|
||||
post_out_buff(log[m][n]);
|
||||
for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
|
||||
*(unsigned long *)addr = PATTERN1;
|
||||
post_out_buff("Reading...\0");
|
||||
for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
|
||||
if ((*(unsigned long *)addr) != PATTERN1) {
|
||||
post_out_buff("Error\n\r\0");
|
||||
ret = 0;
|
||||
}
|
||||
}
|
||||
post_out_buff("OK\n\r\0");
|
||||
}
|
||||
}
|
||||
if (ret)
|
||||
post_out_buff("memory POST passed\n\r\0");
|
||||
else
|
||||
post_out_buff("memory POST failed\n\r\0");
|
||||
|
||||
post_out_buff("\n\r\n\r\0");
|
||||
return 1;
|
||||
}
|
||||
|
||||
void post_init_uart(int sclk)
|
||||
{
|
||||
int divisor;
|
||||
|
||||
for (divisor = 0; sclk > 0; divisor++)
|
||||
sclk -= 57600 * 16;
|
||||
|
||||
*pPORTF_FER = 0x000F;
|
||||
*pPORTH_FER = 0xFFFF;
|
||||
|
||||
*pUART_GCTL = 0x00;
|
||||
*pUART_LCR = 0x83;
|
||||
sync();
|
||||
*pUART_DLL = (divisor & 0xFF);
|
||||
sync();
|
||||
*pUART_DLH = ((divisor >> 8) & 0xFF);
|
||||
sync();
|
||||
*pUART_LCR = 0x03;
|
||||
sync();
|
||||
*pUART_GCTL = 0x01;
|
||||
sync();
|
||||
}
|
||||
|
||||
void post_out_buff(char *buff)
|
||||
{
|
||||
|
||||
int i = 0;
|
||||
for (i = 0; i < 0x80000; i++) ;
|
||||
i = 0;
|
||||
while ((buff[i] != '\0') && (i != 100)) {
|
||||
while (!(*pUART_LSR & 0x20)) ;
|
||||
*pUART_THR = buff[i];
|
||||
sync();
|
||||
i++;
|
||||
}
|
||||
for (i = 0; i < 0x80000; i++) ;
|
||||
}
|
||||
|
||||
/* Using sw10-PF5 as the hotkey */
|
||||
#define KEY_LOOP 0x80000
|
||||
#define KEY_DELAY 0x80
|
||||
int post_key_pressed(void)
|
||||
{
|
||||
int i, n;
|
||||
unsigned short value;
|
||||
|
||||
*pPORTF_FER &= ~PF5;
|
||||
*pPORTFIO_DIR &= ~PF5;
|
||||
*pPORTFIO_INEN |= PF5;
|
||||
sync();
|
||||
|
||||
post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
|
||||
for (i = 0; i < KEY_LOOP; i++) {
|
||||
value = *pPORTFIO & PF5;
|
||||
if (*pUART0_RBR == 0x0D) {
|
||||
value = 0;
|
||||
goto key_pressed;
|
||||
}
|
||||
if (value != 0) {
|
||||
goto key_pressed;
|
||||
}
|
||||
for (n = 0; n < KEY_DELAY; n++)
|
||||
asm("nop");
|
||||
}
|
||||
post_out_buff("\b2\0");
|
||||
|
||||
for (i = 0; i < KEY_LOOP; i++) {
|
||||
value = *pPORTFIO & PF5;
|
||||
if (*pUART0_RBR == 0x0D) {
|
||||
value = 0;
|
||||
goto key_pressed;
|
||||
}
|
||||
if (value != 0) {
|
||||
goto key_pressed;
|
||||
}
|
||||
for (n = 0; n < KEY_DELAY; n++)
|
||||
asm("nop");
|
||||
}
|
||||
post_out_buff("\b1\0");
|
||||
|
||||
for (i = 0; i < KEY_LOOP; i++) {
|
||||
value = *pPORTFIO & PF5;
|
||||
if (*pUART0_RBR == 0x0D) {
|
||||
value = 0;
|
||||
goto key_pressed;
|
||||
}
|
||||
if (value != 0) {
|
||||
goto key_pressed;
|
||||
}
|
||||
for (n = 0; n < KEY_DELAY; n++)
|
||||
asm("nop");
|
||||
}
|
||||
key_pressed:
|
||||
post_out_buff("\b0");
|
||||
post_out_buff("\n\r\0");
|
||||
if (value == 0)
|
||||
return 0;
|
||||
post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
|
||||
return 1;
|
||||
}
|
||||
|
||||
void post_init_pll(int mult, int div)
|
||||
{
|
||||
|
||||
*pSIC_IWR = 0x01;
|
||||
*pPLL_CTL = (mult << 9);
|
||||
*pPLL_DIV = div;
|
||||
asm("CLI R2;");
|
||||
asm("IDLE;");
|
||||
asm("STI R2;");
|
||||
while (!(*pPLL_STAT & 0x20)) ;
|
||||
}
|
||||
|
||||
int post_init_sdram(int sclk)
|
||||
{
|
||||
int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
|
||||
SDRAM_tWR;
|
||||
int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
|
||||
mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
|
||||
|
||||
if ((sclk > 119402985)) {
|
||||
SDRAM_tRP = TRP_2;
|
||||
SDRAM_tRP_num = 2;
|
||||
SDRAM_tRAS = TRAS_7;
|
||||
SDRAM_tRAS_num = 7;
|
||||
SDRAM_tRCD = TRCD_2;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if ((sclk > 104477612) && (sclk <= 119402985)) {
|
||||
SDRAM_tRP = TRP_2;
|
||||
SDRAM_tRP_num = 2;
|
||||
SDRAM_tRAS = TRAS_6;
|
||||
SDRAM_tRAS_num = 6;
|
||||
SDRAM_tRCD = TRCD_2;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if ((sclk > 89552239) && (sclk <= 104477612)) {
|
||||
SDRAM_tRP = TRP_2;
|
||||
SDRAM_tRP_num = 2;
|
||||
SDRAM_tRAS = TRAS_5;
|
||||
SDRAM_tRAS_num = 5;
|
||||
SDRAM_tRCD = TRCD_2;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if ((sclk > 74626866) && (sclk <= 89552239)) {
|
||||
SDRAM_tRP = TRP_2;
|
||||
SDRAM_tRP_num = 2;
|
||||
SDRAM_tRAS = TRAS_4;
|
||||
SDRAM_tRAS_num = 4;
|
||||
SDRAM_tRCD = TRCD_2;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if ((sclk > 66666667) && (sclk <= 74626866)) {
|
||||
SDRAM_tRP = TRP_2;
|
||||
SDRAM_tRP_num = 2;
|
||||
SDRAM_tRAS = TRAS_3;
|
||||
SDRAM_tRAS_num = 3;
|
||||
SDRAM_tRCD = TRCD_2;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if ((sclk > 59701493) && (sclk <= 66666667)) {
|
||||
SDRAM_tRP = TRP_1;
|
||||
SDRAM_tRP_num = 1;
|
||||
SDRAM_tRAS = TRAS_4;
|
||||
SDRAM_tRAS_num = 4;
|
||||
SDRAM_tRCD = TRCD_1;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if ((sclk > 44776119) && (sclk <= 59701493)) {
|
||||
SDRAM_tRP = TRP_1;
|
||||
SDRAM_tRP_num = 1;
|
||||
SDRAM_tRAS = TRAS_3;
|
||||
SDRAM_tRAS_num = 3;
|
||||
SDRAM_tRCD = TRCD_1;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if ((sclk > 29850746) && (sclk <= 44776119)) {
|
||||
SDRAM_tRP = TRP_1;
|
||||
SDRAM_tRP_num = 1;
|
||||
SDRAM_tRAS = TRAS_2;
|
||||
SDRAM_tRAS_num = 2;
|
||||
SDRAM_tRCD = TRCD_1;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else if (sclk <= 29850746) {
|
||||
SDRAM_tRP = TRP_1;
|
||||
SDRAM_tRP_num = 1;
|
||||
SDRAM_tRAS = TRAS_1;
|
||||
SDRAM_tRAS_num = 1;
|
||||
SDRAM_tRCD = TRCD_1;
|
||||
SDRAM_tWR = TWR_2;
|
||||
} else {
|
||||
SDRAM_tRP = TRP_1;
|
||||
SDRAM_tRP_num = 1;
|
||||
SDRAM_tRAS = TRAS_1;
|
||||
SDRAM_tRAS_num = 1;
|
||||
SDRAM_tRCD = TRCD_1;
|
||||
SDRAM_tWR = TWR_2;
|
||||
}
|
||||
/*SDRAM INFORMATION: */
|
||||
SDRAM_Tref = 64; /* Refresh period in milliseconds */
|
||||
SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
|
||||
SDRAM_CL = CL_3; /* 2 */
|
||||
|
||||
SDRAM_SIZE = EBSZ_64;
|
||||
SDRAM_WIDTH = EBCAW_10;
|
||||
|
||||
mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
|
||||
|
||||
/* Equation from section 17 (p17-46) of BF533 HRM */
|
||||
mem_SDRRC =
|
||||
(((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
|
||||
(SDRAM_tRAS_num + SDRAM_tRP_num);
|
||||
|
||||
/* Enable SCLK Out */
|
||||
mem_SDGCTL =
|
||||
(SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
|
||||
| PSS);
|
||||
|
||||
sync();
|
||||
|
||||
*pEBIU_SDGCTL |= 0x1000000;
|
||||
/* Set the SDRAM Refresh Rate control register based on SSCLK value */
|
||||
*pEBIU_SDRRC = mem_SDRRC;
|
||||
|
||||
/* SDRAM Memory Bank Control Register */
|
||||
*pEBIU_SDBCTL = mem_SDBCTL;
|
||||
|
||||
/* SDRAM Memory Global Control Register */
|
||||
*pEBIU_SDGCTL = mem_SDGCTL;
|
||||
sync();
|
||||
return mem_SDRRC;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_POST & CFG_POST_MEMORY */
|
||||
#endif /* CONFIG_POST */
|
515
board/bf537-stamp/stm_m25p64.c
Normal file
515
board/bf537-stamp/stm_m25p64.c
Normal file
|
@ -0,0 +1,515 @@
|
|||
/****************************************************************************
|
||||
* SPI flash driver for M25P64
|
||||
****************************************************************************/
|
||||
#include <common.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(CONFIG_SPI)
|
||||
|
||||
/* Application definitions */
|
||||
|
||||
#define NUM_SECTORS 128 /* number of sectors */
|
||||
#define SECTOR_SIZE 0x10000
|
||||
#define NOP_NUM 1000
|
||||
|
||||
#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /* Settings to the SPI_CTL */
|
||||
#define TIMOD01 (0x01) /* stes the SPI to work with core instructions */
|
||||
|
||||
/* Flash commands */
|
||||
#define SPI_WREN (0x06) /*Set Write Enable Latch */
|
||||
#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
|
||||
#define SPI_RDSR (0x05) /*Read Status Register */
|
||||
#define SPI_WRSR (0x01) /*Write Status Register */
|
||||
#define SPI_READ (0x03) /*Read data from memory */
|
||||
#define SPI_FAST_READ (0x0B) /*Read data from memory */
|
||||
#define SPI_PP (0x02) /*Program Data into memory */
|
||||
#define SPI_SE (0xD8) /*Erase one sector in memory */
|
||||
#define SPI_BE (0xC7) /*Erase all memory */
|
||||
#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
|
||||
#define WEL (0x2) /*Check the write enable bit of the SPI status register */
|
||||
|
||||
#define TIMEOUT 350000000
|
||||
|
||||
typedef enum {
|
||||
NO_ERR,
|
||||
POLL_TIMEOUT,
|
||||
INVALID_SECTOR,
|
||||
INVALID_BLOCK,
|
||||
} ERROR_CODE;
|
||||
|
||||
void spi_init_f(void);
|
||||
void spi_init_r(void);
|
||||
ssize_t spi_read(uchar *, int, uchar *, int);
|
||||
ssize_t spi_write(uchar *, int, uchar *, int);
|
||||
|
||||
char ReadStatusRegister(void);
|
||||
void Wait_For_SPIF(void);
|
||||
void SetupSPI(const int spi_setting);
|
||||
void SPI_OFF(void);
|
||||
void SendSingleCommand(const int iCommand);
|
||||
|
||||
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
|
||||
ERROR_CODE EraseBlock(int nBlock);
|
||||
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
|
||||
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
|
||||
ERROR_CODE Wait_For_Status(char Statusbit);
|
||||
ERROR_CODE Wait_For_WEL(void);
|
||||
|
||||
/*
|
||||
* Function: spi_init_f
|
||||
* Description: Init SPI-Controller (ROM part)
|
||||
* return: ---
|
||||
*/
|
||||
void spi_init_f(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Function: spi_init_r
|
||||
* Description: Init SPI-Controller (RAM part) -
|
||||
* The malloc engine is ready and we can move our buffers to
|
||||
* normal RAM
|
||||
* return: ---
|
||||
*/
|
||||
void spi_init_r(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function: spi_write
|
||||
*/
|
||||
ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
unsigned long offset;
|
||||
int start_block, end_block;
|
||||
int start_byte, end_byte;
|
||||
ERROR_CODE result = NO_ERR;
|
||||
uchar temp[SECTOR_SIZE];
|
||||
int i, num;
|
||||
|
||||
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
|
||||
/* Get the start block number */
|
||||
result = GetSectorNumber(offset, &start_block);
|
||||
if (result == INVALID_SECTOR) {
|
||||
printf("Invalid sector! ");
|
||||
return 0;
|
||||
}
|
||||
/* Get the end block number */
|
||||
result = GetSectorNumber(offset + len - 1, &end_block);
|
||||
if (result == INVALID_SECTOR) {
|
||||
printf("Invalid sector! ");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (num = start_block; num <= end_block; num++) {
|
||||
ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
|
||||
start_byte = num * SECTOR_SIZE;
|
||||
end_byte = (num + 1) * SECTOR_SIZE - 1;
|
||||
if (start_byte < offset)
|
||||
start_byte = offset;
|
||||
if (end_byte > (offset + len))
|
||||
end_byte = (offset + len - 1);
|
||||
for (i = start_byte; i <= end_byte; i++)
|
||||
temp[i - num * SECTOR_SIZE] = buffer[i - offset];
|
||||
EraseBlock(num);
|
||||
result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
|
||||
if (result != NO_ERR)
|
||||
return 0;
|
||||
printf(".");
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function: spi_read
|
||||
*/
|
||||
ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
unsigned long offset;
|
||||
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
|
||||
ReadData(offset, len, (int *)buffer);
|
||||
return len;
|
||||
}
|
||||
|
||||
void SendSingleCommand(const int iCommand)
|
||||
{
|
||||
unsigned short dummy;
|
||||
|
||||
/* turns on the SPI in single write mode */
|
||||
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
|
||||
|
||||
/* sends the actual command to the SPI TX register */
|
||||
*pSPI_TDBR = iCommand;
|
||||
sync();
|
||||
|
||||
/* The SPI status register will be polled to check the SPIF bit */
|
||||
Wait_For_SPIF();
|
||||
|
||||
dummy = *pSPI_RDBR;
|
||||
|
||||
/* The SPI will be turned off */
|
||||
SPI_OFF();
|
||||
|
||||
}
|
||||
|
||||
void SetupSPI(const int spi_setting)
|
||||
{
|
||||
|
||||
if (icache_status() || dcache_status())
|
||||
udelay(CONFIG_CCLK_HZ / 50000000);
|
||||
/*sets up the PF10 to be the slave select of the SPI */
|
||||
*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
|
||||
*pSPI_FLG = 0xFF02;
|
||||
*pSPI_BAUD = CONFIG_SPI_BAUD;
|
||||
*pSPI_CTL = spi_setting;
|
||||
sync();
|
||||
|
||||
*pSPI_FLG = 0xFD02;
|
||||
sync();
|
||||
}
|
||||
|
||||
void SPI_OFF(void)
|
||||
{
|
||||
|
||||
*pSPI_CTL = 0x0400; /* disable SPI */
|
||||
*pSPI_FLG = 0;
|
||||
*pSPI_BAUD = 0;
|
||||
sync();
|
||||
udelay(CONFIG_CCLK_HZ / 50000000);
|
||||
|
||||
}
|
||||
|
||||
void Wait_For_SPIF(void)
|
||||
{
|
||||
unsigned short dummyread;
|
||||
while ((*pSPI_STAT & TXS)) ;
|
||||
while (!(*pSPI_STAT & SPIF)) ;
|
||||
while (!(*pSPI_STAT & RXS)) ;
|
||||
/* Read dummy to empty the receive register */
|
||||
dummyread = *pSPI_RDBR;
|
||||
}
|
||||
|
||||
ERROR_CODE Wait_For_WEL(void)
|
||||
{
|
||||
int i;
|
||||
char status_register = 0;
|
||||
ERROR_CODE ErrorCode = NO_ERR;
|
||||
|
||||
for (i = 0; i < TIMEOUT; i++) {
|
||||
status_register = ReadStatusRegister();
|
||||
if ((status_register & WEL)) {
|
||||
ErrorCode = NO_ERR;
|
||||
break;
|
||||
}
|
||||
ErrorCode = POLL_TIMEOUT; /* Time out error */
|
||||
};
|
||||
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
ERROR_CODE Wait_For_Status(char Statusbit)
|
||||
{
|
||||
int i;
|
||||
char status_register = 0xFF;
|
||||
ERROR_CODE ErrorCode = NO_ERR;
|
||||
|
||||
for (i = 0; i < TIMEOUT; i++) {
|
||||
status_register = ReadStatusRegister();
|
||||
if (!(status_register & Statusbit)) {
|
||||
ErrorCode = NO_ERR;
|
||||
break;
|
||||
}
|
||||
ErrorCode = POLL_TIMEOUT; /* Time out error */
|
||||
};
|
||||
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
char ReadStatusRegister(void)
|
||||
{
|
||||
char status_register = 0;
|
||||
|
||||
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
|
||||
|
||||
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
|
||||
sync();
|
||||
Wait_For_SPIF(); /*wait until the instruction has been sent */
|
||||
*pSPI_TDBR = 0; /*send dummy to receive the status register */
|
||||
sync();
|
||||
Wait_For_SPIF(); /*wait until the data has been sent */
|
||||
status_register = *pSPI_RDBR; /*read the status register */
|
||||
|
||||
SPI_OFF(); /* Turn off the SPI */
|
||||
|
||||
return status_register;
|
||||
}
|
||||
|
||||
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
|
||||
{
|
||||
int nSector = 0;
|
||||
ERROR_CODE ErrorCode = NO_ERR;
|
||||
|
||||
if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
|
||||
ErrorCode = INVALID_SECTOR;
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
nSector = (int)ulOffset / 0x10000;
|
||||
*pnSector = nSector;
|
||||
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
ERROR_CODE EraseBlock(int nBlock)
|
||||
{
|
||||
unsigned long ulSectorOff = 0x0, ShiftValue;
|
||||
ERROR_CODE ErrorCode = NO_ERR;
|
||||
|
||||
/* if the block is invalid just return */
|
||||
if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
|
||||
ErrorCode = INVALID_BLOCK;
|
||||
return ErrorCode;
|
||||
}
|
||||
/* figure out the offset of the block in flash */
|
||||
if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
|
||||
ulSectorOff = (nBlock * SECTOR_SIZE);
|
||||
|
||||
} else {
|
||||
ErrorCode = INVALID_BLOCK;
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
/* A write enable instruction must previously have been executed */
|
||||
SendSingleCommand(SPI_WREN);
|
||||
|
||||
/* The status register will be polled to check the write enable latch "WREN" */
|
||||
ErrorCode = Wait_For_WEL();
|
||||
|
||||
if (POLL_TIMEOUT == ErrorCode) {
|
||||
printf("SPI Erase block error\n");
|
||||
return ErrorCode;
|
||||
} else
|
||||
|
||||
/* Turn on the SPI to send single commands */
|
||||
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
|
||||
|
||||
/*
|
||||
* Send the erase block command to the flash followed by the 24 address
|
||||
* to point to the start of a sector
|
||||
*/
|
||||
*pSPI_TDBR = SPI_SE;
|
||||
sync();
|
||||
Wait_For_SPIF();
|
||||
/* Send the highest byte of the 24 bit address at first */
|
||||
ShiftValue = (ulSectorOff >> 16);
|
||||
*pSPI_TDBR = ShiftValue;
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
/* Send the middle byte of the 24 bit address at second */
|
||||
ShiftValue = (ulSectorOff >> 8);
|
||||
*pSPI_TDBR = ShiftValue;
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
/* Send the lowest byte of the 24 bit address finally */
|
||||
*pSPI_TDBR = ulSectorOff;
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
|
||||
/* Turns off the SPI */
|
||||
SPI_OFF();
|
||||
|
||||
/* Poll the status register to check the Write in Progress bit */
|
||||
/* Sector erase takes time */
|
||||
ErrorCode = Wait_For_Status(WIP);
|
||||
|
||||
/* block erase should be complete */
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
/*
|
||||
* ERROR_CODE ReadData()
|
||||
* Read a value from flash for verify purpose
|
||||
* Inputs: unsigned long ulStart - holds the SPI start address
|
||||
* int pnData - pointer to store value read from flash
|
||||
* long lCount - number of elements to read
|
||||
*/
|
||||
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
|
||||
{
|
||||
unsigned long ShiftValue;
|
||||
char *cnData;
|
||||
int i;
|
||||
|
||||
/* Pointer cast to be able to increment byte wise */
|
||||
|
||||
cnData = (char *)pnData;
|
||||
/* Start SPI interface */
|
||||
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH_FAST_READ
|
||||
/* Send the read command to SPI device */
|
||||
*pSPI_TDBR = SPI_FAST_READ;
|
||||
#else
|
||||
/* Send the read command to SPI device */
|
||||
*pSPI_TDBR = SPI_READ;
|
||||
#endif
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
/* Send the highest byte of the 24 bit address at first */
|
||||
ShiftValue = (ulStart >> 16);
|
||||
/* Send the byte to the SPI device */
|
||||
*pSPI_TDBR = ShiftValue;
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
/* Send the middle byte of the 24 bit address at second */
|
||||
ShiftValue = (ulStart >> 8);
|
||||
/* Send the byte to the SPI device */
|
||||
*pSPI_TDBR = ShiftValue;
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
/* Send the lowest byte of the 24 bit address finally */
|
||||
*pSPI_TDBR = ulStart;
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH_FAST_READ
|
||||
/* Send dummy for FAST_READ */
|
||||
*pSPI_TDBR = 0;
|
||||
sync();
|
||||
/* Wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
#endif
|
||||
|
||||
/* After the SPI device address has been placed on the MOSI pin the data can be */
|
||||
/* received on the MISO pin. */
|
||||
for (i = 0; i < lCount; i++) {
|
||||
*pSPI_TDBR = 0;
|
||||
sync();
|
||||
while (!(*pSPI_STAT & RXS)) ;
|
||||
*cnData++ = *pSPI_RDBR;
|
||||
|
||||
if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
|
||||
printf(".");
|
||||
}
|
||||
|
||||
/* Turn off the SPI */
|
||||
SPI_OFF();
|
||||
|
||||
return NO_ERR;
|
||||
}
|
||||
|
||||
ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
|
||||
int *iDataSource, long *lWriteCount)
|
||||
{
|
||||
|
||||
unsigned long ulWAddr;
|
||||
long lWTransferCount = 0;
|
||||
int i;
|
||||
char iData;
|
||||
char *temp = (char *)iDataSource;
|
||||
ERROR_CODE ErrorCode = NO_ERR;
|
||||
|
||||
/* First, a Write Enable Command must be sent to the SPI. */
|
||||
SendSingleCommand(SPI_WREN);
|
||||
|
||||
/*
|
||||
* Second, the SPI Status Register will be tested whether the
|
||||
* Write Enable Bit has been set
|
||||
*/
|
||||
ErrorCode = Wait_For_WEL();
|
||||
if (POLL_TIMEOUT == ErrorCode) {
|
||||
printf("SPI Write Time Out\n");
|
||||
return ErrorCode;
|
||||
} else
|
||||
/* Third, the 24 bit address will be shifted out
|
||||
* the SPI MOSI bytewise.
|
||||
* Turns the SPI on
|
||||
*/
|
||||
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
|
||||
*pSPI_TDBR = SPI_PP;
|
||||
sync();
|
||||
/*wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
ulWAddr = (ulStartAddr >> 16);
|
||||
*pSPI_TDBR = ulWAddr;
|
||||
sync();
|
||||
/*wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
ulWAddr = (ulStartAddr >> 8);
|
||||
*pSPI_TDBR = ulWAddr;
|
||||
sync();
|
||||
/*wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
ulWAddr = ulStartAddr;
|
||||
*pSPI_TDBR = ulWAddr;
|
||||
sync();
|
||||
/*wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
/*
|
||||
* Fourth, maximum number of 256 bytes will be taken from the Buffer
|
||||
* and sent to the SPI device.
|
||||
*/
|
||||
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
|
||||
iData = *temp;
|
||||
*pSPI_TDBR = iData;
|
||||
sync();
|
||||
/*wait until the instruction has been sent */
|
||||
Wait_For_SPIF();
|
||||
temp++;
|
||||
}
|
||||
|
||||
/* Turns the SPI off */
|
||||
SPI_OFF();
|
||||
|
||||
/*
|
||||
* Sixth, the SPI Write in Progress Bit must be toggled to ensure the
|
||||
* programming is done before start of next transfer
|
||||
*/
|
||||
ErrorCode = Wait_For_Status(WIP);
|
||||
|
||||
if (POLL_TIMEOUT == ErrorCode) {
|
||||
printf("SPI Program Time out!\n");
|
||||
return ErrorCode;
|
||||
} else
|
||||
|
||||
*lWriteCount = lWTransferCount;
|
||||
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
|
||||
{
|
||||
|
||||
unsigned long ulWStart = ulStart;
|
||||
long lWCount = lCount, lWriteCount;
|
||||
long *pnWriteCount = &lWriteCount;
|
||||
|
||||
ERROR_CODE ErrorCode = NO_ERR;
|
||||
|
||||
while (lWCount != 0) {
|
||||
ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
|
||||
|
||||
/*
|
||||
* After each function call of WriteFlash the counter
|
||||
* must be adjusted
|
||||
*/
|
||||
lWCount -= *pnWriteCount;
|
||||
|
||||
/* Also, both address pointers must be recalculated. */
|
||||
ulWStart += *pnWriteCount;
|
||||
pnData += *pnWriteCount / 4;
|
||||
}
|
||||
|
||||
/* return the appropriate error code */
|
||||
return ErrorCode;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SPI */
|
190
board/bf537-stamp/u-boot.lds.S
Normal file
190
board/bf537-stamp/u-boot.lds.S
Normal file
|
@ -0,0 +1,190 @@
|
|||
/*
|
||||
* U-boot - u-boot.lds.S
|
||||
*
|
||||
* Copyright (c) 2005-2007 Analog Device Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
OUTPUT_ARCH(bfin)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
MEMORY
|
||||
{
|
||||
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
|
||||
l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
|
||||
l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS; /*0x1000;*/
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
. = CFG_MONITOR_BASE;
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector before the environment sector. If it throws */
|
||||
/* an error during compilation remove an object here to get */
|
||||
/* it linked after the configuration sector. */
|
||||
|
||||
cpu/bf537/start.o (.text)
|
||||
cpu/bf537/start1.o (.text)
|
||||
cpu/bf537/traps.o (.text)
|
||||
cpu/bf537/interrupt.o (.text)
|
||||
cpu/bf537/serial.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
/* lib_blackfin/bf533_string.o (.text) */
|
||||
/* lib_generic/vsprintf.o (.text) */
|
||||
lib_generic/crc32.o (.text)
|
||||
/* lib_generic/zlib.o (.text) */
|
||||
/* board/bf537-stamp/bf537-stamp.o (.text) */
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
} > ram
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.text_l1 :
|
||||
{
|
||||
. = ALIGN(4) ;
|
||||
_text_l1 = .;
|
||||
PROVIDE (text_l1 = .);
|
||||
board/bf537-stamp/post-memory.o (.text)
|
||||
. = ALIGN(4) ;
|
||||
_etext_l1 = .;
|
||||
PROVIDE (etext_l1 = .);
|
||||
} > l1_code AT > ram
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata)
|
||||
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata1)
|
||||
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
. = ALIGN(4);
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_erodata = .;
|
||||
PROVIDE (erodata = .);
|
||||
.rodata_l1 :
|
||||
{
|
||||
. = ALIGN(4) ;
|
||||
_rodata_l1 = .;
|
||||
PROVIDE (rodata_l1 = .);
|
||||
board/bf537-stamp/post-memory.o (.rodata)
|
||||
board/bf537-stamp/post-memory.o (.rodata1)
|
||||
board/bf537-stamp/post-memory.o (.rodata.str1.4)
|
||||
. = ALIGN(4) ;
|
||||
_erodata_l1 = .;
|
||||
PROVIDE(erodata_l1 = .);
|
||||
} > l1_data AT > ram
|
||||
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
} > ram
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
___u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) } > ram
|
||||
___u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
} > ram
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
52
cpu/bf537/Makefile
Normal file
52
cpu/bf537/Makefile
Normal file
|
@ -0,0 +1,52 @@
|
|||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(CPU).a
|
||||
|
||||
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
|
||||
COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o
|
||||
|
||||
EXTRA = init_sdram_bootrom_initblock.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
||||
all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
128
cpu/bf537/cache.S
Normal file
128
cpu/bf537/cache.S
Normal file
|
@ -0,0 +1,128 @@
|
|||
#define ASSEMBLY
|
||||
#include <asm/linkage.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
.text
|
||||
.align 2
|
||||
ENTRY(_blackfin_icache_flush_range)
|
||||
R2 = -32;
|
||||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC;
|
||||
1:
|
||||
IFLUSH[P0++];
|
||||
CC = P0 < P1(iu);
|
||||
IF CC JUMP 1b(bp);
|
||||
IFLUSH[P0];
|
||||
SSYNC;
|
||||
RTS;
|
||||
|
||||
ENTRY(_blackfin_dcache_flush_range)
|
||||
R2 = -32;
|
||||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC;
|
||||
1:
|
||||
FLUSH[P0++];
|
||||
CC = P0 < P1(iu);
|
||||
IF CC JUMP 1b(bp);
|
||||
FLUSH[P0];
|
||||
SSYNC;
|
||||
RTS;
|
||||
|
||||
ENTRY(_icache_invalidate)
|
||||
ENTRY(_invalidate_entire_icache)
|
||||
[--SP] = (R7:5);
|
||||
|
||||
P0.L = (IMEM_CONTROL & 0xFFFF);
|
||||
P0.H = (IMEM_CONTROL >> 16);
|
||||
R7 =[P0];
|
||||
|
||||
/*
|
||||
* Clear the IMC bit , All valid bits in the instruction
|
||||
* cache are set to the invalid state
|
||||
*/
|
||||
BITCLR(R7, IMC_P);
|
||||
CLI R6;
|
||||
/* SSYNC required before invalidating cache. */
|
||||
SSYNC;
|
||||
.align 8;
|
||||
[P0] = R7;
|
||||
SSYNC;
|
||||
STI R6;
|
||||
|
||||
/* Configures the instruction cache agian */
|
||||
R6 = (IMC | ENICPLB);
|
||||
R7 = R7 | R6;
|
||||
|
||||
CLI R6;
|
||||
SSYNC;
|
||||
.align 8;
|
||||
[P0] = R7;
|
||||
SSYNC;
|
||||
STI R6;
|
||||
|
||||
(R7:5) =[SP++];
|
||||
RTS;
|
||||
|
||||
/*
|
||||
* Invalidate the Entire Data cache by
|
||||
* clearing DMC[1:0] bits
|
||||
*/
|
||||
ENTRY(_invalidate_entire_dcache)
|
||||
ENTRY(_dcache_invalidate)
|
||||
[--SP] = (R7:6);
|
||||
|
||||
P0.L = (DMEM_CONTROL & 0xFFFF);
|
||||
P0.H = (DMEM_CONTROL >> 16);
|
||||
R7 =[P0];
|
||||
|
||||
/*
|
||||
* Clear the DMC[1:0] bits, All valid bits in the data
|
||||
* cache are set to the invalid state
|
||||
*/
|
||||
BITCLR(R7, DMC0_P);
|
||||
BITCLR(R7, DMC1_P);
|
||||
CLI R6;
|
||||
SSYNC;
|
||||
.align 8;
|
||||
[P0] = R7;
|
||||
SSYNC;
|
||||
STI R6;
|
||||
/* Configures the data cache again */
|
||||
|
||||
R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
|
||||
R7 = R7 | R6;
|
||||
|
||||
CLI R6;
|
||||
SSYNC;
|
||||
.align 8;
|
||||
[P0] = R7;
|
||||
SSYNC;
|
||||
STI R6;
|
||||
|
||||
(R7:6) =[SP++];
|
||||
RTS;
|
||||
|
||||
ENTRY(_blackfin_dcache_invalidate_range)
|
||||
R2 = -32;
|
||||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC;
|
||||
1:
|
||||
FLUSHINV[P0++];
|
||||
CC = P0 < P1(iu);
|
||||
IF CC JUMP 1b(bp);
|
||||
|
||||
/*
|
||||
* If the data crosses a cache line, then we'll be pointing to
|
||||
* the last cache line, but won't have flushed/invalidated it yet, so do
|
||||
* one more.
|
||||
*/
|
||||
FLUSHINV[P0];
|
||||
SSYNC;
|
||||
RTS;
|
27
cpu/bf537/config.mk
Normal file
27
cpu/bf537/config.mk
Normal file
|
@ -0,0 +1,27 @@
|
|||
# U-boot - config.mk
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5
|
227
cpu/bf537/cpu.c
Normal file
227
cpu/bf537/cpu.c
Normal file
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* U-boot - cpu.c CPU specific functions
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <command.h>
|
||||
#include <asm/entry.h>
|
||||
#include <asm/cplb.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define CACHE_ON 1
|
||||
#define CACHE_OFF 0
|
||||
|
||||
extern unsigned int icplb_table[page_descriptor_table_size][2];
|
||||
extern unsigned int dcplb_table[page_descriptor_table_size][2];
|
||||
|
||||
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
|
||||
);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* These functions are just used to satisfy the linker */
|
||||
int cpu_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cleanup_before_linux(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void icache_enable(void)
|
||||
{
|
||||
unsigned int *I0, *I1;
|
||||
int i, j = 0;
|
||||
|
||||
if ((*pCHIPID >> 28) < 2)
|
||||
return;
|
||||
|
||||
/* Before enable icache, disable it first */
|
||||
icache_disable();
|
||||
I0 = (unsigned int *)ICPLB_ADDR0;
|
||||
I1 = (unsigned int *)ICPLB_DATA0;
|
||||
|
||||
/* make sure the locked ones go in first */
|
||||
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||
if (CPLB_LOCK & icplb_table[i][1]) {
|
||||
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||
icplb_table[i][0], icplb_table[i][1]);
|
||||
*I0++ = icplb_table[i][0];
|
||||
*I1++ = icplb_table[i][1];
|
||||
j++;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||
if (!(CPLB_LOCK & icplb_table[i][1])) {
|
||||
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||
icplb_table[i][0], icplb_table[i][1]);
|
||||
*I0++ = icplb_table[i][0];
|
||||
*I1++ = icplb_table[i][1];
|
||||
j++;
|
||||
if (j == 16) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill the rest with invalid entry */
|
||||
if (j <= 15) {
|
||||
for (; j < 16; j++) {
|
||||
debug("filling %i with 0", j);
|
||||
*I1++ = 0x0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
cli();
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
|
||||
sync();
|
||||
sti();
|
||||
}
|
||||
|
||||
void icache_disable(void)
|
||||
{
|
||||
if ((*pCHIPID >> 28) < 2)
|
||||
return;
|
||||
cli();
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
|
||||
sync();
|
||||
sti();
|
||||
}
|
||||
|
||||
int icache_status(void)
|
||||
{
|
||||
unsigned int value;
|
||||
value = *(unsigned int *)IMEM_CONTROL;
|
||||
|
||||
if (value & (IMC | ENICPLB))
|
||||
return CACHE_ON;
|
||||
else
|
||||
return CACHE_OFF;
|
||||
}
|
||||
|
||||
void dcache_enable(void)
|
||||
{
|
||||
unsigned int *I0, *I1;
|
||||
unsigned int temp;
|
||||
int i, j = 0;
|
||||
|
||||
/* Before enable dcache, disable it first */
|
||||
dcache_disable();
|
||||
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||
I1 = (unsigned int *)DCPLB_DATA0;
|
||||
|
||||
/* make sure the locked ones go in first */
|
||||
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||
if (CPLB_LOCK & dcplb_table[i][1]) {
|
||||
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||
dcplb_table[i][0], dcplb_table[i][1]);
|
||||
*I0++ = dcplb_table[i][0];
|
||||
*I1++ = dcplb_table[i][1];
|
||||
j++;
|
||||
} else {
|
||||
debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||
dcplb_table[i][0], dcplb_table[i][1]);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||
if (!(CPLB_LOCK & dcplb_table[i][1])) {
|
||||
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||
dcplb_table[i][0], dcplb_table[i][1]);
|
||||
*I0++ = dcplb_table[i][0];
|
||||
*I1++ = dcplb_table[i][1];
|
||||
j++;
|
||||
if (j == 16) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill the rest with invalid entry */
|
||||
if (j <= 15) {
|
||||
for (; j < 16; j++) {
|
||||
debug("filling %i with 0", j);
|
||||
*I1++ = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
cli();
|
||||
temp = *(unsigned int *)DMEM_CONTROL;
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)DMEM_CONTROL =
|
||||
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
|
||||
sync();
|
||||
sti();
|
||||
}
|
||||
|
||||
void dcache_disable(void)
|
||||
{
|
||||
unsigned int *I0, *I1;
|
||||
int i;
|
||||
|
||||
cli();
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)DMEM_CONTROL &=
|
||||
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
|
||||
sync();
|
||||
sti();
|
||||
|
||||
/* after disable dcache,
|
||||
* clear it so we don't confuse the next application
|
||||
*/
|
||||
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||
I1 = (unsigned int *)DCPLB_DATA0;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
*I0++ = 0x0;
|
||||
*I1++ = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
int dcache_status(void)
|
||||
{
|
||||
unsigned int value;
|
||||
value = *(unsigned int *)DMEM_CONTROL;
|
||||
|
||||
if (value & (ENDCPLB))
|
||||
return CACHE_ON;
|
||||
else
|
||||
return CACHE_OFF;
|
||||
}
|
66
cpu/bf537/cpu.h
Normal file
66
cpu/bf537/cpu.h
Normal file
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* U-boot - cpu.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _CPU_H_
|
||||
#define _CPU_H_
|
||||
|
||||
#include <command.h>
|
||||
|
||||
#define INTERNAL_IRQS (32)
|
||||
#define NUM_IRQ_NODES 16
|
||||
#define DEF_INTERRUPT_FLAGS 1
|
||||
#define MAX_TIM_LOAD 0xFFFFFFFF
|
||||
|
||||
void blackfin_irq_panic(int reason, struct pt_regs *reg);
|
||||
extern void dump(struct pt_regs *regs);
|
||||
void display_excp(void);
|
||||
asmlinkage void evt_nmi(void);
|
||||
asmlinkage void evt_exception(void);
|
||||
asmlinkage void trap(void);
|
||||
asmlinkage void evt_ivhw(void);
|
||||
asmlinkage void evt_rst(void);
|
||||
asmlinkage void evt_timer(void);
|
||||
asmlinkage void evt_evt7(void);
|
||||
asmlinkage void evt_evt8(void);
|
||||
asmlinkage void evt_evt9(void);
|
||||
asmlinkage void evt_evt10(void);
|
||||
asmlinkage void evt_evt11(void);
|
||||
asmlinkage void evt_evt12(void);
|
||||
asmlinkage void evt_evt13(void);
|
||||
asmlinkage void evt_soft_int1(void);
|
||||
asmlinkage void evt_system_call(void);
|
||||
void blackfin_irq_panic(int reason, struct pt_regs *regs);
|
||||
void blackfin_free_irq(unsigned int irq, void *dev_id);
|
||||
void call_isr(int irq, struct pt_regs *fp);
|
||||
void blackfin_do_irq(int vec, struct pt_regs *fp);
|
||||
void blackfin_init_IRQ(void);
|
||||
void blackfin_enable_irq(unsigned int irq);
|
||||
void blackfin_disable_irq(unsigned int irq);
|
||||
extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
|
||||
int blackfin_request_irq(unsigned int irq,
|
||||
void (*handler) (int, void *, struct pt_regs *),
|
||||
unsigned long flags, const char *devname,
|
||||
void *dev_id);
|
||||
void timer_init(void);
|
||||
#endif
|
403
cpu/bf537/flush.S
Normal file
403
cpu/bf537/flush.S
Normal file
|
@ -0,0 +1,403 @@
|
|||
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2004 LG SOft India. All Rights Reserved.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License.
|
||||
*/
|
||||
#define ASSEMBLY
|
||||
|
||||
#include <asm/linkage.h>
|
||||
#include <asm/cplb.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
.text
|
||||
|
||||
/* This is an external function being called by the user
|
||||
* application through __flush_cache_all. Currently this function
|
||||
* serves the purpose of flushing all the pending writes in
|
||||
* in the instruction cache.
|
||||
*/
|
||||
|
||||
ENTRY(_flush_instruction_cache)
|
||||
[--SP] = ( R7:6, P5:4 );
|
||||
LINK 12;
|
||||
SP += -12;
|
||||
P5.H = (ICPLB_ADDR0 >> 16);
|
||||
P5.L = (ICPLB_ADDR0 & 0xFFFF);
|
||||
P4.H = (ICPLB_DATA0 >> 16);
|
||||
P4.L = (ICPLB_DATA0 & 0xFFFF);
|
||||
R7 = CPLB_VALID | CPLB_L1_CHBL;
|
||||
R6 = 16;
|
||||
inext: R0 = [P5++];
|
||||
R1 = [P4++];
|
||||
[--SP] = RETS;
|
||||
CALL _icplb_flush; /* R0 = page, R1 = data*/
|
||||
RETS = [SP++];
|
||||
iskip: R6 += -1;
|
||||
CC = R6;
|
||||
IF CC JUMP inext;
|
||||
SSYNC;
|
||||
SP += 12;
|
||||
UNLINK;
|
||||
( R7:6, P5:4 ) = [SP++];
|
||||
RTS;
|
||||
|
||||
/* This is an internal function to flush all pending
|
||||
* writes in the cache associated with a particular ICPLB.
|
||||
*
|
||||
* R0 - page's start address
|
||||
* R1 - CPLB's data field.
|
||||
*/
|
||||
|
||||
.align 2
|
||||
ENTRY(_icplb_flush)
|
||||
[--SP] = ( R7:0, P5:0 );
|
||||
[--SP] = LC0;
|
||||
[--SP] = LT0;
|
||||
[--SP] = LB0;
|
||||
[--SP] = LC1;
|
||||
[--SP] = LT1;
|
||||
[--SP] = LB1;
|
||||
|
||||
/* If it's a 1K or 4K page, then it's quickest to
|
||||
* just systematically flush all the addresses in
|
||||
* the page, regardless of whether they're in the
|
||||
* cache, or dirty. If it's a 1M or 4M page, there
|
||||
* are too many addresses, and we have to search the
|
||||
* cache for lines corresponding to the page.
|
||||
*/
|
||||
|
||||
CC = BITTST(R1, 17); /* 1MB or 4MB */
|
||||
IF !CC JUMP iflush_whole_page;
|
||||
|
||||
/* We're only interested in the page's size, so extract
|
||||
* this from the CPLB (bits 17:16), and scale to give an
|
||||
* offset into the page_size and page_prefix tables.
|
||||
*/
|
||||
|
||||
R1 <<= 14;
|
||||
R1 >>= 30;
|
||||
R1 <<= 2;
|
||||
|
||||
/* We can also determine the sub-bank used, because this is
|
||||
* taken from bits 13:12 of the address.
|
||||
*/
|
||||
|
||||
R3 = ((12<<8)|2); /* Extraction pattern */
|
||||
nop; /* Anamoly 05000209 */
|
||||
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
|
||||
|
||||
/* Save in extraction pattern for later deposit. */
|
||||
R3.H = R4.L << 0;
|
||||
|
||||
/* So:
|
||||
* R0 = Page start
|
||||
* R1 = Page length (actually, offset into size/prefix tables)
|
||||
* R3 = sub-bank deposit values
|
||||
*
|
||||
* The cache has 2 Ways, and 64 sets, so we iterate through
|
||||
* the sets, accessing the tag for each Way, for our Bank and
|
||||
* sub-bank, looking for dirty, valid tags that match our
|
||||
* address prefix.
|
||||
*/
|
||||
|
||||
P5.L = (ITEST_COMMAND & 0xFFFF);
|
||||
P5.H = (ITEST_COMMAND >> 16);
|
||||
P4.L = (ITEST_DATA0 & 0xFFFF);
|
||||
P4.H = (ITEST_DATA0 >> 16);
|
||||
|
||||
P0.L = page_prefix_table;
|
||||
P0.H = page_prefix_table;
|
||||
P1 = R1;
|
||||
R5 = 0; /* Set counter*/
|
||||
P0 = P1 + P0;
|
||||
R4 = [P0]; /* This is the address prefix*/
|
||||
|
||||
/* We're reading (bit 1==0) the tag (bit 2==0), and we
|
||||
* don't care about which double-word, since we're only
|
||||
* fetching tags, so we only have to set Set, Bank,
|
||||
* Sub-bank and Way.
|
||||
*/
|
||||
|
||||
P2 = 4;
|
||||
LSETUP (ifs1, ife1) LC1 = P2;
|
||||
ifs1: P0 = 32; /* iterate over all sets*/
|
||||
LSETUP (ifs0, ife0) LC0 = P0;
|
||||
ifs0: R6 = R5 << 5; /* Combine set*/
|
||||
R6.H = R3.H << 0 ; /* and sub-bank*/
|
||||
[P5] = R6; /* Issue Command*/
|
||||
SSYNC; /* CSYNC will not work here :(*/
|
||||
R7 = [P4]; /* and read Tag.*/
|
||||
CC = BITTST(R7, 0); /* Check if valid*/
|
||||
IF !CC JUMP ifskip; /* and skip if not.*/
|
||||
|
||||
/* Compare against the page address. First, plant bits 13:12
|
||||
* into the tag, since those aren't part of the returned data.
|
||||
*/
|
||||
|
||||
R7 = DEPOSIT(R7, R3); /* set 13:12*/
|
||||
R1 = R7 & R4; /* Mask off lower bits*/
|
||||
CC = R1 == R0; /* Compare against page start.*/
|
||||
IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
|
||||
|
||||
/* Tag address matches against page, so this is an entry
|
||||
* we must flush.
|
||||
*/
|
||||
|
||||
R7 >>= 10; /* Mask off the non-address bits*/
|
||||
R7 <<= 10;
|
||||
P3 = R7;
|
||||
IFLUSH [P3]; /* And flush the entry*/
|
||||
ifskip:
|
||||
ife0: R5 += 1; /* Advance to next Set*/
|
||||
ife1: NOP;
|
||||
|
||||
ifinished:
|
||||
SSYNC; /* Ensure the data gets out to mem.*/
|
||||
|
||||
/*Finished. Restore context.*/
|
||||
LB1 = [SP++];
|
||||
LT1 = [SP++];
|
||||
LC1 = [SP++];
|
||||
LB0 = [SP++];
|
||||
LT0 = [SP++];
|
||||
LC0 = [SP++];
|
||||
( R7:0, P5:0 ) = [SP++];
|
||||
RTS;
|
||||
|
||||
iflush_whole_page:
|
||||
/* It's a 1K or 4K page, so quicker to just flush the
|
||||
* entire page.
|
||||
*/
|
||||
|
||||
P1 = 32; /* For 1K pages*/
|
||||
P2 = P1 << 2; /* For 4K pages*/
|
||||
P0 = R0; /* Start of page*/
|
||||
CC = BITTST(R1, 16); /* Whether 1K or 4K*/
|
||||
IF CC P1 = P2;
|
||||
P1 += -1; /* Unroll one iteration*/
|
||||
SSYNC;
|
||||
IFLUSH [P0++]; /* because CSYNC can't end loops.*/
|
||||
LSETUP (isall, ieall) LC0 = P1;
|
||||
isall:IFLUSH [P0++];
|
||||
ieall: NOP;
|
||||
SSYNC;
|
||||
JUMP ifinished;
|
||||
|
||||
/* This is an external function being called by the user
|
||||
* application through __flush_cache_all. Currently this function
|
||||
* serves the purpose of flushing all the pending writes in
|
||||
* in the data cache.
|
||||
*/
|
||||
|
||||
ENTRY(_flush_data_cache)
|
||||
[--SP] = ( R7:6, P5:4 );
|
||||
LINK 12;
|
||||
SP += -12;
|
||||
P5.H = (DCPLB_ADDR0 >> 16);
|
||||
P5.L = (DCPLB_ADDR0 & 0xFFFF);
|
||||
P4.H = (DCPLB_DATA0 >> 16);
|
||||
P4.L = (DCPLB_DATA0 & 0xFFFF);
|
||||
R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
|
||||
R6 = 16;
|
||||
next: R0 = [P5++];
|
||||
R1 = [P4++];
|
||||
CC = BITTST(R1, 14); /* Is it write-through?*/
|
||||
IF CC JUMP skip; /* If so, ignore it.*/
|
||||
R2 = R1 & R7; /* Is it a dirty, cached page?*/
|
||||
CC = R2;
|
||||
IF !CC JUMP skip; /* If not, ignore it.*/
|
||||
[--SP] = RETS;
|
||||
CALL _dcplb_flush; /* R0 = page, R1 = data*/
|
||||
RETS = [SP++];
|
||||
skip: R6 += -1;
|
||||
CC = R6;
|
||||
IF CC JUMP next;
|
||||
SSYNC;
|
||||
SP += 12;
|
||||
UNLINK;
|
||||
( R7:6, P5:4 ) = [SP++];
|
||||
RTS;
|
||||
|
||||
/* This is an internal function to flush all pending
|
||||
* writes in the cache associated with a particular DCPLB.
|
||||
*
|
||||
* R0 - page's start address
|
||||
* R1 - CPLB's data field.
|
||||
*/
|
||||
|
||||
.align 2
|
||||
ENTRY(_dcplb_flush)
|
||||
[--SP] = ( R7:0, P5:0 );
|
||||
[--SP] = LC0;
|
||||
[--SP] = LT0;
|
||||
[--SP] = LB0;
|
||||
[--SP] = LC1;
|
||||
[--SP] = LT1;
|
||||
[--SP] = LB1;
|
||||
|
||||
/* If it's a 1K or 4K page, then it's quickest to
|
||||
* just systematically flush all the addresses in
|
||||
* the page, regardless of whether they're in the
|
||||
* cache, or dirty. If it's a 1M or 4M page, there
|
||||
* are too many addresses, and we have to search the
|
||||
* cache for lines corresponding to the page.
|
||||
*/
|
||||
|
||||
CC = BITTST(R1, 17); /* 1MB or 4MB */
|
||||
IF !CC JUMP dflush_whole_page;
|
||||
|
||||
/* We're only interested in the page's size, so extract
|
||||
* this from the CPLB (bits 17:16), and scale to give an
|
||||
* offset into the page_size and page_prefix tables.
|
||||
*/
|
||||
|
||||
R1 <<= 14;
|
||||
R1 >>= 30;
|
||||
R1 <<= 2;
|
||||
|
||||
/* The page could be mapped into Bank A or Bank B, depending
|
||||
* on (a) whether both banks are configured as cache, and
|
||||
* (b) on whether address bit A[x] is set. x is determined
|
||||
* by DCBS in DMEM_CONTROL
|
||||
*/
|
||||
|
||||
R2 = 0; /* Default to Bank A (Bank B would be 1)*/
|
||||
|
||||
P0.L = (DMEM_CONTROL & 0xFFFF);
|
||||
P0.H = (DMEM_CONTROL >> 16);
|
||||
|
||||
R3 = [P0]; /* If Bank B is not enabled as cache*/
|
||||
CC = BITTST(R3, 2); /* then Bank A is our only option.*/
|
||||
IF CC JUMP bank_chosen;
|
||||
|
||||
R4 = 1<<14; /* If DCBS==0, use A[14].*/
|
||||
R5 = R4 << 7; /* If DCBS==1, use A[23];*/
|
||||
CC = BITTST(R3, 4);
|
||||
IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
|
||||
R5 = R0 & R4; /* Use it to test the Page address*/
|
||||
CC = R5; /* and if that bit is set, we use Bank B,*/
|
||||
R2 = CC; /* else we use Bank A.*/
|
||||
R2 <<= 23; /* The Bank selection's at posn 23.*/
|
||||
|
||||
bank_chosen:
|
||||
|
||||
/* We can also determine the sub-bank used, because this is
|
||||
* taken from bits 13:12 of the address.
|
||||
*/
|
||||
|
||||
R3 = ((12<<8)|2); /* Extraction pattern */
|
||||
nop; /*Anamoly 05000209*/
|
||||
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
|
||||
/* Save in extraction pattern for later deposit.*/
|
||||
R3.H = R4.L << 0;
|
||||
|
||||
/* So:
|
||||
* R0 = Page start
|
||||
* R1 = Page length (actually, offset into size/prefix tables)
|
||||
* R2 = Bank select mask
|
||||
* R3 = sub-bank deposit values
|
||||
*
|
||||
* The cache has 2 Ways, and 64 sets, so we iterate through
|
||||
* the sets, accessing the tag for each Way, for our Bank and
|
||||
* sub-bank, looking for dirty, valid tags that match our
|
||||
* address prefix.
|
||||
*/
|
||||
|
||||
P5.L = (DTEST_COMMAND & 0xFFFF);
|
||||
P5.H = (DTEST_COMMAND >> 16);
|
||||
P4.L = (DTEST_DATA0 & 0xFFFF);
|
||||
P4.H = (DTEST_DATA0 >> 16);
|
||||
|
||||
P0.L = page_prefix_table;
|
||||
P0.H = page_prefix_table;
|
||||
P1 = R1;
|
||||
R5 = 0; /* Set counter*/
|
||||
P0 = P1 + P0;
|
||||
R4 = [P0]; /* This is the address prefix*/
|
||||
|
||||
|
||||
/* We're reading (bit 1==0) the tag (bit 2==0), and we
|
||||
* don't care about which double-word, since we're only
|
||||
* fetching tags, so we only have to set Set, Bank,
|
||||
* Sub-bank and Way.
|
||||
*/
|
||||
|
||||
P2 = 2;
|
||||
LSETUP (fs1, fe1) LC1 = P2;
|
||||
fs1: P0 = 64; /* iterate over all sets*/
|
||||
LSETUP (fs0, fe0) LC0 = P0;
|
||||
fs0: R6 = R5 << 5; /* Combine set*/
|
||||
R6.H = R3.H << 0 ; /* and sub-bank*/
|
||||
R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
|
||||
BITSET(R6,14);
|
||||
[P5] = R6; /* Issue Command*/
|
||||
SSYNC;
|
||||
R7 = [P4]; /* and read Tag.*/
|
||||
CC = BITTST(R7, 0); /* Check if valid*/
|
||||
IF !CC JUMP fskip; /* and skip if not.*/
|
||||
CC = BITTST(R7, 1); /* Check if dirty*/
|
||||
IF !CC JUMP fskip; /* and skip if not.*/
|
||||
|
||||
/* Compare against the page address. First, plant bits 13:12
|
||||
* into the tag, since those aren't part of the returned data.
|
||||
*/
|
||||
|
||||
R7 = DEPOSIT(R7, R3); /* set 13:12*/
|
||||
R1 = R7 & R4; /* Mask off lower bits*/
|
||||
CC = R1 == R0; /* Compare against page start.*/
|
||||
IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
|
||||
|
||||
/* Tag address matches against page, so this is an entry
|
||||
* we must flush.
|
||||
*/
|
||||
|
||||
R7 >>= 10; /* Mask off the non-address bits*/
|
||||
R7 <<= 10;
|
||||
P3 = R7;
|
||||
SSYNC;
|
||||
FLUSHINV [P3]; /* And flush the entry*/
|
||||
fskip:
|
||||
fe0: R5 += 1; /* Advance to next Set*/
|
||||
fe1: BITSET(R2, 26); /* Go to next Way.*/
|
||||
|
||||
dfinished:
|
||||
SSYNC; /* Ensure the data gets out to mem.*/
|
||||
|
||||
/*Finished. Restore context.*/
|
||||
LB1 = [SP++];
|
||||
LT1 = [SP++];
|
||||
LC1 = [SP++];
|
||||
LB0 = [SP++];
|
||||
LT0 = [SP++];
|
||||
LC0 = [SP++];
|
||||
( R7:0, P5:0 ) = [SP++];
|
||||
RTS;
|
||||
|
||||
dflush_whole_page:
|
||||
|
||||
/* It's a 1K or 4K page, so quicker to just flush the
|
||||
* entire page.
|
||||
*/
|
||||
|
||||
P1 = 32; /* For 1K pages*/
|
||||
P2 = P1 << 2; /* For 4K pages*/
|
||||
P0 = R0; /* Start of page*/
|
||||
CC = BITTST(R1, 16); /* Whether 1K or 4K*/
|
||||
IF CC P1 = P2;
|
||||
P1 += -1; /* Unroll one iteration*/
|
||||
SSYNC;
|
||||
FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
|
||||
LSETUP (eall, eall) LC0 = P1;
|
||||
eall: FLUSHINV [P0++];
|
||||
SSYNC;
|
||||
JUMP dfinished;
|
||||
|
||||
.align 4;
|
||||
page_prefix_table:
|
||||
.byte4 0xFFFFFC00; /* 1K */
|
||||
.byte4 0xFFFFF000; /* 4K */
|
||||
.byte4 0xFFF00000; /* 1M */
|
||||
.byte4 0xFFC00000; /* 4M */
|
||||
.page_prefix_table.end:
|
460
cpu/bf537/i2c.c
Normal file
460
cpu/bf537/i2c.c
Normal file
|
@ -0,0 +1,460 @@
|
|||
/****************************************************************
|
||||
* $ID: i2c.c 24 Oct 2006 12:00:00 +0800 $ *
|
||||
* *
|
||||
* Description: *
|
||||
* *
|
||||
* Maintainer: sonicz <sonic.zhang@analog.com> *
|
||||
* *
|
||||
* CopyRight (c) 2006 Analog Device *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* This file is free software; *
|
||||
* you are free to modify and/or redistribute it *
|
||||
* under the terms of the GNU General Public Licence (GPL).*
|
||||
* *
|
||||
****************************************************************/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define bfin_read16(addr) ({ unsigned __v; \
|
||||
__asm__ __volatile__ (\
|
||||
"%0 = w[%1] (z);\n\t"\
|
||||
: "=d"(__v) : "a"(addr)); (unsigned short)__v; })
|
||||
|
||||
#define bfin_write16(addr,val) ({\
|
||||
__asm__ __volatile__ (\
|
||||
"w[%0] = %1;\n\t"\
|
||||
: : "a"(addr) , "d"(val) : "memory");})
|
||||
|
||||
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
|
||||
#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
|
||||
#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
|
||||
#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
|
||||
#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
|
||||
#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
|
||||
#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
|
||||
#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
|
||||
#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
|
||||
#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
|
||||
#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
|
||||
#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
|
||||
#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
|
||||
#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
|
||||
#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
|
||||
#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
|
||||
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
|
||||
#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
|
||||
#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
|
||||
#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
|
||||
#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
|
||||
#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
|
||||
#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
|
||||
#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
|
||||
#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
|
||||
#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
|
||||
#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
|
||||
#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
|
||||
#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
|
||||
#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
|
||||
#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
|
||||
#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
|
||||
#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
|
||||
|
||||
#ifdef DEBUG_I2C
|
||||
#define PRINTD(fmt,args...) do { \
|
||||
DECLARE_GLOBAL_DATA_PTR; \
|
||||
if (gd->have_console) \
|
||||
printf(fmt ,##args); \
|
||||
} while (0)
|
||||
#else
|
||||
#define PRINTD(fmt,args...)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TWICLK_KHZ
|
||||
#define CONFIG_TWICLK_KHZ 50
|
||||
#endif
|
||||
|
||||
/* All transfers are described by this data structure */
|
||||
struct i2c_msg {
|
||||
u16 addr; /* slave address */
|
||||
u16 flags;
|
||||
#define I2C_M_STOP 0x2
|
||||
#define I2C_M_RD 0x1
|
||||
u16 len; /* msg length */
|
||||
u8 *buf; /* pointer to msg data */
|
||||
};
|
||||
|
||||
/**
|
||||
* i2c_reset: - reset the host controller
|
||||
*
|
||||
*/
|
||||
|
||||
static void i2c_reset(void)
|
||||
{
|
||||
/* Disable TWI */
|
||||
bfin_write_TWI_CONTROL(0);
|
||||
sync();
|
||||
|
||||
/* Set TWI internal clock as 10MHz */
|
||||
bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
|
||||
|
||||
/* Set Twi interface clock as specified */
|
||||
if (CONFIG_TWICLK_KHZ > 400)
|
||||
bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 /
|
||||
400) & 0xFF));
|
||||
else
|
||||
bfin_write_TWI_CLKDIV(((5 * 1024 /
|
||||
CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 /
|
||||
CONFIG_TWICLK_KHZ)
|
||||
& 0xFF));
|
||||
|
||||
/* Enable TWI */
|
||||
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
|
||||
sync();
|
||||
}
|
||||
|
||||
int wait_for_completion(struct i2c_msg *msg, int timeout_count)
|
||||
{
|
||||
unsigned short twi_int_stat;
|
||||
unsigned short mast_stat;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < timeout_count; i++) {
|
||||
twi_int_stat = bfin_read_TWI_INT_STAT();
|
||||
mast_stat = bfin_read_TWI_MASTER_STAT();
|
||||
|
||||
if (XMTSERV & twi_int_stat) {
|
||||
/* Transmit next data */
|
||||
if (msg->len > 0) {
|
||||
bfin_write_TWI_XMT_DATA8(*(msg->buf++));
|
||||
msg->len--;
|
||||
} else if (msg->flags & I2C_M_STOP)
|
||||
bfin_write_TWI_MASTER_CTL
|
||||
(bfin_read_TWI_MASTER_CTL() | STOP);
|
||||
sync();
|
||||
/* Clear status */
|
||||
bfin_write_TWI_INT_STAT(XMTSERV);
|
||||
sync();
|
||||
i = 0;
|
||||
}
|
||||
if (RCVSERV & twi_int_stat) {
|
||||
if (msg->len > 0) {
|
||||
/* Receive next data */
|
||||
*(msg->buf++) = bfin_read_TWI_RCV_DATA8();
|
||||
msg->len--;
|
||||
} else if (msg->flags & I2C_M_STOP) {
|
||||
bfin_write_TWI_MASTER_CTL
|
||||
(bfin_read_TWI_MASTER_CTL() | STOP);
|
||||
sync();
|
||||
}
|
||||
/* Clear interrupt source */
|
||||
bfin_write_TWI_INT_STAT(RCVSERV);
|
||||
sync();
|
||||
i = 0;
|
||||
}
|
||||
if (MERR & twi_int_stat) {
|
||||
bfin_write_TWI_INT_STAT(MERR);
|
||||
bfin_write_TWI_INT_MASK(0);
|
||||
bfin_write_TWI_MASTER_STAT(0x3e);
|
||||
bfin_write_TWI_MASTER_CTL(0);
|
||||
sync();
|
||||
/*
|
||||
* if both err and complete int stats are set,
|
||||
* return proper results.
|
||||
*/
|
||||
if (MCOMP & twi_int_stat) {
|
||||
bfin_write_TWI_INT_STAT(MCOMP);
|
||||
bfin_write_TWI_INT_MASK(0);
|
||||
bfin_write_TWI_MASTER_CTL(0);
|
||||
sync();
|
||||
/*
|
||||
* If it is a quick transfer,
|
||||
* only address bug no data, not an err.
|
||||
*/
|
||||
if (msg->len == 0 && mast_stat & BUFRDERR)
|
||||
return 0;
|
||||
/*
|
||||
* If address not acknowledged return -3,
|
||||
* else return 0.
|
||||
*/
|
||||
else if (!(mast_stat & ANAK))
|
||||
return 0;
|
||||
else
|
||||
return -3;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
if (MCOMP & twi_int_stat) {
|
||||
bfin_write_TWI_INT_STAT(MCOMP);
|
||||
sync();
|
||||
bfin_write_TWI_INT_MASK(0);
|
||||
bfin_write_TWI_MASTER_CTL(0);
|
||||
sync();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
if (msg->flags & I2C_M_RD)
|
||||
return -4;
|
||||
else
|
||||
return -2;
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_transfer: - Transfer one byte over the i2c bus
|
||||
*
|
||||
* This function can tranfer a byte over the i2c bus in both directions.
|
||||
* It is used by the public API functions.
|
||||
*
|
||||
* @return: 0: transfer successful
|
||||
* -1: transfer fail
|
||||
* -2: transmit timeout
|
||||
* -3: ACK missing
|
||||
* -4: receive timeout
|
||||
* -5: controller not ready
|
||||
*/
|
||||
int i2c_transfer(struct i2c_msg *msg)
|
||||
{
|
||||
int ret = 0;
|
||||
int timeout_count = 10000;
|
||||
int len = msg->len;
|
||||
|
||||
if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) {
|
||||
ret = -5;
|
||||
goto transfer_error;
|
||||
}
|
||||
|
||||
while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ;
|
||||
|
||||
/* Set Transmit device address */
|
||||
bfin_write_TWI_MASTER_ADDR(msg->addr);
|
||||
|
||||
/*
|
||||
* FIFO Initiation.
|
||||
* Data in FIFO should be discarded before start a new operation.
|
||||
*/
|
||||
bfin_write_TWI_FIFO_CTL(0x3);
|
||||
sync();
|
||||
bfin_write_TWI_FIFO_CTL(0);
|
||||
sync();
|
||||
|
||||
if (!(msg->flags & I2C_M_RD)) {
|
||||
/* Transmit first data */
|
||||
if (msg->len > 0) {
|
||||
PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf,
|
||||
len);
|
||||
bfin_write_TWI_XMT_DATA8(*(msg->buf++));
|
||||
msg->len--;
|
||||
sync();
|
||||
}
|
||||
}
|
||||
|
||||
/* clear int stat */
|
||||
bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV);
|
||||
|
||||
/* Interrupt mask . Enable XMT, RCV interrupt */
|
||||
bfin_write_TWI_INT_MASK(MCOMP | MERR |
|
||||
((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
|
||||
sync();
|
||||
|
||||
if (len > 0 && len <= 255)
|
||||
bfin_write_TWI_MASTER_CTL((len << 6));
|
||||
else if (msg->len > 255) {
|
||||
bfin_write_TWI_MASTER_CTL((0xff << 6));
|
||||
msg->flags &= I2C_M_STOP;
|
||||
} else
|
||||
bfin_write_TWI_MASTER_CTL(0);
|
||||
|
||||
/* Master enable */
|
||||
bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
|
||||
((msg->flags & I2C_M_RD)
|
||||
? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
|
||||
100) ? FAST : 0));
|
||||
sync();
|
||||
|
||||
ret = wait_for_completion(msg, timeout_count);
|
||||
PRINTD("3 in i2c_transfer: ret=%d\n", ret);
|
||||
|
||||
transfer_error:
|
||||
switch (ret) {
|
||||
case 1:
|
||||
PRINTD(("i2c_transfer: error: transfer fail\n"));
|
||||
break;
|
||||
case 2:
|
||||
PRINTD(("i2c_transfer: error: transmit timeout\n"));
|
||||
break;
|
||||
case 3:
|
||||
PRINTD(("i2c_transfer: error: ACK missing\n"));
|
||||
break;
|
||||
case 4:
|
||||
PRINTD(("i2c_transfer: error: receive timeout\n"));
|
||||
break;
|
||||
case 5:
|
||||
PRINTD(("i2c_transfer: error: controller not ready\n"));
|
||||
i2c_reset();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------*/
|
||||
/* API Functions */
|
||||
/* ---------------------------------------------------------------------*/
|
||||
|
||||
void i2c_init(int speed, int slaveaddr)
|
||||
{
|
||||
i2c_reset();
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_probe: - Test if a chip answers for a given i2c address
|
||||
*
|
||||
* @chip: address of the chip which is searched for
|
||||
* @return: 0 if a chip was found, -1 otherwhise
|
||||
*/
|
||||
|
||||
int i2c_probe(uchar chip)
|
||||
{
|
||||
struct i2c_msg msg;
|
||||
u8 probebuf;
|
||||
|
||||
i2c_reset();
|
||||
|
||||
probebuf = 0;
|
||||
msg.addr = chip;
|
||||
msg.flags = 0;
|
||||
msg.len = 1;
|
||||
msg.buf = &probebuf;
|
||||
if (i2c_transfer(&msg))
|
||||
return -1;
|
||||
|
||||
msg.addr = chip;
|
||||
msg.flags = I2C_M_RD;
|
||||
msg.len = 1;
|
||||
msg.buf = &probebuf;
|
||||
if (i2c_transfer(&msg))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_read: - Read multiple bytes from an i2c device
|
||||
*
|
||||
* chip: I2C chip address, range 0..127
|
||||
* addr: Memory (register) address within the chip
|
||||
* alen: Number of bytes to use for addr (typically 1, 2 for larger
|
||||
* memories, 0 for register type devices with only one
|
||||
* register)
|
||||
* buffer: Where to read/write the data
|
||||
* len: How many bytes to read/write
|
||||
*
|
||||
* Returns: 0 on success, not 0 on failure
|
||||
*/
|
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
struct i2c_msg msg;
|
||||
u8 addr_bytes[3]; /* lowest...highest byte of data address */
|
||||
|
||||
PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip,
|
||||
addr, alen, len);
|
||||
|
||||
if (alen > 0) {
|
||||
addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
|
||||
addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
|
||||
addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
|
||||
msg.addr = chip;
|
||||
msg.flags = 0;
|
||||
msg.len = alen;
|
||||
msg.buf = addr_bytes;
|
||||
if (i2c_transfer(&msg))
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* start read sequence */
|
||||
PRINTD(("i2c_read: start read sequence\n"));
|
||||
msg.addr = chip;
|
||||
msg.flags = I2C_M_RD;
|
||||
msg.len = len;
|
||||
msg.buf = buffer;
|
||||
if (i2c_transfer(&msg))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_write: - Write multiple bytes to an i2c device
|
||||
*
|
||||
* chip: I2C chip address, range 0..127
|
||||
* addr: Memory (register) address within the chip
|
||||
* alen: Number of bytes to use for addr (typically 1, 2 for larger
|
||||
* memories, 0 for register type devices with only one
|
||||
* register)
|
||||
* buffer: Where to read/write the data
|
||||
* len: How many bytes to read/write
|
||||
*
|
||||
* Returns: 0 on success, not 0 on failure
|
||||
*/
|
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
struct i2c_msg msg;
|
||||
u8 addr_bytes[3]; /* lowest...highest byte of data address */
|
||||
|
||||
PRINTD
|
||||
("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
|
||||
chip, addr, alen, len, buffer[0]);
|
||||
|
||||
/* chip address write */
|
||||
if (alen > 0) {
|
||||
addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
|
||||
addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
|
||||
addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
|
||||
msg.addr = chip;
|
||||
msg.flags = 0;
|
||||
msg.len = alen;
|
||||
msg.buf = addr_bytes;
|
||||
if (i2c_transfer(&msg))
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* start read sequence */
|
||||
PRINTD(("i2c_write: start write sequence\n"));
|
||||
msg.addr = chip;
|
||||
msg.flags = 0;
|
||||
msg.len = len;
|
||||
msg.buf = buffer;
|
||||
if (i2c_transfer(&msg))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
uchar i2c_reg_read(uchar chip, uchar reg)
|
||||
{
|
||||
uchar buf;
|
||||
|
||||
PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg);
|
||||
i2c_read(chip, reg, 0, &buf, 1);
|
||||
return (buf);
|
||||
}
|
||||
|
||||
void i2c_reg_write(uchar chip, uchar reg, uchar val)
|
||||
{
|
||||
PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip,
|
||||
reg, val);
|
||||
i2c_write(chip, reg, 0, &val, 1);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
174
cpu/bf537/init_sdram.S
Normal file
174
cpu/bf537/init_sdram.S
Normal file
|
@ -0,0 +1,174 @@
|
|||
#define ASSEMBLY
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/mem_init.h>
|
||||
.global init_sdram;
|
||||
|
||||
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
|
||||
#if (CONFIG_CCLK_DIV == 1)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 2)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 4)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 8)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
|
||||
#endif
|
||||
#ifndef CONFIG_CCLK_ACT_DIV
|
||||
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
|
||||
#endif
|
||||
#endif
|
||||
|
||||
init_sdram:
|
||||
[--SP] = ASTAT;
|
||||
[--SP] = RETS;
|
||||
[--SP] = (R7:0);
|
||||
[--SP] = (P5:0);
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
p0.h = hi(SIC_IWR);
|
||||
p0.l = lo(SIC_IWR);
|
||||
r0.l = 0x1;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
|
||||
p0.h = hi(SPI_BAUD);
|
||||
p0.l = lo(SPI_BAUD);
|
||||
r0.l = CONFIG_SPI_BAUD;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
#endif
|
||||
|
||||
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
|
||||
|
||||
#ifdef CONFIG_BF537
|
||||
/* Enable PHY CLK buffer output */
|
||||
p0.h = hi(VR_CTL);
|
||||
p0.l = lo(VR_CTL);
|
||||
r0.l = w[p0];
|
||||
bitset(r0, 14);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
#endif
|
||||
/*
|
||||
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
|
||||
*/
|
||||
p0.h = hi(PLL_LOCKCNT);
|
||||
p0.l = lo(PLL_LOCKCNT);
|
||||
r0 = 0x300(Z);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* Put SDRAM in self-refresh, incase anything is running
|
||||
*/
|
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITSET (R0, 24);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/*
|
||||
* Set PLL_CTL with the value that we calculate in R0
|
||||
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
||||
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
||||
* - [7] = output delay (add 200ps of delay to mem signals)
|
||||
* - [6] = input delay (add 200ps of input delay to mem signals)
|
||||
* - [5] = PDWN : 1=All Clocks off
|
||||
* - [3] = STOPCK : 1=Core Clock off
|
||||
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
||||
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
||||
* all other bits set to zero
|
||||
*/
|
||||
|
||||
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||
r0 = r0 << 9; /* Shift it over */
|
||||
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||
r0 = r1 | r0;
|
||||
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
||||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
p0.l = lo(PLL_CTL); /* Load the address */
|
||||
cli r2; /* Disable interrupts */
|
||||
ssync;
|
||||
w[p0] = r0.l; /* Set the value */
|
||||
idle; /* Wait for the PLL to stablize */
|
||||
sti r2; /* Enable interrupts */
|
||||
|
||||
check_again:
|
||||
p0.h = hi(PLL_STAT);
|
||||
p0.l = lo(PLL_STAT);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0,5);
|
||||
if ! CC jump check_again;
|
||||
|
||||
/* Configure SCLK & CCLK Dividers */
|
||||
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||
p0.h = hi(PLL_DIV);
|
||||
p0.l = lo(PLL_DIV);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Now, Initialize the SDRAM,
|
||||
* start with the SDRAM Refresh Rate Control Register
|
||||
*/
|
||||
p0.l = lo(EBIU_SDRRC);
|
||||
p0.h = hi(EBIU_SDRRC);
|
||||
r0 = mem_SDRRC;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* SDRAM Memory Bank Control Register - bank specific parameters
|
||||
*/
|
||||
p0.l = (EBIU_SDBCTL & 0xFFFF);
|
||||
p0.h = (EBIU_SDBCTL >> 16);
|
||||
r0 = mem_SDBCTL;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* SDRAM Global Control Register - global programmable parameters
|
||||
* Disable self-refresh
|
||||
*/
|
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITCLR (R0, 24);
|
||||
|
||||
/*
|
||||
* Check if SDRAM is already powered up, if it is, enable self-refresh
|
||||
*/
|
||||
p0.h = hi(EBIU_SDSTAT);
|
||||
p0.l = lo(EBIU_SDSTAT);
|
||||
r2.l = w[p0];
|
||||
cc = bittst(r2,3);
|
||||
if !cc jump skip;
|
||||
NOP;
|
||||
BITSET (R0, 23);
|
||||
skip:
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/* Write in the new value in the register */
|
||||
R0.L = lo(mem_SDGCTL);
|
||||
R0.H = hi(mem_SDGCTL);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
nop;
|
||||
|
||||
(P5:0) = [SP++];
|
||||
(R7:0) = [SP++];
|
||||
RETS = [SP++];
|
||||
ASTAT = [SP++];
|
||||
RTS;
|
199
cpu/bf537/init_sdram_bootrom_initblock.S
Normal file
199
cpu/bf537/init_sdram_bootrom_initblock.S
Normal file
|
@ -0,0 +1,199 @@
|
|||
#define ASSEMBLY
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/mem_init.h>
|
||||
.global init_sdram;
|
||||
|
||||
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
|
||||
#if (CONFIG_CCLK_DIV == 1)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 2)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 4)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 8)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
|
||||
#endif
|
||||
#ifndef CONFIG_CCLK_ACT_DIV
|
||||
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
|
||||
#endif
|
||||
#endif
|
||||
|
||||
init_sdram:
|
||||
[--SP] = ASTAT;
|
||||
[--SP] = RETS;
|
||||
[--SP] = (R7:0);
|
||||
[--SP] = (P5:0);
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
p0.h = hi(SIC_IWR);
|
||||
p0.l = lo(SIC_IWR);
|
||||
r0.l = 0x1;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
|
||||
p0.h = hi(SPI_BAUD);
|
||||
p0.l = lo(SPI_BAUD);
|
||||
r0.l = CONFIG_SPI_BAUD_INITBLOCK;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
#endif
|
||||
|
||||
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
|
||||
|
||||
#ifdef CONFIG_BF537
|
||||
/* Enable PHY CLK buffer output */
|
||||
p0.h = hi(VR_CTL);
|
||||
p0.l = lo(VR_CTL);
|
||||
r0.l = w[p0];
|
||||
bitset(r0, 14);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
#endif
|
||||
/*
|
||||
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
|
||||
*/
|
||||
p0.h = hi(PLL_LOCKCNT);
|
||||
p0.l = lo(PLL_LOCKCNT);
|
||||
r0 = 0x300(Z);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* Put SDRAM in self-refresh, incase anything is running
|
||||
*/
|
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITSET (R0, 24);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/*
|
||||
* Set PLL_CTL with the value that we calculate in R0
|
||||
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
||||
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
||||
* - [7] = output delay (add 200ps of delay to mem signals)
|
||||
* - [6] = input delay (add 200ps of input delay to mem signals)
|
||||
* - [5] = PDWN : 1=All Clocks off
|
||||
* - [3] = STOPCK : 1=Core Clock off
|
||||
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
||||
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
||||
* all other bits set to zero
|
||||
*/
|
||||
|
||||
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||
r0 = r0 << 9; /* Shift it over */
|
||||
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||
r0 = r1 | r0;
|
||||
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
||||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
p0.l = lo(PLL_CTL); /* Load the address */
|
||||
cli r2; /* Disable interrupts */
|
||||
ssync;
|
||||
w[p0] = r0.l; /* Set the value */
|
||||
idle; /* Wait for the PLL to stablize */
|
||||
sti r2; /* Enable interrupts */
|
||||
|
||||
check_again:
|
||||
p0.h = hi(PLL_STAT);
|
||||
p0.l = lo(PLL_STAT);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0,5);
|
||||
if ! CC jump check_again;
|
||||
|
||||
/* Configure SCLK & CCLK Dividers */
|
||||
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||
p0.h = hi(PLL_DIV);
|
||||
p0.l = lo(PLL_DIV);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We now are running at speed, time to set the Async mem bank wait states
|
||||
* This will speed up execution, since we are normally running from FLASH.
|
||||
*/
|
||||
|
||||
p2.h = (EBIU_AMBCTL1 >> 16);
|
||||
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
|
||||
r0.h = (AMBCTL1VAL >> 16);
|
||||
r0.l = (AMBCTL1VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMBCTL0 >> 16);
|
||||
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
|
||||
r0.h = (AMBCTL0VAL >> 16);
|
||||
r0.l = (AMBCTL0VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMGCTL >> 16);
|
||||
p2.l = (EBIU_AMGCTL & 0xffff);
|
||||
r0 = AMGCTLVAL;
|
||||
w[p2] = r0;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* Now, Initialize the SDRAM,
|
||||
* start with the SDRAM Refresh Rate Control Register
|
||||
*/
|
||||
p0.l = lo(EBIU_SDRRC);
|
||||
p0.h = hi(EBIU_SDRRC);
|
||||
r0 = mem_SDRRC;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* SDRAM Memory Bank Control Register - bank specific parameters
|
||||
*/
|
||||
p0.l = (EBIU_SDBCTL & 0xFFFF);
|
||||
p0.h = (EBIU_SDBCTL >> 16);
|
||||
r0 = mem_SDBCTL;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* SDRAM Global Control Register - global programmable parameters
|
||||
* Disable self-refresh
|
||||
*/
|
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITCLR (R0, 24);
|
||||
|
||||
/*
|
||||
* Check if SDRAM is already powered up, if it is, enable self-refresh
|
||||
*/
|
||||
p0.h = hi(EBIU_SDSTAT);
|
||||
p0.l = lo(EBIU_SDSTAT);
|
||||
r2.l = w[p0];
|
||||
cc = bittst(r2,3);
|
||||
if !cc jump skip;
|
||||
NOP;
|
||||
BITSET (R0, 23);
|
||||
skip:
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/* Write in the new value in the register */
|
||||
R0.L = lo(mem_SDGCTL);
|
||||
R0.H = hi(mem_SDGCTL);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
nop;
|
||||
|
||||
(P5:0) = [SP++];
|
||||
(R7:0) = [SP++];
|
||||
RETS = [SP++];
|
||||
ASTAT = [SP++];
|
||||
RTS;
|
246
cpu/bf537/interrupt.S
Normal file
246
cpu/bf537/interrupt.S
Normal file
|
@ -0,0 +1,246 @@
|
|||
/*
|
||||
* U-boot - interrupt.S Processing of interrupts and exception handling
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* This file is based on interrupt.S
|
||||
*
|
||||
* Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
|
||||
* Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
|
||||
* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
|
||||
* Kenneth Albanowski <kjahds@kjahds.com>,
|
||||
* The Silver Hammer Group, Ltd.
|
||||
*
|
||||
* (c) 1995, Dionne & Associates
|
||||
* (c) 1995, DKG Display Tech.
|
||||
*
|
||||
* This file is also based on exception.asm
|
||||
* (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/hw_irq.h>
|
||||
#include <asm/entry.h>
|
||||
#include <asm/blackfin_defs.h>
|
||||
|
||||
.global _blackfin_irq_panic;
|
||||
|
||||
.text
|
||||
.align 2
|
||||
|
||||
#ifndef CONFIG_KGDB
|
||||
.global _evt_emulation
|
||||
_evt_emulation:
|
||||
SAVE_CONTEXT
|
||||
r0 = IRQ_EMU;
|
||||
r1 = seqstat;
|
||||
sp += -12;
|
||||
call _blackfin_irq_panic;
|
||||
sp += 12;
|
||||
rte;
|
||||
#endif
|
||||
|
||||
.global _evt_nmi
|
||||
_evt_nmi:
|
||||
SAVE_CONTEXT
|
||||
r0 = IRQ_NMI;
|
||||
r1 = RETN;
|
||||
sp += -12;
|
||||
call _blackfin_irq_panic;
|
||||
sp += 12;
|
||||
|
||||
_evt_nmi_exit:
|
||||
rtn;
|
||||
|
||||
.global _trap
|
||||
_trap:
|
||||
SAVE_ALL_SYS
|
||||
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
|
||||
sp += -12;
|
||||
call _trap_c
|
||||
sp += 12;
|
||||
RESTORE_ALL_SYS
|
||||
rtx;
|
||||
|
||||
.global _evt_rst
|
||||
_evt_rst:
|
||||
SAVE_CONTEXT
|
||||
r0 = IRQ_RST;
|
||||
r1 = RETN;
|
||||
sp += -12;
|
||||
call _do_reset;
|
||||
sp += 12;
|
||||
|
||||
_evt_rst_exit:
|
||||
rtn;
|
||||
|
||||
irq_panic:
|
||||
r0 = IRQ_EVX;
|
||||
r1 = sp;
|
||||
sp += -12;
|
||||
call _blackfin_irq_panic;
|
||||
sp += 12;
|
||||
|
||||
.global _evt_ivhw
|
||||
_evt_ivhw:
|
||||
SAVE_CONTEXT
|
||||
RAISE 14;
|
||||
|
||||
_evt_ivhw_exit:
|
||||
rti;
|
||||
|
||||
.global _evt_timer
|
||||
_evt_timer:
|
||||
SAVE_CONTEXT
|
||||
r0 = IRQ_CORETMR;
|
||||
sp += -12;
|
||||
/* Polling method used now. */
|
||||
/* call timer_int; */
|
||||
sp += 12;
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
nop;
|
||||
|
||||
.global _evt_evt7
|
||||
_evt_evt7:
|
||||
SAVE_CONTEXT
|
||||
r0 = 7;
|
||||
sp += -12;
|
||||
call _process_int;
|
||||
sp += 12;
|
||||
|
||||
evt_evt7_exit:
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
|
||||
.global _evt_evt8
|
||||
_evt_evt8:
|
||||
SAVE_CONTEXT
|
||||
r0 = 8;
|
||||
sp += -12;
|
||||
call _process_int;
|
||||
sp += 12;
|
||||
|
||||
evt_evt8_exit:
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
|
||||
.global _evt_evt9
|
||||
_evt_evt9:
|
||||
SAVE_CONTEXT
|
||||
r0 = 9;
|
||||
sp += -12;
|
||||
call _process_int;
|
||||
sp += 12;
|
||||
|
||||
evt_evt9_exit:
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
|
||||
.global _evt_evt10
|
||||
_evt_evt10:
|
||||
SAVE_CONTEXT
|
||||
r0 = 10;
|
||||
sp += -12;
|
||||
call _process_int;
|
||||
sp += 12;
|
||||
|
||||
evt_evt10_exit:
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
|
||||
.global _evt_evt11
|
||||
_evt_evt11:
|
||||
SAVE_CONTEXT
|
||||
r0 = 11;
|
||||
sp += -12;
|
||||
call _process_int;
|
||||
sp += 12;
|
||||
|
||||
evt_evt11_exit:
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
|
||||
.global _evt_evt12
|
||||
_evt_evt12:
|
||||
SAVE_CONTEXT
|
||||
r0 = 12;
|
||||
sp += -12;
|
||||
call _process_int;
|
||||
sp += 12;
|
||||
evt_evt12_exit:
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
|
||||
.global _evt_evt13
|
||||
_evt_evt13:
|
||||
SAVE_CONTEXT
|
||||
r0 = 13;
|
||||
sp += -12;
|
||||
call _process_int;
|
||||
sp += 12;
|
||||
|
||||
evt_evt13_exit:
|
||||
RESTORE_CONTEXT
|
||||
rti;
|
||||
|
||||
.global _evt_system_call
|
||||
_evt_system_call:
|
||||
[--sp] = r0;
|
||||
[--SP] = RETI;
|
||||
r0 = [sp++];
|
||||
r0 += 2;
|
||||
[--sp] = r0;
|
||||
RETI = [SP++];
|
||||
r0 = [SP++];
|
||||
SAVE_CONTEXT
|
||||
sp += -12;
|
||||
call _exception_handle;
|
||||
sp += 12;
|
||||
RESTORE_CONTEXT
|
||||
RTI;
|
||||
|
||||
evt_system_call_exit:
|
||||
rti;
|
||||
|
||||
.global _evt_soft_int1
|
||||
_evt_soft_int1:
|
||||
[--sp] = r0;
|
||||
[--SP] = RETI;
|
||||
r0 = [sp++];
|
||||
r0 += 2;
|
||||
[--sp] = r0;
|
||||
RETI = [SP++];
|
||||
r0 = [SP++];
|
||||
SAVE_CONTEXT
|
||||
sp += -12;
|
||||
call _exception_handle;
|
||||
sp += 12;
|
||||
RESTORE_CONTEXT
|
||||
RTI;
|
||||
|
||||
evt_soft_int1_exit:
|
||||
rti;
|
174
cpu/bf537/interrupts.c
Normal file
174
cpu/bf537/interrupts.c
Normal file
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* U-boot - interrupts.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* This file is based on interrupts.c
|
||||
* Copyright 1996 Roman Zippel
|
||||
* Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
|
||||
* Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
|
||||
* Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
|
||||
* Copyright 2003 Metrowerks/Motorola
|
||||
* Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
|
||||
* BuyWays B.V. (www.buyways.nl)
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/irq.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include "cpu.h"
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong last_time;
|
||||
static int int_flag;
|
||||
|
||||
int irq_flags; /* needed by asm-blackfin/system.h */
|
||||
|
||||
/* Functions just to satisfy the linker */
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On BF533 it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On BF533 it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk (void)
|
||||
{
|
||||
ulong tbclk;
|
||||
|
||||
tbclk = CFG_HZ;
|
||||
return tbclk;
|
||||
}
|
||||
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
restore_flags(int_flag);
|
||||
}
|
||||
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
save_and_cli(int_flag);
|
||||
return 1;
|
||||
}
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
void udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long delay, start, stop;
|
||||
unsigned long cclk;
|
||||
cclk = (CONFIG_CCLK_HZ);
|
||||
|
||||
while (usec > 1) {
|
||||
/*
|
||||
* how many clock ticks to delay?
|
||||
* - request(in useconds) * clock_ticks(Hz) / useconds/second
|
||||
*/
|
||||
if (usec < 1000) {
|
||||
delay = (usec * (cclk / 244)) >> 12;
|
||||
usec = 0;
|
||||
} else {
|
||||
delay = (1000 * (cclk / 244)) >> 12;
|
||||
usec -= 1000;
|
||||
}
|
||||
|
||||
asm volatile (" %0 = CYCLES;":"=r" (start));
|
||||
do {
|
||||
asm volatile (" %0 = CYCLES; ":"=r" (stop));
|
||||
} while (stop - start < delay);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void timer_init(void)
|
||||
{
|
||||
*pTCNTL = 0x1;
|
||||
*pTSCALE = 0x0;
|
||||
*pTCOUNT = MAX_TIM_LOAD;
|
||||
*pTPERIOD = MAX_TIM_LOAD;
|
||||
*pTCNTL = 0x7;
|
||||
asm("CSYNC;");
|
||||
|
||||
timestamp = 0;
|
||||
last_time = 0;
|
||||
}
|
||||
|
||||
/* Any network command or flash
|
||||
* command is started get_timer shall
|
||||
* be called before TCOUNT gets reset,
|
||||
* to implement the accurate timeouts.
|
||||
*
|
||||
* How ever milliconds doesn't return
|
||||
* the number that has been elapsed from
|
||||
* the last reset.
|
||||
*
|
||||
* As get_timer is used in the u-boot
|
||||
* only for timeouts this should be
|
||||
* sufficient
|
||||
*/
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
ulong milisec;
|
||||
|
||||
/* Number of clocks elapsed */
|
||||
ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
|
||||
|
||||
/**
|
||||
* Find if the TCOUNT is reset
|
||||
* timestamp gives the number of times
|
||||
* TCOUNT got reset
|
||||
*/
|
||||
if (clocks < last_time)
|
||||
timestamp++;
|
||||
last_time = clocks;
|
||||
|
||||
/* Get the number of milliseconds */
|
||||
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
|
||||
|
||||
/**
|
||||
* Find the number of millisonds
|
||||
* that got elapsed before this TCOUNT cycle
|
||||
*/
|
||||
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
|
||||
|
||||
return (milisec - base);
|
||||
}
|
||||
|
||||
void reset_timer (void)
|
||||
{
|
||||
timestamp = 0;
|
||||
}
|
117
cpu/bf537/ints.c
Normal file
117
cpu/bf537/ints.c
Normal file
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* U-boot - ints.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* This file is based on ints.c
|
||||
*
|
||||
* Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
|
||||
* drivers
|
||||
*
|
||||
* Copyright 1996 Roman Zippel
|
||||
* Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
|
||||
* Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
|
||||
* Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
|
||||
* Copyright 2003 Metrowerks/Motorola
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include "cpu.h"
|
||||
|
||||
void blackfin_irq_panic(int reason, struct pt_regs *regs)
|
||||
{
|
||||
printf("\n\nException: IRQ 0x%x entered\n", reason);
|
||||
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
|
||||
printf("stack frame=0x%x, ", (unsigned int)regs);
|
||||
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
|
||||
dump(regs);
|
||||
printf("Unhandled IRQ or exceptions!\n");
|
||||
printf("Please reset the board \n");
|
||||
}
|
||||
|
||||
void blackfin_init_IRQ(void)
|
||||
{
|
||||
*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
|
||||
cli();
|
||||
#ifndef CONFIG_KGDB
|
||||
*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
|
||||
#endif
|
||||
*(unsigned volatile long *)(EVT_NMI_ADDR) =
|
||||
(unsigned volatile long)evt_nmi;
|
||||
*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
|
||||
(unsigned volatile long)trap;
|
||||
*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
|
||||
(unsigned volatile long)evt_ivhw;
|
||||
*(unsigned volatile long *)(EVT_RESET_ADDR) =
|
||||
(unsigned volatile long)evt_rst;
|
||||
*(unsigned volatile long *)(EVT_TIMER_ADDR) =
|
||||
(unsigned volatile long)evt_timer;
|
||||
*(unsigned volatile long *)(EVT_IVG7_ADDR) =
|
||||
(unsigned volatile long)evt_evt7;
|
||||
*(unsigned volatile long *)(EVT_IVG8_ADDR) =
|
||||
(unsigned volatile long)evt_evt8;
|
||||
*(unsigned volatile long *)(EVT_IVG9_ADDR) =
|
||||
(unsigned volatile long)evt_evt9;
|
||||
*(unsigned volatile long *)(EVT_IVG10_ADDR) =
|
||||
(unsigned volatile long)evt_evt10;
|
||||
*(unsigned volatile long *)(EVT_IVG11_ADDR) =
|
||||
(unsigned volatile long)evt_evt11;
|
||||
*(unsigned volatile long *)(EVT_IVG12_ADDR) =
|
||||
(unsigned volatile long)evt_evt12;
|
||||
*(unsigned volatile long *)(EVT_IVG13_ADDR) =
|
||||
(unsigned volatile long)evt_evt13;
|
||||
*(unsigned volatile long *)(EVT_IVG14_ADDR) =
|
||||
(unsigned volatile long)evt_system_call;
|
||||
*(unsigned volatile long *)(EVT_IVG15_ADDR) =
|
||||
(unsigned volatile long)evt_soft_int1;
|
||||
*(volatile unsigned long *)ILAT = 0;
|
||||
asm("csync;");
|
||||
sti();
|
||||
*(volatile unsigned long *)IMASK = 0xffbf;
|
||||
asm("csync;");
|
||||
}
|
||||
|
||||
void exception_handle(void)
|
||||
{
|
||||
#if defined (CONFIG_PANIC_HANG)
|
||||
display_excp();
|
||||
#else
|
||||
udelay(100000); /* allow messages to go out */
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
#endif
|
||||
}
|
||||
|
||||
void display_excp(void)
|
||||
{
|
||||
printf("Exception!\n");
|
||||
}
|
194
cpu/bf537/serial.c
Normal file
194
cpu/bf537/serial.c
Normal file
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* U-boot - serial.c Serial driver for BF537
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* This file is based on
|
||||
* bf537_serial.c: Serial driver for BlackFin BF537 internal UART.
|
||||
* Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
|
||||
* BuyWays B.V. (www.buyways.nl)
|
||||
*
|
||||
* Based heavily on blkfinserial.c
|
||||
* blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
|
||||
* Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
|
||||
* Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
|
||||
* Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
|
||||
*
|
||||
* Based on code from 68328 version serial driver imlpementation which was:
|
||||
* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
|
||||
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
|
||||
* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
|
||||
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/segment.h>
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/delay.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/io.h>
|
||||
#include "serial.h"
|
||||
|
||||
unsigned long pll_div_fact;
|
||||
|
||||
void calc_baud(void)
|
||||
{
|
||||
unsigned char i;
|
||||
int temp;
|
||||
u_long sclk = get_sclk();
|
||||
|
||||
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
|
||||
temp = sclk / (baud_table[i] * 8);
|
||||
if ((temp & 0x1) == 1) {
|
||||
temp++;
|
||||
}
|
||||
temp = temp / 2;
|
||||
hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
|
||||
hw_baud_table[i].dl_low = (temp) & 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
int i;
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
calc_baud();
|
||||
|
||||
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
|
||||
if (gd->baudrate == baud_table[i])
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable UART */
|
||||
*pUART_GCTL |= UART_GCTL_UCEN;
|
||||
sync();
|
||||
|
||||
/* Set DLAB in LCR to Access DLL and DLH */
|
||||
ACCESS_LATCH;
|
||||
sync();
|
||||
|
||||
*pUART_DLL = hw_baud_table[i].dl_low;
|
||||
sync();
|
||||
*pUART_DLH = hw_baud_table[i].dl_high;
|
||||
sync();
|
||||
|
||||
/* Clear DLAB in LCR to Access THR RBR IER */
|
||||
ACCESS_PORT_IER;
|
||||
sync();
|
||||
|
||||
/* Enable ERBFI and ELSI interrupts
|
||||
* to poll SIC_ISR register*/
|
||||
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
|
||||
sync();
|
||||
|
||||
/* Set LCR to Word Lengh 8-bit word select */
|
||||
*pUART_LCR = UART_LCR_WLS8;
|
||||
sync();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int serial_init(void)
|
||||
{
|
||||
serial_setbrg();
|
||||
return (0);
|
||||
}
|
||||
|
||||
void serial_putc(const char c)
|
||||
{
|
||||
if ((*pUART_LSR) & UART_LSR_TEMT) {
|
||||
if (c == '\n')
|
||||
serial_putc('\r');
|
||||
|
||||
local_put_char(c);
|
||||
}
|
||||
|
||||
while (!((*pUART_LSR) & UART_LSR_TEMT))
|
||||
SYNC_ALL;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int serial_tstc(void)
|
||||
{
|
||||
if (*pUART_LSR & UART_LSR_DR)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
int serial_getc(void)
|
||||
{
|
||||
unsigned short uart_lsr_val, uart_rbr_val;
|
||||
unsigned long isr_val;
|
||||
int ret;
|
||||
|
||||
/* Poll for RX Interrupt */
|
||||
while (!((isr_val =
|
||||
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
|
||||
asm("csync;");
|
||||
|
||||
uart_lsr_val = *pUART_LSR; /* Clear status bit */
|
||||
uart_rbr_val = *pUART_RBR; /* getc() */
|
||||
|
||||
if (isr_val & IRQ_UART_ERROR_BIT) {
|
||||
ret = -1;
|
||||
} else {
|
||||
ret = uart_rbr_val & 0xff;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void serial_puts(const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc(*s++);
|
||||
}
|
||||
}
|
||||
|
||||
static void local_put_char(char ch)
|
||||
{
|
||||
int flags = 0;
|
||||
unsigned long isr_val;
|
||||
|
||||
save_and_cli(flags);
|
||||
|
||||
/* Poll for TX Interruput */
|
||||
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
|
||||
asm("csync;");
|
||||
|
||||
*pUART_THR = ch; /* putc() */
|
||||
|
||||
if (isr_val & IRQ_UART_ERROR_BIT) {
|
||||
printf("?");
|
||||
}
|
||||
|
||||
restore_flags(flags);
|
||||
|
||||
return;
|
||||
}
|
77
cpu/bf537/serial.h
Normal file
77
cpu/bf537/serial.h
Normal file
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* U-boot - bf537_serial.h Serial Driver defines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* This file is based on
|
||||
* bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
|
||||
* Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
|
||||
* BuyWays B.V. (www.buyways.nl)
|
||||
*
|
||||
* Based heavily on:
|
||||
* blkfinserial.h: Definitions for the BlackFin DSP serial driver.
|
||||
*
|
||||
* Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
|
||||
* Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
|
||||
*
|
||||
* Based on code from 68328serial.c which was:
|
||||
* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
|
||||
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
|
||||
* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
|
||||
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _Bf537_SERIAL_H
|
||||
#define _Bf537_SERIAL_H
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
|
||||
#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
|
||||
#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
|
||||
|
||||
void serial_setbrg(void);
|
||||
static void local_put_char(char ch);
|
||||
void calc_baud(void);
|
||||
void serial_setbrg(void);
|
||||
int serial_init(void);
|
||||
void serial_putc(const char c);
|
||||
int serial_tstc(void);
|
||||
int serial_getc(void);
|
||||
void serial_puts(const char *s);
|
||||
static void local_put_char(char ch);
|
||||
|
||||
int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
|
||||
|
||||
struct {
|
||||
unsigned char dl_high;
|
||||
unsigned char dl_low;
|
||||
} hw_baud_table[5];
|
||||
|
||||
#ifdef CONFIG_STAMP
|
||||
extern unsigned long pll_div_fact;
|
||||
#endif
|
||||
|
||||
#endif
|
579
cpu/bf537/start.S
Normal file
579
cpu/bf537/start.S
Normal file
|
@ -0,0 +1,579 @@
|
|||
/*
|
||||
* U-boot - start.S Startup file of u-boot for BF537
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* This file is based on head.S
|
||||
* Copyright (c) 2003 Metrowerks/Motorola
|
||||
* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
|
||||
* Kenneth Albanowski <kjahds@kjahds.com>,
|
||||
* The Silver Hammer Group, Ltd.
|
||||
* (c) 1995, Dionne & Associates
|
||||
* (c) 1995, DKG Display Tech.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note: A change in this file subsequently requires a change in
|
||||
* board/$(board_name)/config.mk for a valid u-boot.bin
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
.global _stext;
|
||||
.global __bss_start;
|
||||
.global start;
|
||||
.global _start;
|
||||
.global _rambase;
|
||||
.global _ramstart;
|
||||
.global _ramend;
|
||||
.global _bf533_data_dest;
|
||||
.global _bf533_data_size;
|
||||
.global edata;
|
||||
.global _initialize;
|
||||
.global _exit;
|
||||
.global flashdataend;
|
||||
.global init_sdram;
|
||||
.global _icache_enable;
|
||||
.global _dcache_enable;
|
||||
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
|
||||
.global _memory_post_test;
|
||||
.global _post_flag;
|
||||
#endif
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
|
||||
#if (CONFIG_CCLK_DIV == 1)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 2)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 4)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
|
||||
#endif
|
||||
#if (CONFIG_CCLK_DIV == 8)
|
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
|
||||
#endif
|
||||
#ifndef CONFIG_CCLK_ACT_DIV
|
||||
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.text
|
||||
_start:
|
||||
start:
|
||||
_stext:
|
||||
|
||||
R0 = 0x32;
|
||||
SYSCFG = R0;
|
||||
SSYNC;
|
||||
|
||||
/* As per HW reference manual DAG registers,
|
||||
* DATA and Address resgister shall be zero'd
|
||||
* in initialization, after a reset state
|
||||
*/
|
||||
r1 = 0; /* Data registers zero'd */
|
||||
r2 = 0;
|
||||
r3 = 0;
|
||||
r4 = 0;
|
||||
r5 = 0;
|
||||
r6 = 0;
|
||||
r7 = 0;
|
||||
|
||||
p0 = 0; /* Address registers zero'd */
|
||||
p1 = 0;
|
||||
p2 = 0;
|
||||
p3 = 0;
|
||||
p4 = 0;
|
||||
p5 = 0;
|
||||
|
||||
i0 = 0; /* DAG Registers zero'd */
|
||||
i1 = 0;
|
||||
i2 = 0;
|
||||
i3 = 0;
|
||||
m0 = 0;
|
||||
m1 = 0;
|
||||
m3 = 0;
|
||||
m3 = 0;
|
||||
l0 = 0;
|
||||
l1 = 0;
|
||||
l2 = 0;
|
||||
l3 = 0;
|
||||
b0 = 0;
|
||||
b1 = 0;
|
||||
b2 = 0;
|
||||
b3 = 0;
|
||||
|
||||
/* Set loop counters to zero, to make sure that
|
||||
* hw loops are disabled.
|
||||
*/
|
||||
r0 = 0;
|
||||
lc0 = r0;
|
||||
lc1 = r0;
|
||||
|
||||
SSYNC;
|
||||
|
||||
/* Check soft reset status */
|
||||
p0.h = SWRST >> 16;
|
||||
p0.l = SWRST & 0xFFFF;
|
||||
r0.l = w[p0];
|
||||
|
||||
cc = bittst(r0, 15);
|
||||
if !cc jump no_soft_reset;
|
||||
|
||||
/* Clear Soft reset */
|
||||
r0 = 0x0000;
|
||||
w[p0] = r0;
|
||||
ssync;
|
||||
|
||||
no_soft_reset:
|
||||
nop;
|
||||
|
||||
/* Clear EVT registers */
|
||||
p0.h = (EVT_EMULATION_ADDR >> 16);
|
||||
p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
|
||||
p0 += 8;
|
||||
p1 = 14;
|
||||
r1 = 0;
|
||||
LSETUP(4,4) lc0 = p1;
|
||||
[ p0 ++ ] = r1;
|
||||
|
||||
#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
|
||||
p0.h = hi(SIC_IWR);
|
||||
p0.l = lo(SIC_IWR);
|
||||
r0.l = 0x1;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
#endif
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
|
||||
|
||||
p0.h = hi(SIC_IWR);
|
||||
p0.l = lo(SIC_IWR);
|
||||
r0.l = 0x1;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
|
||||
/*
|
||||
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
|
||||
*/
|
||||
p0.h = hi(PLL_LOCKCNT);
|
||||
p0.l = lo(PLL_LOCKCNT);
|
||||
r0 = 0x300(Z);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* Put SDRAM in self-refresh, incase anything is running
|
||||
*/
|
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITSET (R0, 24);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/*
|
||||
* Set PLL_CTL with the value that we calculate in R0
|
||||
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
||||
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
||||
* - [7] = output delay (add 200ps of delay to mem signals)
|
||||
* - [6] = input delay (add 200ps of input delay to mem signals)
|
||||
* - [5] = PDWN : 1=All Clocks off
|
||||
* - [3] = STOPCK : 1=Core Clock off
|
||||
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
||||
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
||||
* all other bits set to zero
|
||||
*/
|
||||
|
||||
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||
r0 = r0 << 9; /* Shift it over, */
|
||||
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||
r0 = r1 | r0;
|
||||
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
||||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
p0.l = lo(PLL_CTL); /* Load the address */
|
||||
cli r2; /* Disable interrupts */
|
||||
ssync;
|
||||
w[p0] = r0.l; /* Set the value */
|
||||
idle; /* Wait for the PLL to stablize */
|
||||
sti r2; /* Enable interrupts */
|
||||
|
||||
check_again:
|
||||
p0.h = hi(PLL_STAT);
|
||||
p0.l = lo(PLL_STAT);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0,5);
|
||||
if ! CC jump check_again;
|
||||
|
||||
/* Configure SCLK & CCLK Dividers */
|
||||
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||
p0.h = hi(PLL_DIV);
|
||||
p0.l = lo(PLL_DIV);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We now are running at speed, time to set the Async mem bank wait states
|
||||
* This will speed up execution, since we are normally running from FLASH.
|
||||
* we need to read MAC address from FLASH
|
||||
*/
|
||||
p2.h = (EBIU_AMBCTL1 >> 16);
|
||||
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
|
||||
r0.h = (AMBCTL1VAL >> 16);
|
||||
r0.l = (AMBCTL1VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMBCTL0 >> 16);
|
||||
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
|
||||
r0.h = (AMBCTL0VAL >> 16);
|
||||
r0.l = (AMBCTL0VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMGCTL >> 16);
|
||||
p2.l = (EBIU_AMGCTL & 0xffff);
|
||||
r0 = AMGCTLVAL;
|
||||
w[p2] = r0;
|
||||
ssync;
|
||||
|
||||
#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
|
||||
sp.l = (0xffb01000 & 0xFFFF);
|
||||
sp.h = (0xffb01000 >> 16);
|
||||
|
||||
call init_sdram;
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
|
||||
/* DMA POST code to Hi of L1 SRAM */
|
||||
postcopy:
|
||||
/* P1 Points to the beginning of SYSTEM MMR Space */
|
||||
P1.H = hi(SYSMMR_BASE);
|
||||
P1.L = lo(SYSMMR_BASE);
|
||||
|
||||
R0.H = _text_l1;
|
||||
R0.L = _text_l1;
|
||||
R1.H = _etext_l1;
|
||||
R1.L = _etext_l1;
|
||||
R2 = R1 - R0; /* Count */
|
||||
R0.H = _etext;
|
||||
R0.L = _etext;
|
||||
R1.H = (CFG_MONITOR_BASE >> 16);
|
||||
R1.L = (CFG_MONITOR_BASE & 0xFFFF);
|
||||
R0 = R0 - R1;
|
||||
R1.H = (CFG_FLASH_BASE >> 16);
|
||||
R1.L = (CFG_FLASH_BASE & 0xFFFF);
|
||||
R0 = R0 + R1; /* Source Address */
|
||||
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
|
||||
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
|
||||
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
|
||||
/* Destination DMAConfig Value (8-bit words) */
|
||||
R4.L = (DI_EN | WNR | DMAEN);
|
||||
|
||||
R6 = 0x1 (Z);
|
||||
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
|
||||
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
|
||||
|
||||
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
|
||||
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
|
||||
/* Set Source DMAConfig = DMA Enable,
|
||||
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
|
||||
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
|
||||
|
||||
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
|
||||
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
|
||||
/* Set Destination DMAConfig = DMA Enable,
|
||||
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
|
||||
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
|
||||
|
||||
POST_DMA_DONE:
|
||||
p0.h = hi(MDMA_D0_IRQ_STATUS);
|
||||
p0.l = lo(MDMA_D0_IRQ_STATUS);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0, 0);
|
||||
if ! CC jump POST_DMA_DONE
|
||||
|
||||
R0 = 0x1;
|
||||
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
|
||||
|
||||
/* DMA POST data to Hi of L1 SRAM */
|
||||
R0.H = _rodata_l1;
|
||||
R0.L = _rodata_l1;
|
||||
R1.H = _erodata_l1;
|
||||
R1.L = _erodata_l1;
|
||||
R2 = R1 - R0; /* Count */
|
||||
R0.H = _erodata;
|
||||
R0.L = _erodata;
|
||||
R1.H = (CFG_MONITOR_BASE >> 16);
|
||||
R1.L = (CFG_MONITOR_BASE & 0xFFFF);
|
||||
R0 = R0 - R1;
|
||||
R1.H = (CFG_FLASH_BASE >> 16);
|
||||
R1.L = (CFG_FLASH_BASE & 0xFFFF);
|
||||
R0 = R0 + R1; /* Source Address */
|
||||
R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
|
||||
R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
|
||||
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
|
||||
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
|
||||
|
||||
R6 = 0x1 (Z);
|
||||
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
|
||||
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
|
||||
|
||||
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
|
||||
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
|
||||
/* Set Source DMAConfig = DMA Enable,
|
||||
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
|
||||
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
|
||||
|
||||
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
|
||||
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
|
||||
/* Set Destination DMAConfig = DMA Enable,
|
||||
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
|
||||
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
|
||||
|
||||
POST_DATA_DMA_DONE:
|
||||
p0.h = hi(MDMA_D0_IRQ_STATUS);
|
||||
p0.l = lo(MDMA_D0_IRQ_STATUS);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0, 0);
|
||||
if ! CC jump POST_DATA_DMA_DONE
|
||||
|
||||
R0 = 0x1;
|
||||
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
|
||||
|
||||
p0.l = _memory_post_test;
|
||||
p0.h = _memory_post_test;
|
||||
r0 = 0x0;
|
||||
call (p0);
|
||||
r7 = r0; /* save return value */
|
||||
|
||||
call init_sdram;
|
||||
#endif
|
||||
|
||||
/* relocate into to RAM */
|
||||
call get_pc;
|
||||
offset:
|
||||
r2.l = offset;
|
||||
r2.h = offset;
|
||||
r3.l = start;
|
||||
r3.h = start;
|
||||
r1 = r2 - r3;
|
||||
|
||||
r0 = r0 - r1;
|
||||
p1 = r0;
|
||||
|
||||
p2.l = (CFG_MONITOR_BASE & 0xffff);
|
||||
p2.h = (CFG_MONITOR_BASE >> 16);
|
||||
|
||||
p3 = 0x04;
|
||||
p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
|
||||
p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
|
||||
loop1:
|
||||
r1 = [p1 ++ p3];
|
||||
[p2 ++ p3] = r1;
|
||||
cc=p2==p4;
|
||||
if !cc jump loop1;
|
||||
/*
|
||||
* configure STACK
|
||||
*/
|
||||
r0.h = (CONFIG_STACKBASE >> 16);
|
||||
r0.l = (CONFIG_STACKBASE & 0xFFFF);
|
||||
sp = r0;
|
||||
fp = sp;
|
||||
|
||||
/*
|
||||
* This next section keeps the processor in supervisor mode
|
||||
* during kernel boot. Switches to user mode at end of boot.
|
||||
* See page 3-9 of Hardware Reference manual for documentation.
|
||||
*/
|
||||
|
||||
/* To keep ourselves in the supervisor mode */
|
||||
p0.l = (EVT_IVG15_ADDR & 0xFFFF);
|
||||
p0.h = (EVT_IVG15_ADDR >> 16);
|
||||
|
||||
p1.l = _real_start;
|
||||
p1.h = _real_start;
|
||||
[p0] = p1;
|
||||
|
||||
p0.l = (IMASK & 0xFFFF);
|
||||
p0.h = (IMASK >> 16);
|
||||
r0.l = LO(IVG15_POS);
|
||||
r0.h = HI(IVG15_POS);
|
||||
[p0] = r0;
|
||||
raise 15;
|
||||
p0.l = WAIT_HERE;
|
||||
p0.h = WAIT_HERE;
|
||||
reti = p0;
|
||||
rti;
|
||||
|
||||
WAIT_HERE:
|
||||
jump WAIT_HERE;
|
||||
|
||||
.global _real_start;
|
||||
_real_start:
|
||||
[ -- sp ] = reti;
|
||||
|
||||
#ifdef CONFIG_BF537
|
||||
/* Initialise General-Purpose I/O Modules on BF537
|
||||
* Rev 0.0 Anomaly 05000212 - PORTx_FER,
|
||||
* PORT_MUX Registers Do Not accept "writes" correctly
|
||||
*/
|
||||
p0.h = hi(PORTF_FER);
|
||||
p0.l = lo(PORTF_FER);
|
||||
R0.L = W[P0]; /* Read */
|
||||
nop;
|
||||
nop;
|
||||
nop;
|
||||
ssync;
|
||||
R0 = 0x000F(Z);
|
||||
W[P0] = R0.L; /* Write */
|
||||
nop;
|
||||
nop;
|
||||
nop;
|
||||
ssync;
|
||||
W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
|
||||
nop;
|
||||
nop;
|
||||
nop;
|
||||
ssync;
|
||||
|
||||
p0.h = hi(PORTH_FER);
|
||||
p0.l = lo(PORTH_FER);
|
||||
R0.L = W[P0]; /* Read */
|
||||
nop;
|
||||
nop;
|
||||
nop;
|
||||
ssync;
|
||||
R0 = 0xFFFF(Z);
|
||||
W[P0] = R0.L; /* Write */
|
||||
nop;
|
||||
nop;
|
||||
nop;
|
||||
ssync;
|
||||
W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
|
||||
nop;
|
||||
nop;
|
||||
nop;
|
||||
ssync;
|
||||
|
||||
#endif
|
||||
|
||||
/* DMA reset code to Hi of L1 SRAM */
|
||||
copy:
|
||||
P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
|
||||
P1.L = lo(SYSMMR_BASE);
|
||||
|
||||
R0.H = reset_start; /* Source Address (high) */
|
||||
R0.L = reset_start; /* Source Address (low) */
|
||||
R1.H = reset_end;
|
||||
R1.L = reset_end;
|
||||
R2 = R1 - R0; /* Count */
|
||||
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
|
||||
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
|
||||
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
|
||||
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
|
||||
|
||||
DMA:
|
||||
R6 = 0x1 (Z);
|
||||
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
|
||||
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
|
||||
|
||||
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
|
||||
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
|
||||
/* Set Source DMAConfig = DMA Enable,
|
||||
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
|
||||
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
|
||||
|
||||
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
|
||||
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
|
||||
/* Set Destination DMAConfig = DMA Enable,
|
||||
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
|
||||
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
|
||||
|
||||
WAIT_DMA_DONE:
|
||||
p0.h = hi(MDMA_D0_IRQ_STATUS);
|
||||
p0.l = lo(MDMA_D0_IRQ_STATUS);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0, 0);
|
||||
if ! CC jump WAIT_DMA_DONE
|
||||
|
||||
R0 = 0x1;
|
||||
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
|
||||
|
||||
/* Initialize BSS Section with 0 s */
|
||||
p1.l = __bss_start;
|
||||
p1.h = __bss_start;
|
||||
p2.l = _end;
|
||||
p2.h = _end;
|
||||
r1 = p1;
|
||||
r2 = p2;
|
||||
r3 = r2 - r1;
|
||||
r3 = r3 >> 2;
|
||||
p3 = r3;
|
||||
lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
|
||||
CC = p2<=p1;
|
||||
if CC jump _clear_bss_skip;
|
||||
r0 = 0;
|
||||
_clear_bss:
|
||||
_clear_bss_end:
|
||||
[p1++] = r0;
|
||||
_clear_bss_skip:
|
||||
|
||||
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
|
||||
p0.l = _post_flag;
|
||||
p0.h = _post_flag;
|
||||
r0 = r7;
|
||||
[p0] = r0;
|
||||
#endif
|
||||
|
||||
p0.l = _start1;
|
||||
p0.h = _start1;
|
||||
jump (p0);
|
||||
|
||||
reset_start:
|
||||
p0.h = WDOG_CNT >> 16;
|
||||
p0.l = WDOG_CNT & 0xffff;
|
||||
r0 = 0x0010;
|
||||
w[p0] = r0;
|
||||
p0.h = WDOG_CTL >> 16;
|
||||
p0.l = WDOG_CTL & 0xffff;
|
||||
r0 = 0x0000;
|
||||
w[p0] = r0;
|
||||
reset_wait:
|
||||
jump reset_wait;
|
||||
|
||||
reset_end:
|
||||
nop;
|
||||
|
||||
_exit:
|
||||
jump.s _exit;
|
||||
get_pc:
|
||||
r0 = rets;
|
||||
rts;
|
38
cpu/bf537/start1.S
Normal file
38
cpu/bf537/start1.S
Normal file
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* U-boot - start1.S Code running out of RAM after relocation
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
#include <linux/config.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
.global start1;
|
||||
.global _start1;
|
||||
|
||||
.text
|
||||
_start1:
|
||||
start1:
|
||||
sp += -12;
|
||||
call _board_init_f;
|
||||
sp += 12;
|
241
cpu/bf537/traps.c
Normal file
241
cpu/bf537/traps.c
Normal file
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* U-boot - traps.c Routines related to interrupts and exceptions
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* This file is based on
|
||||
* No original Copyright holder listed,
|
||||
* Probabily original (C) Roman Zippel (assigned DJD, 1999)
|
||||
*
|
||||
* Copyright 2003 Metrowerks - for Blackfin
|
||||
* Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
|
||||
* Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/machdep.h>
|
||||
#include "cpu.h"
|
||||
#include <asm/arch/anomaly.h>
|
||||
#include <asm/cplb.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
void init_IRQ(void)
|
||||
{
|
||||
blackfin_init_IRQ();
|
||||
return;
|
||||
}
|
||||
|
||||
void process_int(unsigned long vec, struct pt_regs *fp)
|
||||
{
|
||||
printf("interrupt\n");
|
||||
return;
|
||||
}
|
||||
|
||||
extern unsigned int icplb_table[page_descriptor_table_size][2];
|
||||
extern unsigned int dcplb_table[page_descriptor_table_size][2];
|
||||
|
||||
unsigned long last_cplb_fault_retx;
|
||||
|
||||
static unsigned int cplb_sizes[4] =
|
||||
{ 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
|
||||
|
||||
void trap_c(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
|
||||
unsigned int i, j, size, *I0, *I1;
|
||||
unsigned short data = 0;
|
||||
|
||||
switch (trapnr) {
|
||||
/* 0x26 - Data CPLB Miss */
|
||||
case VEC_CPLB_M:
|
||||
|
||||
#ifdef ANOMALY_05000261
|
||||
/*
|
||||
* Work around an anomaly: if we see a new DCPLB fault,
|
||||
* return without doing anything. Then,
|
||||
* if we get the same fault again, handle it.
|
||||
*/
|
||||
addr = last_cplb_fault_retx;
|
||||
last_cplb_fault_retx = regs->retx;
|
||||
printf("this time, curr = 0x%08x last = 0x%08x\n",
|
||||
addr, last_cplb_fault_retx);
|
||||
if (addr != last_cplb_fault_retx)
|
||||
goto trap_c_return;
|
||||
#endif
|
||||
data = 1;
|
||||
|
||||
case VEC_CPLB_I_M:
|
||||
|
||||
if (data) {
|
||||
addr = *pDCPLB_FAULT_ADDR;
|
||||
} else {
|
||||
addr = *pICPLB_FAULT_ADDR;
|
||||
}
|
||||
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||
if (data) {
|
||||
size = cplb_sizes[dcplb_table[i][1] >> 16];
|
||||
j = dcplb_table[i][0];
|
||||
} else {
|
||||
size = cplb_sizes[icplb_table[i][1] >> 16];
|
||||
j = icplb_table[i][0];
|
||||
}
|
||||
if ((j <= addr) && ((j + size) > addr)) {
|
||||
debug("found %i 0x%08x\n", i, j);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i == page_descriptor_table_size) {
|
||||
printf("something is really wrong\n");
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
/* Turn the cache off */
|
||||
if (data) {
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)DMEM_CONTROL &=
|
||||
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
|
||||
sync();
|
||||
} else {
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
|
||||
sync();
|
||||
}
|
||||
|
||||
if (data) {
|
||||
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||
I1 = (unsigned int *)DCPLB_DATA0;
|
||||
} else {
|
||||
I0 = (unsigned int *)ICPLB_ADDR0;
|
||||
I1 = (unsigned int *)ICPLB_DATA0;
|
||||
}
|
||||
|
||||
j = 0;
|
||||
while (*I1 & CPLB_LOCK) {
|
||||
debug("skipping %i %08p - %08x\n", j, I1, *I1);
|
||||
*I0++;
|
||||
*I1++;
|
||||
j++;
|
||||
}
|
||||
|
||||
debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
|
||||
|
||||
for (; j < 15; j++) {
|
||||
debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
|
||||
*I0++ = *(I0 + 1);
|
||||
*I1++ = *(I1 + 1);
|
||||
}
|
||||
|
||||
if (data) {
|
||||
*I0 = dcplb_table[i][0];
|
||||
*I1 = dcplb_table[i][1];
|
||||
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||
I1 = (unsigned int *)DCPLB_DATA0;
|
||||
} else {
|
||||
*I0 = icplb_table[i][0];
|
||||
*I1 = icplb_table[i][1];
|
||||
I0 = (unsigned int *)ICPLB_ADDR0;
|
||||
I1 = (unsigned int *)ICPLB_DATA0;
|
||||
}
|
||||
|
||||
for (j = 0; j < 16; j++) {
|
||||
debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
|
||||
}
|
||||
|
||||
/* Turn the cache back on */
|
||||
if (data) {
|
||||
j = *(unsigned int *)DMEM_CONTROL;
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)DMEM_CONTROL =
|
||||
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
|
||||
sync();
|
||||
} else {
|
||||
sync();
|
||||
asm(" .align 8; ");
|
||||
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
|
||||
sync();
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
/* All traps come here */
|
||||
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
|
||||
printf("stack frame=0x%x, ", (unsigned int)regs);
|
||||
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
|
||||
dump(regs);
|
||||
printf("\n\n");
|
||||
|
||||
printf("Unhandled IRQ or exceptions!\n");
|
||||
printf("Please reset the board \n");
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
trap_c_return:
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
void dump(struct pt_regs *fp)
|
||||
{
|
||||
debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
|
||||
fp->rete, fp->retn, fp->retx, fp->rets);
|
||||
debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
|
||||
debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
|
||||
debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
|
||||
fp->r0, fp->r1, fp->r2, fp->r3);
|
||||
debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
|
||||
fp->r4, fp->r5, fp->r6, fp->r7);
|
||||
debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
|
||||
fp->p0, fp->p1, fp->p2, fp->p3);
|
||||
debug("P4: %08lx P5: %08lx FP: %08lx\n",
|
||||
fp->p4, fp->p5, fp->fp);
|
||||
debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
|
||||
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
|
||||
|
||||
debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
|
||||
fp->lb0, fp->lt0, fp->lc0);
|
||||
debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
|
||||
fp->lb1, fp->lt1, fp->lc1);
|
||||
debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
|
||||
fp->b0, fp->l0, fp->m0, fp->i0);
|
||||
debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
|
||||
fp->b1, fp->l1, fp->m1, fp->i1);
|
||||
debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
|
||||
fp->b2, fp->l2, fp->m2, fp->i2);
|
||||
debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
|
||||
fp->b3, fp->l3, fp->m3, fp->i3);
|
||||
|
||||
debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
|
||||
debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
|
||||
|
||||
}
|
194
cpu/bf537/video.c
Normal file
194
cpu/bf537/video.c
Normal file
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Denk, wd@denx.de
|
||||
* (C) Copyright 2006
|
||||
* Aubrey Li, aubrey.li@analog.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <i2c.h>
|
||||
#include <linux/types.h>
|
||||
#include <devices.h>
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define NTSC_FRAME_ADDR 0x06000000
|
||||
#include "video.h"
|
||||
|
||||
/* NTSC OUTPUT SIZE 720 * 240 */
|
||||
#define VERTICAL 2
|
||||
#define HORIZONTAL 4
|
||||
|
||||
int is_vblank_line(const int line)
|
||||
{
|
||||
/*
|
||||
* This array contains a single bit for each line in
|
||||
* an NTSC frame.
|
||||
*/
|
||||
if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
int NTSC_framebuffer_init(char *base_address)
|
||||
{
|
||||
const int NTSC_frames = 1;
|
||||
const int NTSC_lines = 525;
|
||||
char *dest = base_address;
|
||||
int frame_num, line_num;
|
||||
|
||||
for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
|
||||
for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
|
||||
unsigned int code;
|
||||
int offset = 0;
|
||||
int i;
|
||||
|
||||
if (is_vblank_line(line_num))
|
||||
offset++;
|
||||
|
||||
if (line_num > 266 || line_num < 3)
|
||||
offset += 2;
|
||||
|
||||
/* Output EAV code */
|
||||
code = SystemCodeMap[offset].EAV;
|
||||
write_dest_byte((char)(code >> 24) & 0xff);
|
||||
write_dest_byte((char)(code >> 16) & 0xff);
|
||||
write_dest_byte((char)(code >> 8) & 0xff);
|
||||
write_dest_byte((char)(code) & 0xff);
|
||||
|
||||
/* Output horizontal blanking */
|
||||
for (i = 0; i < 67 * 2; ++i) {
|
||||
write_dest_byte(0x80);
|
||||
write_dest_byte(0x10);
|
||||
}
|
||||
|
||||
/* Output SAV */
|
||||
code = SystemCodeMap[offset].SAV;
|
||||
write_dest_byte((char)(code >> 24) & 0xff);
|
||||
write_dest_byte((char)(code >> 16) & 0xff);
|
||||
write_dest_byte((char)(code >> 8) & 0xff);
|
||||
write_dest_byte((char)(code) & 0xff);
|
||||
|
||||
/* Output empty horizontal data */
|
||||
for (i = 0; i < 360 * 2; ++i) {
|
||||
write_dest_byte(0x80);
|
||||
write_dest_byte(0x10);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return dest - base_address;
|
||||
}
|
||||
|
||||
void fill_frame(char *Frame, int Value)
|
||||
{
|
||||
int *OddPtr32;
|
||||
int OddLine;
|
||||
int *EvenPtr32;
|
||||
int EvenLine;
|
||||
int i;
|
||||
int *data;
|
||||
int m, n;
|
||||
|
||||
/* fill odd and even frames */
|
||||
for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
|
||||
OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
|
||||
EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
|
||||
for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
|
||||
*OddPtr32 = Value;
|
||||
*EvenPtr32 = Value;
|
||||
}
|
||||
}
|
||||
|
||||
for (m = 0; m < VERTICAL; m++) {
|
||||
data = (int *)u_boot_logo.data;
|
||||
for (OddLine = (22 + m), EvenLine = (285 + m);
|
||||
OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
|
||||
OddLine += VERTICAL, EvenLine += VERTICAL) {
|
||||
OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
|
||||
EvenPtr32 =
|
||||
(int *)((Frame + ((EvenLine) * 1716)) + 276);
|
||||
for (i = 0; i < u_boot_logo.width / 2; i++) {
|
||||
/* enlarge one pixel to m x n */
|
||||
for (n = 0; n < HORIZONTAL; n++) {
|
||||
*OddPtr32++ = *data;
|
||||
*EvenPtr32++ = *data;
|
||||
}
|
||||
data++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void video_putc(const char c)
|
||||
{
|
||||
}
|
||||
|
||||
void video_puts(const char *s)
|
||||
{
|
||||
}
|
||||
|
||||
static int video_init(void)
|
||||
{
|
||||
char *NTSCFrame;
|
||||
NTSCFrame = (char *)NTSC_FRAME_ADDR;
|
||||
NTSC_framebuffer_init(NTSCFrame);
|
||||
fill_frame(NTSCFrame, BLUE);
|
||||
|
||||
*pPPI_CONTROL = 0x0082;
|
||||
*pPPI_FRAME = 0x020D;
|
||||
|
||||
*pDMA0_START_ADDR = NTSCFrame;
|
||||
*pDMA0_X_COUNT = 0x035A;
|
||||
*pDMA0_X_MODIFY = 0x0002;
|
||||
*pDMA0_Y_COUNT = 0x020D;
|
||||
*pDMA0_Y_MODIFY = 0x0002;
|
||||
*pDMA0_CONFIG = 0x1015;
|
||||
*pPPI_CONTROL = 0x0083;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int drv_video_init(void)
|
||||
{
|
||||
int error, devices = 1;
|
||||
|
||||
device_t videodev;
|
||||
|
||||
video_init(); /* Video initialization */
|
||||
|
||||
memset(&videodev, 0, sizeof(videodev));
|
||||
|
||||
strcpy(videodev.name, "video");
|
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
|
||||
videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
|
||||
videodev.putc = video_putc; /* 'putc' function */
|
||||
videodev.puts = video_puts; /* 'puts' function */
|
||||
|
||||
error = device_register(&videodev);
|
||||
|
||||
return (error == 0) ? devices : error;
|
||||
}
|
||||
#endif
|
25
cpu/bf537/video.h
Normal file
25
cpu/bf537/video.h
Normal file
|
@ -0,0 +1,25 @@
|
|||
#include <video_logo.h>
|
||||
#define write_dest_byte(val) {*dest++=val;}
|
||||
#define BLACK (0x01800180) /* black pixel pattern */
|
||||
#define BLUE (0x296E29F0) /* blue pixel pattern */
|
||||
#define RED (0x51F0515A) /* red pixel pattern */
|
||||
#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern*/
|
||||
#define GREEN (0x91229136) /* green pixel pattern */
|
||||
#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
|
||||
#define YELLOW (0xD292D210) /* yellow pixel pattern */
|
||||
#define WHITE (0xFE80FE80) /* white pixel pattern */
|
||||
|
||||
#define true 1
|
||||
#define false 0
|
||||
|
||||
typedef struct {
|
||||
unsigned int SAV;
|
||||
unsigned int EAV;
|
||||
} SystemCodeType;
|
||||
|
||||
const SystemCodeType SystemCodeMap[4] = {
|
||||
{0xFF000080, 0xFF00009D},
|
||||
{0xFF0000AB, 0xFF0000B6},
|
||||
{0xFF0000C7, 0xFF0000DA},
|
||||
{0xFF0000EC, 0xFF0000F1}
|
||||
};
|
|
@ -86,10 +86,14 @@ BIN += sched.bin
|
|||
endif
|
||||
|
||||
ifeq ($(ARCH),blackfin)
|
||||
ifneq ($(BOARD),bf537-stamp)
|
||||
ifneq ($(BOARD),bf537-pnav)
|
||||
ELF += smc91111_eeprom
|
||||
SREC += smc91111_eeprom.srec
|
||||
BIN += smc91111_eeprom.bin
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# The following example is pretty 8xx specific...
|
||||
ifeq ($(CPU),mpc8xx)
|
||||
|
|
116
include/asm-blackfin/arch-bf537/anomaly.h
Normal file
116
include/asm-blackfin/arch-bf537/anomaly.h
Normal file
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* File: include/asm-blackfin/arch-bf537/anomaly.h
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
|
||||
* - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
|
||||
* - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* We do not support 0.1 silicon - sorry */
|
||||
#if (defined(CONFIG_BF_REV_0_1))
|
||||
#error Kernel will not work on BF537/6/4 Version 0.1
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
|
||||
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
|
||||
slot1 and store of a P register in slot 2 is not
|
||||
supported */
|
||||
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
|
||||
Channel DMA stops */
|
||||
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
|
||||
registers. */
|
||||
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
|
||||
upper bits */
|
||||
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
|
||||
syncs */
|
||||
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
|
||||
#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
|
||||
Changed */
|
||||
#endif
|
||||
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
|
||||
SPORT external receive and transmit clocks. */
|
||||
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
|
||||
VDDint <=0.9V */
|
||||
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
|
||||
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
|
||||
an edge is detected may clear interrupt */
|
||||
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
|
||||
not restored */
|
||||
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
|
||||
control */
|
||||
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
|
||||
killed in a particular stage */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF_REV_0_2)
|
||||
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
|
||||
IDLE around a Change of Control causes
|
||||
unpredictable results */
|
||||
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
|
||||
(TDM) */
|
||||
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
|
||||
#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
|
||||
#endif
|
||||
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
|
||||
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
|
||||
interrupt not functional */
|
||||
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
|
||||
#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
|
||||
#endif
|
||||
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
|
||||
loops may cause the instruction fetch unit to
|
||||
malfunction */
|
||||
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
|
||||
the ICPLB Data registers differ */
|
||||
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
|
||||
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
|
||||
#define ANOMALY_05000262 /* Stores to data cache may be lost */
|
||||
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
|
||||
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
|
||||
instruction will cause an infinite stall in the
|
||||
second to last instruction in a hardware loop */
|
||||
#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
|
||||
and non-zero DEB_TRAFFIC_PERIOD value */
|
||||
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
|
||||
internal voltage regulator (VDDint) to decrease */
|
||||
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
|
||||
an edge is detected may clear interrupt */
|
||||
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
|
||||
DMA system instability */
|
||||
#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
|
||||
Atmel Dataflash devices */
|
||||
|
||||
#endif /* CONFIG_BF_REV_0_2 */
|
||||
|
||||
#endif /* _MACH_ANOMALY_H_ */
|
78
include/asm-blackfin/arch-bf537/bf537_serial.h
Normal file
78
include/asm-blackfin/arch-bf537/bf537_serial.h
Normal file
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* U-boot bf537_serial.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _BF537_SERIAL_H_
|
||||
#define _BF537_SERIAL_H_
|
||||
|
||||
#define BYTE_REF(addr) (*((volatile char*)addr))
|
||||
#define HALFWORD_REF(addr) (*((volatile short*)addr))
|
||||
#define WORD_REF(addr) (*((volatile long*)addr))
|
||||
|
||||
#define UART_THR_LO HALFWORD_REF(UART_THR)
|
||||
#define UART_RBR_LO HALFWORD_REF(UART_RBR)
|
||||
#define UART_DLL_LO HALFWORD_REF(UART_DLL)
|
||||
#define UART_IER_LO HALFWORD_REF(UART_IER)
|
||||
#define UART_IER_ERBFI 0x01
|
||||
#define UART_IER_ETBEI 0x02
|
||||
#define UART_IER_ELSI 0x04
|
||||
#define UART_IER_EDDSI 0x08
|
||||
|
||||
#define UART_DLH_LO HALFWORD_REF(UART_DLH)
|
||||
#define UART_IIR_LO HALFWORD_REF(UART_IIR)
|
||||
#define UART_IIR_NOINT 0x01
|
||||
#define UART_IIR_STATUS 0x06
|
||||
#define UART_IIR_LSR 0x06
|
||||
#define UART_IIR_RBR 0x04
|
||||
#define UART_IIR_THR 0x02
|
||||
#define UART_IIR_MSR 0x00
|
||||
|
||||
#define UART_LCR_LO HALFWORD_REF(UART_LCR)
|
||||
#define UART_LCR_WLS5 0
|
||||
#define UART_LCR_WLS6 0x01
|
||||
#define UART_LCR_WLS7 0x02
|
||||
#define UART_LCR_WLS8 0x03
|
||||
#define UART_LCR_STB 0x04
|
||||
#define UART_LCR_PEN 0x08
|
||||
#define UART_LCR_EPS 0x10
|
||||
#define UART_LCR_SP 0x20
|
||||
#define UART_LCR_SB 0x40
|
||||
#define UART_LCR_DLAB 0x80
|
||||
|
||||
#define UART_MCR_LO HALFWORD_REF(UART_MCR)
|
||||
|
||||
#define UART_LSR_LO HALFWORD_REF(UART_LSR)
|
||||
#define UART_LSR_DR 0x01
|
||||
#define UART_LSR_OE 0x02
|
||||
#define UART_LSR_PE 0x04
|
||||
#define UART_LSR_FE 0x08
|
||||
#define UART_LSR_BI 0x10
|
||||
#define UART_LSR_THRE 0x20
|
||||
#define UART_LSR_TEMT 0x40
|
||||
|
||||
#define UART_MSR_LO HALFWORD_REF(UART_MSR)
|
||||
#define UART_SCR_LO HALFWORD_REF(UART_SCR)
|
||||
#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
|
||||
#define UART_GCTL_UCEN 0x01
|
||||
|
||||
#endif
|
46
include/asm-blackfin/arch-bf537/bf5xx_rtc.h
Normal file
46
include/asm-blackfin/arch-bf537/bf5xx_rtc.h
Normal file
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* U-boot - bf537_rtc.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _BF537_RTC_H_
|
||||
#define _BF537_RTC_H_
|
||||
|
||||
void rtc_init(void);
|
||||
void wait_for_complete(void);
|
||||
void rtc_reset(void);
|
||||
|
||||
#define MIN_TO_SECS(_x_) (60 * _x_)
|
||||
#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
|
||||
#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
|
||||
|
||||
#define NUM_SECS_IN_DAY (24 * 3600)
|
||||
#define NUM_SECS_IN_HOUR (3600)
|
||||
#define NUM_SECS_IN_MIN (60)
|
||||
|
||||
/* Shift values for RTC_STAT register */
|
||||
#define DAY_BITS_OFF 17
|
||||
#define HOUR_BITS_OFF 12
|
||||
#define MIN_BITS_OFF 6
|
||||
#define SEC_BITS_OFF 0
|
||||
|
||||
#endif
|
1009
include/asm-blackfin/arch-bf537/cdefBF534.h
Normal file
1009
include/asm-blackfin/arch-bf537/cdefBF534.h
Normal file
File diff suppressed because it is too large
Load diff
186
include/asm-blackfin/arch-bf537/cdefBF537.h
Normal file
186
include/asm-blackfin/arch-bf537/cdefBF537.h
Normal file
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
|
||||
*
|
||||
***********************************************************************************
|
||||
*
|
||||
* This include file contains a list of macro "defines" to enable the programmer
|
||||
* to use symbolic names for register-access.
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.1
|
||||
* date: 2004/03/01 21:23:01; author: joeb
|
||||
* Initial revision
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.2
|
||||
* date: 2004/05/15 16:30:00; author: joeb
|
||||
* comments: removed I2C/IIC references to TWI, changed GPIO sections
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.3
|
||||
* date: 2004/06/08 12:25:00; author: joeb
|
||||
* comments: renamed some TWI and GPIO registers
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.4
|
||||
* date: 2004/06/09 14:25:00; author: joeb
|
||||
* comments: changed Timer status register to 32-bit, renamed EMAC count registers
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.5
|
||||
* date: 2004/08/10 10:25:00; author: joeb
|
||||
* comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.6
|
||||
* date: 2004/08/17 16:25:00; author: joeb
|
||||
* comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.7
|
||||
* date: 2004/08/18 13:21:00; author: joeb
|
||||
* comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.8
|
||||
* date: 2004/08/20 10:27:00; author: joeb
|
||||
* comments: Renamed External DMA to Handshake DMA
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.9
|
||||
* date: 2004/08/23 13:42:00; author: joeb
|
||||
* comments: Renamed Handshake DMA Register Set
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.10
|
||||
* date: 2004/10/28 15:40:00; author: joeb
|
||||
* comments: Shortened EMAC Count Register Names
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.11
|
||||
* date: 2004/12/13 11:05:00; author: joeb
|
||||
* comments: Fixed address pointers - (volatile void **) to (void * volatile *)
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.12
|
||||
* date: 2004/12/17 14:25:00; author: joeb
|
||||
* comments: Replaced C++ Single-Line Comments w/C-standard Comments
|
||||
* Changed EMAC EQ1024 TX/RX References to GE1024
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.13
|
||||
* date: 2005/01/05 10:50:00; author: joeb
|
||||
* comments: Removed excess white space in CAN_AM section
|
||||
* Added support for CAN Macros to Index AM and Mailbox Areas
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.14
|
||||
* date: 2005/01/26 14:10:00; author: joeb
|
||||
* comments: Fixed Typo In EMAC_RXC_PAUSE register
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.15
|
||||
* date: 2005/01/27 14:41:00; author: joeb
|
||||
* comments: Moved Common MMRs to cdefBF534.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* System MMR Register Map
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF537_H
|
||||
#define _CDEF_BF537_H
|
||||
|
||||
/* Include MMRs Common to BF534 */
|
||||
#include <asm/arch-bf537/cdefBF534.h>
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/arch-bf537/defBF537.h>
|
||||
|
||||
/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
|
||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||
#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
|
||||
#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
|
||||
#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
|
||||
#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
|
||||
#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
|
||||
#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
|
||||
#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
|
||||
#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
|
||||
#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
|
||||
#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
|
||||
#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
|
||||
#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
|
||||
#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
|
||||
#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
|
||||
#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
|
||||
#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
|
||||
#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
|
||||
#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
|
||||
#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
|
||||
|
||||
#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
|
||||
#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
|
||||
#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
|
||||
#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
|
||||
#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
|
||||
#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
|
||||
#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
|
||||
#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
|
||||
|
||||
#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
|
||||
#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
|
||||
#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
|
||||
#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
|
||||
#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
|
||||
|
||||
#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
|
||||
#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
|
||||
#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
|
||||
#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
|
||||
#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
|
||||
#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
|
||||
#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
|
||||
#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
|
||||
#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
|
||||
#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
|
||||
#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
|
||||
#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
|
||||
#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
|
||||
#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
|
||||
#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
|
||||
#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
|
||||
#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
|
||||
#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
|
||||
#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
|
||||
#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
|
||||
#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
|
||||
#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
|
||||
#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
|
||||
#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
|
||||
|
||||
#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
|
||||
#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
|
||||
#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
|
||||
#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
|
||||
#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
|
||||
#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
|
||||
#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
|
||||
#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
|
||||
#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
|
||||
#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
|
||||
#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
|
||||
#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
|
||||
#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
|
||||
#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
|
||||
#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
|
||||
#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
|
||||
#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
|
||||
#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
|
||||
#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
|
||||
#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
|
||||
#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
|
||||
#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
|
||||
#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
|
||||
|
||||
#endif /* _CDEF_BF537_H */
|
408
include/asm-blackfin/arch-bf537/cplbtab.h
Normal file
408
include/asm-blackfin/arch-bf537/cplbtab.h
Normal file
|
@ -0,0 +1,408 @@
|
|||
/*This file is subject to the terms and conditions of the GNU General Public
|
||||
* License.
|
||||
*
|
||||
* Blackfin BF533/2.6 support : LG Soft India
|
||||
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
|
||||
* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
|
||||
* shouldn't be victimized. cplbmgr.S search logic is corrected
|
||||
* to findout the appropriate victim.
|
||||
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
|
||||
* : LG Soft India
|
||||
*/
|
||||
#include <config.h>
|
||||
|
||||
#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
|
||||
#define __ARCH_BFINNOMMU_CPLBTAB_H
|
||||
|
||||
/*
|
||||
* ICPLB TABLE
|
||||
*/
|
||||
|
||||
.data
|
||||
/* This table is configurable */
|
||||
.align 4;
|
||||
|
||||
/* Data Attibutes*/
|
||||
|
||||
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
|
||||
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#endif
|
||||
|
||||
.align 4;
|
||||
.global _ipdt_table _ipdt_table:.byte4 0x00000000;
|
||||
.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
|
||||
.byte4 0x00400000;
|
||||
.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
|
||||
.byte4 0x00800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
|
||||
.byte4 0x00C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
|
||||
.byte4 0x01000000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
|
||||
.byte4 0x01400000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
|
||||
.byte4 0x01800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
|
||||
.byte4 0x01C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
|
||||
.byte4 0x02000000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
|
||||
.byte4 0x02400000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
|
||||
.byte4 0x02800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
|
||||
.byte4 0x02C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
|
||||
.byte4 0x03000000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
|
||||
.byte4 0x03400000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
|
||||
.byte4 0x03800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
|
||||
.byte4 0x03C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
|
||||
.byte4 0x20000000;
|
||||
.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
|
||||
|
||||
.byte4 0xffffffff; /* end of section - termination */
|
||||
|
||||
/*
|
||||
* PAGE DESCRIPTOR TABLE
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Till here we are discussing about the static memory management model.
|
||||
* However, the operating envoronments commonly define more CPLB
|
||||
* descriptors to cover the entire addressable memory than will fit into
|
||||
* the available on-chip 16 CPLB MMRs. When this happens, the below table
|
||||
* will be used which will hold all the potentially required CPLB descriptors
|
||||
*
|
||||
* This is how Page descriptor Table is implemented in uClinux/Blackfin.
|
||||
*/
|
||||
.global _dpdt_table _dpdt_table:.byte4 0x00000000;
|
||||
.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
|
||||
.byte4 0x00400000;
|
||||
.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
|
||||
.byte4 0x00800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
|
||||
.byte4 0x00C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
|
||||
.byte4 0x01000000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
|
||||
.byte4 0x01400000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
|
||||
.byte4 0x01800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
|
||||
.byte4 0x01C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
|
||||
.byte4 0x02000000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
|
||||
.byte4 0x02400000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
|
||||
.byte4 0x02800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
|
||||
.byte4 0x02C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
|
||||
.byte4 0x03000000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
|
||||
.byte4 0x03400000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
|
||||
.byte4 0x03800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
|
||||
.byte4 0x03C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
|
||||
.byte4 0x20000000;
|
||||
.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
|
||||
|
||||
#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
|
||||
.byte4 0xFF800000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF801000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF802000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF803000;
|
||||
.byte4(L1_DMEMORY);
|
||||
#endif
|
||||
.byte4 0xFF804000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF805000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF806000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF807000;
|
||||
.byte4(L1_DMEMORY);
|
||||
#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
|
||||
.byte4 0xFF900000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF901000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF902000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF903000;
|
||||
.byte4(L1_DMEMORY);
|
||||
#endif
|
||||
.byte4 0xFF904000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF905000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF906000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF907000;
|
||||
.byte4(L1_DMEMORY);
|
||||
|
||||
.byte4 0xFFB00000;
|
||||
.byte4(L1_DMEMORY);
|
||||
|
||||
.byte4 0xffffffff; /*end of section - termination */
|
||||
|
||||
#ifdef CONFIG_CPLB_INFO
|
||||
.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
|
||||
_ipdt_swapcount_table:
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 10 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 20 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 30 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 40 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 50 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 60 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 70 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 90 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 100 */
|
||||
|
||||
.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
|
||||
_dpdt_swapcount_table:
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 10 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 20 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 30 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 40 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 50 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 60 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 70 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 100 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 110 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 120 */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
|
2627
include/asm-blackfin/arch-bf537/defBF534.h
Normal file
2627
include/asm-blackfin/arch-bf537/defBF534.h
Normal file
File diff suppressed because it is too large
Load diff
488
include/asm-blackfin/arch-bf537/defBF537.h
Normal file
488
include/asm-blackfin/arch-bf537/defBF537.h
Normal file
|
@ -0,0 +1,488 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved.
|
||||
*
|
||||
***********************************************************************************
|
||||
*
|
||||
* This include file contains a list of macro "defines" to enable the programmer
|
||||
* to use symbolic names for register-access and bit-manipulation.
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.1
|
||||
* date: 2004/03/01 21:23:01; author: joeb
|
||||
* Initial revision
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.2
|
||||
* date: 2004/05/15 16:30:00; author: joeb
|
||||
* comments: removed I2C/IIC references, changed GPIO sections
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.3
|
||||
* date: 2004/06/08 12:25:00; author: joeb
|
||||
* comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed
|
||||
* FLAG references in GPIO register names
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.4
|
||||
* date: 2004/06/09 2:25:00; author: joeb
|
||||
* comments: fixed bit-defines for EMAC section, renamed EMAC count registers,
|
||||
* combined 2 Timer status registers into one
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.5
|
||||
* date: 2004/08/10 10:25:00; author: joeb
|
||||
* comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.6
|
||||
* date: 2004/08/17 16:25:00; author: joeb
|
||||
* comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.7
|
||||
* date: 2004/08/18 13:21:00; author: joeb
|
||||
* comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.8
|
||||
* date: 2004/08/20 10:24:00; author: joeb
|
||||
* comments: Renamed External DMA to Handshake MDMA
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.9
|
||||
* date: 2004/08/23 13:42:00; author: joeb
|
||||
* comments: Renamed Handshake DMA Register Set
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.10
|
||||
* date: 2004/09/07 11:21:00; author: joeb
|
||||
* comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names)
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.11
|
||||
* date: 2004/09/28 15:14:00; author: joeb
|
||||
* comments: Fixed CAN Mailbox Area
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.12
|
||||
* date: 2004/10/27 13:18:00; author: joeb
|
||||
* comments: Added IEEE EMAC Register Support
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.13
|
||||
* date: 2004/10/28 15:40:00; author: joeb
|
||||
* comments: Shortened EMAC Count Register Names
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.14
|
||||
* date: 2004/11/09 10:45:00; author: joeb
|
||||
* comments: Fixed WDSIZE macros
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.15
|
||||
* date: 2004/11/18 07:45:00; author: joeb
|
||||
* comments: Fixed TIMER_STATUS register, added EMAC macros
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.16
|
||||
* date: 2004/12/13 11:05:00; author: joeb
|
||||
* comments: Removed HI/LO macros (now Assembler mnemonics)
|
||||
* Renamed enable bit for HMDMA from EN to HMDMAEN
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.17
|
||||
* date: 2004/12/17 14:25:00; author: joeb
|
||||
* comments: Replaced C++ Single-Line Comments w/C-standard Comments
|
||||
* Changed EMAC EQ1024 TX/RX References to GE1024
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.18
|
||||
* date: 2005/01/05 10:50:00; author: joeb
|
||||
* comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks
|
||||
* Added mask values for field deposit protection
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.19
|
||||
* date: 2005/01/10 10:30:00; author: joeb
|
||||
* comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10.
|
||||
*
|
||||
* ----------------------------
|
||||
* revision 0.20
|
||||
* date: 2005/01/27 14:25:15; author: joeb
|
||||
* comments: Moved MMRs common to BF534 to BF534 header.
|
||||
*/
|
||||
#ifndef _DEF_BF537_H
|
||||
#define _DEF_BF537_H
|
||||
|
||||
/* Include all Core registers and bit definitions */
|
||||
#include <asm/arch-common/def_LPBlackfin.h>
|
||||
|
||||
/* Include all MMR and bit defines common to BF534 */
|
||||
#include <asm/arch-bf537/defBF534.h>
|
||||
|
||||
/*
|
||||
* Define EMAC Section Unique to BF536/BF537
|
||||
*/
|
||||
|
||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
||||
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
|
||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
|
||||
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
|
||||
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
|
||||
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
|
||||
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
|
||||
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
|
||||
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
|
||||
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
|
||||
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
|
||||
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
|
||||
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
|
||||
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
|
||||
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
|
||||
|
||||
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
|
||||
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
|
||||
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
|
||||
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
|
||||
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
|
||||
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
|
||||
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
|
||||
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
|
||||
|
||||
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
|
||||
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
|
||||
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
|
||||
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
|
||||
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
|
||||
|
||||
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
|
||||
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
|
||||
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
|
||||
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
|
||||
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
|
||||
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
|
||||
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
|
||||
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
|
||||
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
|
||||
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
|
||||
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
|
||||
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
|
||||
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
|
||||
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
|
||||
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
|
||||
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
|
||||
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
|
||||
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
|
||||
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
|
||||
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
|
||||
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
|
||||
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
|
||||
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
|
||||
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
|
||||
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
|
||||
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
|
||||
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
|
||||
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
|
||||
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
|
||||
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
|
||||
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
|
||||
|
||||
/* Listing for IEEE-Supported Count Registers */
|
||||
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
|
||||
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
|
||||
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
|
||||
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
|
||||
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
|
||||
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
|
||||
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
|
||||
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
|
||||
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
|
||||
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
|
||||
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
|
||||
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
|
||||
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
|
||||
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
|
||||
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
|
||||
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
|
||||
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
|
||||
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
|
||||
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
|
||||
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
|
||||
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
|
||||
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
|
||||
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
|
||||
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
|
||||
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
|
||||
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
|
||||
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
|
||||
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
|
||||
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
|
||||
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
|
||||
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
|
||||
|
||||
/*
|
||||
* System MMR Register Bits And Macros
|
||||
*
|
||||
* Disclaimer: All macros are intended to make C and Assembly code more readable.
|
||||
* Use these macros carefully, as any that do left shifts for field
|
||||
* depositing will result in the lower order bits being destroyed. Any
|
||||
* macro that shifts left to properly position the bit-field should be
|
||||
* used as part of an OR to initialize a register and NOT as a dynamic
|
||||
* modifier UNLESS the lower order bits are saved and ORed back in when
|
||||
* the macro is used.
|
||||
*/
|
||||
/*
|
||||
* ETHERNET 10/100 CONTROLLER MASKS
|
||||
*/
|
||||
/* EMAC_OPMODE Masks */
|
||||
#define RE 0x00000001 /* Receiver Enable */
|
||||
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
|
||||
#define HU 0x00000010 /* Hash Filter Unicast Address */
|
||||
#define HM 0x00000020 /* Hash Filter Multicast Address */
|
||||
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
|
||||
#define PR 0x00000080 /* Promiscuous Mode Enable */
|
||||
#define IFE 0x00000100 /* Inverse Filtering Enable */
|
||||
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
|
||||
#define PBF 0x00000400 /* Pass Bad Frames Enable */
|
||||
#define PSF 0x00000800 /* Pass Short Frames Enable */
|
||||
#define RAF 0x00001000 /* Receive-All Mode */
|
||||
#define TE 0x00010000 /* Transmitter Enable */
|
||||
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
|
||||
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
|
||||
#define DC 0x00080000 /* Deferral Check */
|
||||
#define BOLMT 0x00300000 /* Back-Off Limit */
|
||||
#define BOLMT_10 0x00000000 /* 10-bit range */
|
||||
#define BOLMT_8 0x00100000 /* 8-bit range */
|
||||
#define BOLMT_4 0x00200000 /* 4-bit range */
|
||||
#define BOLMT_1 0x00300000 /* 1-bit range */
|
||||
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
|
||||
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
|
||||
#define RMII 0x01000000 /* RMII/MII* Mode */
|
||||
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
|
||||
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
|
||||
#define LB 0x08000000 /* Internal Loopback Enable */
|
||||
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
|
||||
|
||||
/* EMAC_STAADD Masks */
|
||||
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
|
||||
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
|
||||
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
|
||||
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
|
||||
#define REGAD 0x000007C0 /* STA Register Address */
|
||||
#define PHYAD 0x0000F800 /* PHY Device Address */
|
||||
|
||||
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
|
||||
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
|
||||
|
||||
/* EMAC_STADAT Mask */
|
||||
#define STADATA 0x0000FFFF /* Station Management Data */
|
||||
|
||||
/* EMAC_FLC Masks */
|
||||
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
|
||||
#define FLCE 0x00000002 /* Flow Control Enable */
|
||||
#define PCF 0x00000004 /* Pass Control Frames */
|
||||
#define BKPRSEN 0x00000008 /* Enable Backpressure */
|
||||
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
|
||||
|
||||
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
|
||||
|
||||
/* EMAC_WKUP_CTL Masks */
|
||||
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
|
||||
#define MPKE 0x00000002 /* Magic Packet Enable */
|
||||
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
|
||||
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
|
||||
#define MPKS 0x00000020 /* Magic Packet Received Status */
|
||||
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
|
||||
|
||||
/* EMAC_WKUP_FFCMD Masks */
|
||||
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
|
||||
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
|
||||
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
|
||||
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
|
||||
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
|
||||
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
|
||||
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
|
||||
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
|
||||
|
||||
/* EMAC_WKUP_FFOFF Masks */
|
||||
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
|
||||
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
|
||||
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
|
||||
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
|
||||
|
||||
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
|
||||
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
|
||||
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
|
||||
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
|
||||
/* Set ALL Offsets */
|
||||
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
|
||||
|
||||
/* EMAC_WKUP_FFCRC0 Masks */
|
||||
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
|
||||
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
|
||||
|
||||
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 0 Target CRC */
|
||||
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 1 Target CRC */
|
||||
|
||||
/* EMAC_WKUP_FFCRC1 Masks */
|
||||
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
|
||||
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
|
||||
|
||||
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 2 Target CRC */
|
||||
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 3 Target CRC */
|
||||
|
||||
/* EMAC_SYSCTL Masks */
|
||||
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
|
||||
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
|
||||
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
|
||||
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
|
||||
|
||||
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
|
||||
|
||||
/* EMAC_SYSTAT Masks */
|
||||
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
|
||||
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
|
||||
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
|
||||
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
|
||||
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
|
||||
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
|
||||
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
|
||||
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
|
||||
|
||||
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
|
||||
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
|
||||
#define RX_COMP 0x00001000 /* RX Frame Complete */
|
||||
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
|
||||
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
|
||||
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
|
||||
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
|
||||
#define RX_LEN 0x00020000 /* RX Frame Length Error */
|
||||
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
|
||||
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
|
||||
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
|
||||
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
|
||||
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
|
||||
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
|
||||
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
|
||||
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
|
||||
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
|
||||
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
|
||||
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
|
||||
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
|
||||
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
|
||||
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
|
||||
|
||||
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
|
||||
#define TX_COMP 0x00000001 /* TX Frame Complete */
|
||||
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
|
||||
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
|
||||
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
|
||||
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
|
||||
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
|
||||
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
|
||||
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
|
||||
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
|
||||
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
|
||||
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
|
||||
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
|
||||
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
|
||||
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
|
||||
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
|
||||
|
||||
/* EMAC_MMC_CTL Masks */
|
||||
#define RSTC 0x00000001 /* Reset All Counters */
|
||||
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
|
||||
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
|
||||
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
|
||||
|
||||
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
|
||||
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
|
||||
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
|
||||
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
|
||||
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
|
||||
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
|
||||
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
|
||||
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
|
||||
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
|
||||
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
|
||||
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
|
||||
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
|
||||
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
|
||||
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
|
||||
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
|
||||
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
|
||||
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
|
||||
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
|
||||
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
|
||||
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
|
||||
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
|
||||
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
|
||||
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
|
||||
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
|
||||
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
|
||||
|
||||
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
|
||||
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
|
||||
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
|
||||
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
|
||||
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
|
||||
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
|
||||
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
|
||||
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
|
||||
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
|
||||
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
|
||||
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
|
||||
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
|
||||
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
|
||||
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
|
||||
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
|
||||
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
|
||||
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
|
||||
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
|
||||
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
|
||||
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
|
||||
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
|
||||
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
|
||||
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
|
||||
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
|
||||
|
||||
#endif /* _DEF_BF537_H */
|
76
include/asm-blackfin/arch-bf537/defBF537_extn.h
Normal file
76
include/asm-blackfin/arch-bf537/defBF537_extn.h
Normal file
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* defBF537_extn.h
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Non-GPL License also available as part of VisualDSP++
|
||||
*
|
||||
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
|
||||
*
|
||||
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
|
||||
*
|
||||
* This file under source code control, please send bugs or changes to:
|
||||
* dsptools.support@analog.com
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF537_EXTN_H
|
||||
#define _DEF_BF537_EXTN_H
|
||||
|
||||
#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
|
||||
/* Delay inserted for PLL transition */
|
||||
#define PLL_DELAY 0x1000
|
||||
|
||||
#define L1_ISRAM 0xFFA00000
|
||||
#define L1_ISRAM_END 0xFFA10000
|
||||
#define DATA_BANKA_SRAM 0xFF800000
|
||||
#define DATA_BANKA_SRAM_END 0xFF808000
|
||||
#define DATA_BANKB_SRAM 0xFF900000
|
||||
#define DATA_BANKB_SRAM_END 0xFF908000
|
||||
#define SYSMMR_BASE 0xFFC00000
|
||||
#define WDSIZE16 0x00000004
|
||||
|
||||
/* Event Vector Table Address */
|
||||
#define EVT_EMULATION_ADDR 0xffe02000
|
||||
#define EVT_RESET_ADDR 0xffe02004
|
||||
#define EVT_NMI_ADDR 0xffe02008
|
||||
#define EVT_EXCEPTION_ADDR 0xffe0200c
|
||||
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
|
||||
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
|
||||
#define EVT_TIMER_ADDR 0xffe02018
|
||||
#define EVT_IVG7_ADDR 0xffe0201c
|
||||
#define EVT_IVG8_ADDR 0xffe02020
|
||||
#define EVT_IVG9_ADDR 0xffe02024
|
||||
#define EVT_IVG10_ADDR 0xffe02028
|
||||
#define EVT_IVG11_ADDR 0xffe0202c
|
||||
#define EVT_IVG12_ADDR 0xffe02030
|
||||
#define EVT_IVG13_ADDR 0xffe02034
|
||||
#define EVT_IVG14_ADDR 0xffe02038
|
||||
#define EVT_IVG15_ADDR 0xffe0203c
|
||||
#define EVT_OVERRIDE_ADDR 0xffe02100
|
||||
|
||||
/* IMASK Bit values */
|
||||
#define IVG15_POS 0x00008000
|
||||
#define IVG14_POS 0x00004000
|
||||
#define IVG13_POS 0x00002000
|
||||
#define IVG12_POS 0x00001000
|
||||
#define IVG11_POS 0x00000800
|
||||
#define IVG10_POS 0x00000400
|
||||
#define IVG9_POS 0x00000200
|
||||
#define IVG8_POS 0x00000100
|
||||
#define IVG7_POS 0x00000080
|
||||
#define IVGTMR_POS 0x00000040
|
||||
#define IVGHW_POS 0x00000020
|
||||
|
||||
#define WDOG_TMR_DISABLE (0xAD << 4)
|
||||
#define ICTL_RST 0x00000000
|
||||
#define ICTL_NMI 0x00000002
|
||||
#define ICTL_GP 0x00000004
|
||||
#define ICTL_DISABLE 0x00000003
|
||||
|
||||
/* Watch Dog timer values setup */
|
||||
#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
|
||||
|
||||
#endif /* _DEF_BF537_EXTN_H */
|
94
include/asm-blackfin/arch-bf537/irq.h
Normal file
94
include/asm-blackfin/arch-bf537/irq.h
Normal file
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* U-boot bf537_irq.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
*
|
||||
* This file is based on
|
||||
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
|
||||
* Changed by HuTao Apr18, 2003
|
||||
*
|
||||
* Copyright was missing when I got the code so took from MIPS arch ...MaTed---
|
||||
* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
|
||||
* Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
|
||||
*
|
||||
* Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
|
||||
* Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
|
||||
* Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
|
||||
*
|
||||
* Adapted for BlackFin BF537 by Bas Vermeulen <bas@buyways.nl>
|
||||
* Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
|
||||
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _BF537_IRQ_H_
|
||||
#define _BF537_IRQ_H_
|
||||
|
||||
/*
|
||||
* Interrupt source definitions
|
||||
* Event Source Core Event Name Number
|
||||
* EMU 0
|
||||
* Reset RST 1
|
||||
* NMI NMI 2
|
||||
* Exception EVX 3
|
||||
* Reserved -- 4
|
||||
* Hardware Error IVHW 5
|
||||
* Core Timer IVTMR 6
|
||||
* PLL Wakeup Interrupt IVG7 7
|
||||
* DMA Error (generic) IVG7 8
|
||||
* PPI Error Interrupt IVG7 9
|
||||
* SPORT0 Error Interrupt IVG7 10
|
||||
* SPORT1 Error Interrupt IVG7 11
|
||||
* SPI Error Interrupt IVG7 12
|
||||
* UART Error Interrupt IVG7 13
|
||||
* RTC Interrupt IVG8 14
|
||||
* DMA0 Interrupt (PPI) IVG8 15
|
||||
* DMA1 (SPORT0 RX) IVG9 16
|
||||
* DMA2 (SPORT0 TX) IVG9 17
|
||||
* DMA3 (SPORT1 RX) IVG9 18
|
||||
* DMA4 (SPORT1 TX) IVG9 19
|
||||
* DMA5 (PPI) IVG10 20
|
||||
* DMA6 (UART RX) IVG10 21
|
||||
* DMA7 (UART TX) IVG10 22
|
||||
* Timer0 IVG11 23
|
||||
* Timer1 IVG11 24
|
||||
* Timer2 IVG11 25
|
||||
* PF Interrupt A IVG12 26
|
||||
* PF Interrupt B IVG12 27
|
||||
* DMA8/9 Interrupt IVG13 28
|
||||
* DMA10/11 Interrupt IVG13 29
|
||||
* Watchdog Timer IVG13 30
|
||||
* Software Interrupt 1 IVG14 31
|
||||
* Software Interrupt 2 --
|
||||
* (lowest priority) IVG15 32
|
||||
*/
|
||||
|
||||
#define IRQ_EMU 0 /* Emulation */
|
||||
#define IRQ_RST 1 /* reset */
|
||||
#define IRQ_NMI 2 /* Non Maskable */
|
||||
#define IRQ_EVX 3 /* Exception */
|
||||
#define IRQ_UNUSED 4 /* - unused interrupt */
|
||||
#define IRQ_HWERR 5 /* Hardware Error */
|
||||
#define IRQ_CORETMR 6 /* Core timer */
|
||||
|
||||
#define IRQ_UART_RX_BIT 0x0800
|
||||
#define IRQ_UART_TX_BIT 0x1000
|
||||
#define IRQ_UART_ERROR_BIT 0x40
|
||||
|
||||
#endif
|
502
include/configs/bf537-stamp.h
Normal file
502
include/configs/bf537-stamp.h
Normal file
|
@ -0,0 +1,502 @@
|
|||
/*
|
||||
* U-boot - Configuration file for BF537 STAMP board
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_BF537_H__
|
||||
#define __CONFIG_BF537_H__
|
||||
|
||||
#define CFG_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_BAUDRATE 57600
|
||||
/* Set default serial console for bf537 */
|
||||
#define CONFIG_UART_CONSOLE 0
|
||||
#define CONFIG_BF537 1
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
|
||||
/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
|
||||
|
||||
/*
|
||||
* Boot Mode Set
|
||||
* Blackfin can support several boot modes
|
||||
*/
|
||||
#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
|
||||
#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
|
||||
#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */
|
||||
#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */
|
||||
#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */
|
||||
#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */
|
||||
#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */
|
||||
/* Define the boot mode */
|
||||
#define BFIN_BOOT_MODE BF537_BYPASS_BOOT
|
||||
|
||||
#define CONFIG_PANIC_HANG 1
|
||||
|
||||
#define ADSP_BF534 0x34
|
||||
#define ADSP_BF536 0x36
|
||||
#define ADSP_BF537 0x37
|
||||
#define BFIN_CPU ADSP_BF537
|
||||
|
||||
/* This sets the default state of the cache on U-Boot's boot */
|
||||
#define CONFIG_ICACHE_ON
|
||||
#define CONFIG_DCACHE_ON
|
||||
|
||||
/* Define if want to do post memory test */
|
||||
#undef CONFIG_POST_TEST
|
||||
|
||||
/* Define where the uboot will be loaded by on-chip boot rom */
|
||||
#define APP_ENTRY 0x00001000
|
||||
|
||||
#define CONFIG_RTC_BFIN 1
|
||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
|
||||
|
||||
/* CONFIG_CLKIN_HZ is any value in Hz */
|
||||
#define CONFIG_CLKIN_HZ 25000000
|
||||
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
|
||||
/* 1=CLKIN/2 */
|
||||
#define CONFIG_CLKIN_HALF 0
|
||||
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
|
||||
/* 1=bypass PLL*/
|
||||
#define CONFIG_PLL_BYPASS 0
|
||||
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
|
||||
/* Values can range from 1-64 */
|
||||
#define CONFIG_VCO_MULT 20
|
||||
/* CONFIG_CCLK_DIV controls what the core clock divider is */
|
||||
/* Values can be 1, 2, 4, or 8 ONLY */
|
||||
#define CONFIG_CCLK_DIV 1
|
||||
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
|
||||
/* Values can range from 1-15 */
|
||||
#define CONFIG_SCLK_DIV 5
|
||||
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
|
||||
/* Values can range from 2-65535 */
|
||||
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
|
||||
#define CONFIG_SPI_BAUD 2
|
||||
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
#define CONFIG_SPI_BAUD_INITBLOCK 4
|
||||
#endif
|
||||
|
||||
#if ( CONFIG_CLKIN_HALF == 0 )
|
||||
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
|
||||
#else
|
||||
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
|
||||
#endif
|
||||
|
||||
#if (CONFIG_PLL_BYPASS == 0)
|
||||
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
|
||||
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
|
||||
#else
|
||||
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
|
||||
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
|
||||
#endif
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
|
||||
#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
|
||||
#else
|
||||
#undef CONFIG_SPI_FLASH_FAST_READ
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
|
||||
#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
|
||||
#define CONFIG_MEM_MT48LC32M8A2_75 1
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1
|
||||
|
||||
/*
|
||||
* rarpb, bootp or dhcp commands will perform only a
|
||||
* configuration lookup from the BOOTP/DHCP server
|
||||
* but not try to load any image using TFTP
|
||||
*/
|
||||
#define CFG_AUTOLOAD "no"
|
||||
|
||||
/*
|
||||
* Network Settings
|
||||
*/
|
||||
/* network support */
|
||||
#if (BFIN_CPU != ADSP_BF534)
|
||||
#define CONFIG_IPADDR 192.168.0.15
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_GATEWAYIP 192.168.0.1
|
||||
#define CONFIG_SERVERIP 192.168.0.2
|
||||
#define CONFIG_HOSTNAME BF537
|
||||
#endif
|
||||
|
||||
#define CONFIG_ROOTPATH /romfs
|
||||
/* Uncomment next line to use fixed MAC address */
|
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
|
||||
/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
|
||||
|
||||
#define CFG_LONGHELP 1
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
|
||||
#define CONFIG_BOOTCOMMAND "run ramboot"
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
|
||||
/* POST support */
|
||||
#define CONFIG_POST ( CFG_POST_MEMORY | \
|
||||
CFG_POST_UART | \
|
||||
CFG_POST_FLASH | \
|
||||
CFG_POST_ETHER | \
|
||||
CFG_POST_LED | \
|
||||
CFG_POST_BUTTON)
|
||||
#else
|
||||
#undef CONFIG_POST
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
|
||||
#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
|
||||
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
|
||||
#else
|
||||
#define CFG_CMD_POST_DIAG 0
|
||||
#endif
|
||||
|
||||
/* CF-CARD IDE-HDD Support */
|
||||
|
||||
/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
|
||||
/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
|
||||
/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
|
||||
|
||||
#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
|
||||
# define CONFIG_BFIN_IDE 1
|
||||
# define ADD_IDE_CMD CFG_CMD_IDE
|
||||
#else
|
||||
# define ADD_IDE_CMD 0
|
||||
#endif
|
||||
|
||||
/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
|
||||
|
||||
#ifdef CONFIG_BF537_NAND
|
||||
# define ADD_NAND_CMD CFG_CMD_NAND
|
||||
#else
|
||||
# define ADD_NAND_CMD 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_NETCONSOLE 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
|
||||
#if (BFIN_CPU == ADSP_BF534)
|
||||
#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET)
|
||||
#else
|
||||
#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING)
|
||||
#endif
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
|
||||
#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DHCP | \
|
||||
ADD_IDE_CMD | \
|
||||
ADD_NAND_CMD | \
|
||||
CFG_CMD_POST_DIAG | \
|
||||
CFG_CMD_DATE)
|
||||
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_EEPROM | \
|
||||
ADD_IDE_CMD | \
|
||||
CFG_CMD_DATE)
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
|
||||
#define CONFIG_LOADADDR 0x1000000
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
|
||||
#if (BFIN_CPU != ADSP_BF534)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):eth0:off\0" \
|
||||
"ramboot=tftpboot $(loadaddr) linux;" \
|
||||
"run ramargs;run addip;bootelf\0" \
|
||||
"nfsboot=tftpboot $(loadaddr) linux;" \
|
||||
"run nfsargs;run addip;bootelf\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
"update=tftpboot $(loadaddr) u-boot.bin;" \
|
||||
"protect off 0x20000000 0x2007FFFF;" \
|
||||
"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
|
||||
""
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
""
|
||||
#endif
|
||||
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
#if (BFIN_CPU != ADSP_BF534)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):eth0:off\0" \
|
||||
"ramboot=tftpboot $(loadaddr) linux;" \
|
||||
"run ramargs;run addip;bootelf\0" \
|
||||
"nfsboot=tftpboot $(loadaddr) linux;" \
|
||||
"run nfsargs;run addip;bootelf\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
"update=tftpboot $(loadaddr) u-boot.ldr;" \
|
||||
"eeprom write $(loadaddr) 0x0 $(filesize);\0" \
|
||||
""
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
""
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
#if (BFIN_CPU == ADSP_BF534)
|
||||
#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */
|
||||
#elif (BFIN_CPU == ADSP_BF536)
|
||||
#define CFG_PROMPT "serial_bf536> " /* Monitor Command Prompt */
|
||||
#else
|
||||
#define CFG_PROMPT "serial_bf537> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
#else
|
||||
#if (BFIN_CPU == ADSP_BF534)
|
||||
#define CFG_PROMPT "bf534> " /* Monitor Command Prompt */
|
||||
#elif (BFIN_CPU == ADSP_BF536)
|
||||
#define CFG_PROMPT "bf536> " /* Monitor Command Prompt */
|
||||
#else
|
||||
#define CFG_PROMPT "bf537> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_MEMTEST_START 0x0 /* memtest works on */
|
||||
#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
|
||||
#define CFG_LOAD_ADDR CONFIG_LOADADDR /* default load address */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
|
||||
#define CFG_FLASH_BASE 0x20000000
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
|
||||
#define CFG_GBL_DATA_SIZE 0x4000
|
||||
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
|
||||
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
|
||||
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
|
||||
/* for bf537-stamp, usrt boot mode still store env in flash */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR 0x20004000
|
||||
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
|
||||
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
|
||||
#define CFG_ENV_IS_IN_EEPROM 1
|
||||
#define CFG_ENV_OFFSET 0x4000
|
||||
#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
|
||||
#endif
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
|
||||
#define ENV_IS_EMBEDDED
|
||||
/* #endif */
|
||||
|
||||
/* JFFS Partition offset set */
|
||||
#define CFG_JFFS2_FIRST_BANK 0
|
||||
#define CFG_JFFS2_NUM_BANKS 1
|
||||
/* 512k reserved for u-boot */
|
||||
#define CFG_JFFS2_FIRST_SECTOR 15
|
||||
|
||||
#define CONFIG_SPI
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
|
||||
#define POLL_MODE 1
|
||||
#define FLASH_TOT_SECT 71
|
||||
#define FLASH_SIZE 0x400000
|
||||
#define CFG_FLASH_SIZE 0x400000
|
||||
|
||||
/*
|
||||
* Board NAND Infomation
|
||||
*/
|
||||
|
||||
#define CFG_NAND_ADDR 0x20212000
|
||||
#define CFG_NAND_BASE CFG_NAND_ADDR
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define SECTORSIZE 512
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define BFIN_NAND_READY PF3
|
||||
|
||||
#define NAND_WAIT_READY(nand) \
|
||||
do { \
|
||||
int timeout = 0; \
|
||||
while(!(*pPORTFIO & PF3)) \
|
||||
if (timeout++ > 100000) \
|
||||
break; \
|
||||
} while (0)
|
||||
|
||||
#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
|
||||
#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
|
||||
/*
|
||||
* Initialize PSD4256 registers for using I2C
|
||||
*/
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
|
||||
|
||||
/*
|
||||
* I2C settings
|
||||
* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
|
||||
*/
|
||||
/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */
|
||||
#define CONFIG_HARD_I2C 1 /* I2C TWI */
|
||||
#if defined CONFIG_HARD_I2C
|
||||
#define CONFIG_TWICLK_KHZ 50
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_SOFT_I2C
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define PF_SCL PF0
|
||||
#define PF_SDA PF1
|
||||
|
||||
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
|
||||
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
|
||||
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
|
||||
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
|
||||
#define I2C_SDA(bit) if(bit) { \
|
||||
*pFIO_FLAG_S = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
}
|
||||
#define I2C_SCL(bit) if(bit) { \
|
||||
*pFIO_FLAG_S = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
}
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
#endif
|
||||
|
||||
#define CFG_I2C_SPEED 50000
|
||||
#define CFG_I2C_SLAVE 0xFE
|
||||
|
||||
/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
|
||||
/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
||||
#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
|
||||
~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
|
||||
#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
|
||||
B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
|
||||
*/
|
||||
|
||||
#define AMGCTLVAL 0xFF
|
||||
#define AMBCTL0VAL 0x7BB07BB0
|
||||
#define AMBCTL1VAL 0xFFC27BB0
|
||||
|
||||
#define CONFIG_VDSP 1
|
||||
|
||||
#ifdef CONFIG_VDSP
|
||||
#define ET_EXEC_VDSP 0x8
|
||||
#define SHT_STRTAB_VDSP 0x1
|
||||
#define ELFSHDRSIZE_VDSP 0x2C
|
||||
#define VDSP_ENTRY_ADDR 0xFFA00000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BFIN_IDE)
|
||||
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
/*
|
||||
* IDE/ATA stuff
|
||||
*/
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
|
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
|
||||
|
||||
#undef AMBCTL1VAL
|
||||
#define AMBCTL1VAL 0xFFC3FFC3
|
||||
|
||||
#define CONFIG_CF_ATASEL_DIS 0x20311800
|
||||
#define CONFIG_CF_ATASEL_ENA 0x20311802
|
||||
|
||||
#if defined(CONFIG_BFIN_TRUE_IDE)
|
||||
/*
|
||||
* Note that these settings aren't for the most part used in include/ata.h
|
||||
* when all of the ATA registers are setup
|
||||
*/
|
||||
#define CFG_ATA_BASE_ADDR 0x2031C000
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
|
||||
#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
|
||||
#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
|
||||
#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
|
||||
#endif /* CONFIG_BFIN_TRUE_IDE */
|
||||
|
||||
#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
|
||||
#define CFG_ATA_BASE_ADDR 0x20211800
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
|
||||
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
|
||||
#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
|
||||
#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
|
||||
#endif /* CONFIG_BFIN_CF_IDE */
|
||||
|
||||
#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
|
||||
#define CFG_ATA_BASE_ADDR 0x20314000
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
|
||||
#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
|
||||
#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
|
||||
#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
|
||||
|
||||
#undef CONFIG_SCLK_DIV
|
||||
#define CONFIG_SCLK_DIV 8
|
||||
#endif /* CONFIG_BFIN_HDD_IDE */
|
||||
|
||||
#endif /*CONFIG_BFIN_IDE */
|
||||
|
||||
#endif
|
Loading…
Reference in a new issue