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pci: Add mask parameter to dm_pci_map_bar()

Browse source 
Add a mask parameter to control the lookup of the PCI region from which
the mapping can be made.

Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Andrew Scull 2022-04-21 16:11:13 +00:00 committed by Tom Rini
parent a822d1dee4
commit 2635e3b50f
33 changed files with 61 additions and 47 deletions
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2
arch/x86/cpu/baytrail/cpu.c
View file

@ -56,7 +56,7 @@ static int baytrail_uart_init(void *ctx, struct event *event)
for (i = 0; i < 2; i++) {
ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev);
if (!ret) {
base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
hsuart_clock_set(base);
}

7
drivers/ata/ahci.c
View file

@ -417,7 +417,7 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
#if !defined(CONFIG_DM_SCSI)
uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 0, 0,
PCI_REGION_MEM);
PCI_REGION_TYPE, PCI_REGION_MEM);
/* Take from kernel:
* JMicron-specific fixup:
@ -1149,7 +1149,7 @@ int ahci_probe_scsi_pci(struct udevice *ahci_dev)
u16 vendor, device;
base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 0, 0,
PCI_REGION_MEM);
PCI_REGION_TYPE, PCI_REGION_MEM);
/*
* Note:
@ -1163,7 +1163,8 @@ int ahci_probe_scsi_pci(struct udevice *ahci_dev)
if (vendor == PCI_VENDOR_ID_CAVIUM &&
device == PCI_DEVICE_ID_CAVIUM_SATA)
base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0, 0, 0,
base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
return ahci_probe_scsi(ahci_dev, base);
}

6
drivers/ata/sata_sil.c
View file

@ -699,9 +699,11 @@ static int sil_pci_probe(struct udevice *dev)
/* Read out all BARs */
sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_MEM);
PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
/* mask out the unused bits */
sata_info.iobase[0] &= 0xffffff80;

2
drivers/gpio/octeon_gpio.c
View file

@ -183,7 +183,7 @@ static int octeon_gpio_probe(struct udevice *dev)
priv->data = (const struct octeon_gpio_data *)dev_get_driver_data(dev);
if (priv->data->probe == PROBE_PCI) {
priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
uc_priv->gpio_count = readq(priv->base +
priv->data->reg_offs + GPIO_CONST) &

3
drivers/i2c/designware_i2c_pci.c
View file

@ -59,7 +59,8 @@ static int designware_i2c_pci_of_to_plat(struct udevice *dev)
priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
} else {
priv->regs = (struct i2c_regs *)
dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
}
if (!priv->regs)
return -EINVAL;

2
drivers/i2c/intel_i2c.c
View file

@ -251,7 +251,7 @@ static int intel_i2c_probe(struct udevice *dev)
ulong base;
/* Save base address from PCI BAR */
priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0,
priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE,
PCI_REGION_IO);
base = priv->base;

2
drivers/i2c/octeon_i2c.c
View file

@ -792,7 +792,7 @@ static int octeon_i2c_probe(struct udevice *dev)
debug("TWSI PCI device: %x\n", bdf);
twsi->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
twsi->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
} else {
twsi->base = dev_remap_addr(dev);

2
drivers/mmc/octeontx_hsmmc.c
View file

@ -3822,7 +3822,7 @@ static int octeontx_mmc_host_probe(struct udevice *dev)
/* Octeon TX & TX2 use PCI based probing */
if (device_is_compatible(dev, "cavium,thunder-8890-mmc")) {
host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
if (!host->base_addr) {
pr_err("%s: Error: MMC base address not found\n",

2
drivers/mmc/pci_mmc.c
View file

@ -50,7 +50,7 @@ static int pci_mmc_probe(struct udevice *dev)
desc = mmc_get_blk_desc(&plat->mmc);
desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE);
host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
host->name = dev->name;
host->cd_gpio = priv->cd_gpio;

6
drivers/mtd/nand/raw/octeontx_bch.c
View file

@ -176,7 +176,8 @@ static int octeontx_pci_bchpf_probe(struct udevice *dev)
if (!bch)
return -ENOMEM;
bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
bch->dev = dev;
debug("%s: base address: %p\n", __func__, bch->reg_base);
@ -361,7 +362,8 @@ static int octeontx_pci_bchvf_probe(struct udevice *dev)
vf->dev = dev;
/* Map PF's configuration registers */
vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
debug("%s: reg base: %p\n", __func__, vf->reg_base);
err = octeontx_cmd_queue_initialize(dev, QID_BCH, QDEPTH - 1, 0,

2
drivers/mtd/nand/raw/octeontx_nand.c
View file

@ -2098,7 +2098,7 @@ static int octeontx_pci_nand_probe(struct udevice *dev)
tn->dev = dev;
INIT_LIST_HEAD(&tn->chips);
tn->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
tn->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM);
if (!tn->base) {
ret = -EINVAL;
goto release;

9
drivers/net/bnxt/bnxt.c
View file

@ -28,9 +28,12 @@ static void bnxt_bring_pci(struct bnxt *bp)
dm_pci_read_config16(bp->pdev, PCI_SUBSYSTEM_ID, &bp->subsystem_device);
dm_pci_read_config16(bp->pdev, PCI_COMMAND, &bp->cmd_reg);
dm_pci_read_config8(bp->pdev, PCI_INTERRUPT_LINE, &bp->irq);
bp->bar0 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
bp->bar1 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_MEM);
bp->bar2 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_MEM);
bp->bar0 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
bp->bar1 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
bp->bar2 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
cmd_reg |= PCI_COMMAND_INTX_DISABLE; /* disable intr */
dm_pci_write_config16(bp->pdev, PCI_COMMAND, cmd_reg);

2
drivers/net/e1000.c
View file

@ -5550,7 +5550,7 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
#endif
#ifdef CONFIG_DM_ETH
hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_MEM);
PCI_REGION_TYPE, PCI_REGION_MEM);
#else
hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);

2
drivers/net/fsl_enetc.c
View file

@ -339,7 +339,7 @@ static int enetc_probe(struct udevice *dev)
}
/* initialize register */
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, 0);
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0);
if (!priv->regs_base) {
enetc_dbg(dev, "failed to map BAR0\n");
return -EINVAL;

2
drivers/net/fsl_enetc_mdio.c
View file

@ -125,7 +125,7 @@ static int enetc_mdio_probe(struct udevice *dev)
{
struct enetc_mdio_priv *priv = dev_get_priv(dev);
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, 0);
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0);
if (!priv->regs_base) {
enetc_dbg(dev, "failed to map BAR0\n");
return -EINVAL;

4
drivers/net/mscc_eswitch/felix_switch.c
View file

@ -292,13 +292,13 @@ static int felix_probe(struct udevice *dev)
return -ENODEV;
}
priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, 0);
priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0);
if (!priv->imdio_base) {
dev_err(dev, "failed to map BAR0\n");
return -EINVAL;
}
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0, 0);
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE, 0);
if (!priv->regs_base) {
dev_err(dev, "failed to map BAR4\n");
return -EINVAL;

2
drivers/net/octeontx/bgx.c
View file

@ -1458,7 +1458,7 @@ int octeontx_bgx_probe(struct udevice *dev)
int bgx_idx, node;
int inc = 1;
bgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
bgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
if (!bgx->reg_base) {
debug("No PCI region found\n");

2
drivers/net/octeontx/nic_main.c
View file

@ -713,7 +713,7 @@ int nic_initialize(struct udevice *dev)
return -ENOMEM;
/* MAP PF's configuration registers */
nic->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
nic->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
if (!nic->reg_base) {
printf("Cannot map config register space, aborting\n");

2
drivers/net/octeontx/nicvf_main.c
View file

@ -509,7 +509,7 @@ int nicvf_initialize(struct udevice *dev)
/* Enable TSO support */
nicvf->hw_tso = true;
nicvf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
nicvf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
debug("nicvf->reg_base: %p\n", nicvf->reg_base);

2
drivers/net/octeontx/smi.c
View file

@ -322,7 +322,7 @@ int octeontx_smi_probe(struct udevice *dev)
u64 baseaddr;
debug("SMI PCI device: %x\n", bdf);
if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM)) {
if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM)) {
printf("Failed to map PCI region for bdf %x\n", bdf);
return -1;
}

2
drivers/net/octeontx2/cgx.c
View file

@ -253,7 +253,7 @@ int cgx_probe(struct udevice *dev)
struct cgx *cgx = dev_get_priv(dev);
int err;
cgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
cgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
cgx->dev = dev;
cgx->cgx_id = ((u64)(cgx->reg_base) >> 24) & 0x7;

2
drivers/net/octeontx2/rvu_af.c
View file

@ -127,7 +127,7 @@ int rvu_af_probe(struct udevice *dev)
{
struct rvu_af *af_ptr = dev_get_priv(dev);
af_ptr->af_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
af_ptr->af_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
debug("%s RVU AF BAR %p\n", __func__, af_ptr->af_base);
af_ptr->dev = dev;

3
drivers/net/octeontx2/rvu_pf.c
View file

@ -58,7 +58,8 @@ int rvu_pf_probe(struct udevice *dev)
debug("%s: name: %s\n", __func__, dev->name);
rvu->pf_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_MEM);
rvu->pf_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
rvu->pfid = dev_seq(dev) + 1; // RVU PF's start from 1;
rvu->dev = dev;
if (!rvu_af_dev) {

2
drivers/net/pch_gbe.c
View file

@ -449,7 +449,7 @@ static int pch_gbe_probe(struct udevice *dev)
priv->dev = dev;
iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_MEM);
iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM);
plat->iobase = (ulong)iobase;
priv->mac_regs = (struct pch_gbe_regs *)iobase;

2
drivers/nvme/nvme_pci.c
View file

@ -29,7 +29,7 @@ static int nvme_probe(struct udevice *udev)
ndev->instance = trailing_strtol(udev->name);
ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_MEM);
PCI_REGION_TYPE, PCI_REGION_MEM);
return nvme_init(udev);
}

6
drivers/pci/pci-uclass.c
View file

@ -1556,7 +1556,7 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, size_t offset,
}
void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
unsigned long flags)
unsigned long mask, unsigned long flags)
{
struct pci_child_plat *pdata = dev_get_parent_plat(dev);
struct udevice *udev = dev;
@ -1596,8 +1596,8 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
* a PCI range, but a better check would be to probe for the size of
* the bar and prevent overflow more locally.
*/
return dm_pci_bus_to_virt(udev, pci_bus_addr + offset, len,
PCI_REGION_TYPE, flags, MAP_NOCACHE);
return dm_pci_bus_to_virt(udev, pci_bus_addr + offset, len, mask, flags,
MAP_NOCACHE);
}
static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)

2
drivers/spi/octeon_spi.c
View file

@ -568,7 +568,7 @@ static int octeon_spi_probe(struct udevice *dev)
pci_dev_t bdf = dm_pci_get_bdf(dev);
debug("SPI PCI device: %x\n", bdf);
priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
/* Add base offset */
priv->base += 0x1000;

3
drivers/usb/host/ehci-pci.c
View file

@ -36,7 +36,8 @@ static int ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr,
return ret;
hccr = (struct ehci_hccr *)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
hcor = (struct ehci_hcor *)((uintptr_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

2
drivers/usb/host/ohci-pci.c
View file

@ -18,7 +18,7 @@ static int ohci_pci_probe(struct udevice *dev)
{
struct ohci_regs *regs;
regs = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
regs = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM);
return ohci_register(dev, regs);
}

3
drivers/usb/host/xhci-pci.c
View file

@ -27,7 +27,8 @@ static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
u32 cmd;
hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_MEM);
PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
PCI_REGION_MEM);
if (!hccr) {
printf("xhci-pci init cannot map PCI mem bar\n");
return -EIO;

3
drivers/virtio/virtio_pci_legacy.c
View file

@ -319,7 +319,8 @@ static int virtio_pci_probe(struct udevice *udev)
uc_priv->device = subdevice;
uc_priv->vendor = subvendor;
priv->ioaddr = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_IO);
priv->ioaddr = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_TYPE, PCI_REGION_IO);
if (!priv->ioaddr)
return -ENXIO;
debug("(%s): virtio legacy device reg base %04lx\n",

3
include/pci.h
View file

@ -1352,11 +1352,12 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, size_t len,
* @bar: Bar register offset (PCI_BASE_ADDRESS_...)
* @offset: Offset from the base to map
* @len: Length to map
* @mask: Mask to match flags for the region type
* @flags: Flags for the region type (PCI_REGION_...)
* @return: pointer to the virtual address to use or 0 on error
*/
void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
unsigned long flags);
unsigned long mask, unsigned long flags);
/**
* dm_pci_find_next_capability() - find a capability starting from an offset

12
test/dm/pci.c
View file

@ -268,27 +268,27 @@ static int dm_test_pci_ea(struct unit_test_state *uts)
ut_asserteq(PCI_CAP_ID_EA_OFFSET, cap);
/* test swap case in BAR 1 */
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_0, 0, 0, 0);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0);
ut_assertnonnull(bar);
*(int *)bar = 2; /* swap upper/lower */
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, 0);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0);
ut_assertnonnull(bar);
strcpy(bar, "ea TEST");
unmap_sysmem(bar);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, 0);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0);
ut_assertnonnull(bar);
ut_asserteq_str("EA test", bar);
/* test magic values in BARs2, 4; BAR 3 is n/a */
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_2, 0, 0, 0);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE, 0);
ut_assertnonnull(bar);
ut_asserteq(PCI_EA_BAR2_MAGIC, *(u32 *)bar);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_3, 0, 0, 0);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_3, 0, 0, PCI_REGION_TYPE, 0);
ut_assertnull(bar);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_4, 0, 0, 0);
bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE, 0);
ut_assertnonnull(bar);
ut_asserteq(PCI_EA_BAR4_MAGIC, *(u32 *)bar);