mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
configs: rockchip: Enable ethernet driver on RK356x boards
Enable DWC_ETH_QOS_ROCKCHIP and related PHY driver on RK356x boards that have an enabled gmac node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
parent
01b8ed4754
commit
25f56459ae
11 changed files with 35 additions and 6 deletions
|
@ -46,6 +46,7 @@ CONFIG_CMD_REGULATOR=y
|
||||||
CONFIG_SPL_OF_CONTROL=y
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
CONFIG_OF_LIVE=y
|
CONFIG_OF_LIVE=y
|
||||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
CONFIG_SPL_REGMAP=y
|
CONFIG_SPL_REGMAP=y
|
||||||
CONFIG_SPL_SYSCON=y
|
CONFIG_SPL_SYSCON=y
|
||||||
CONFIG_SPL_CLK=y
|
CONFIG_SPL_CLK=y
|
||||||
|
@ -58,8 +59,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
CONFIG_MMC_SDHCI=y
|
CONFIG_MMC_SDHCI=y
|
||||||
CONFIG_MMC_SDHCI_SDMA=y
|
CONFIG_MMC_SDHCI_SDMA=y
|
||||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
CONFIG_ETH_DESIGNWARE=y
|
CONFIG_PHY_REALTEK=y
|
||||||
CONFIG_GMAC_ROCKCHIP=y
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_DM_PMIC=y
|
CONFIG_DM_PMIC=y
|
||||||
CONFIG_PMIC_RK8XX=y
|
CONFIG_PMIC_RK8XX=y
|
||||||
CONFIG_REGULATOR_RK8XX=y
|
CONFIG_REGULATOR_RK8XX=y
|
||||||
|
|
|
@ -61,6 +61,9 @@ CONFIG_MMC_SDHCI=y
|
||||||
CONFIG_MMC_SDHCI_SDMA=y
|
CONFIG_MMC_SDHCI_SDMA=y
|
||||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
# CONFIG_SPI_FLASH is not set
|
# CONFIG_SPI_FLASH is not set
|
||||||
|
CONFIG_PHY_REALTEK=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||||
CONFIG_SPL_PINCTRL=y
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
|
|
@ -65,6 +65,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
CONFIG_MMC_SDHCI=y
|
CONFIG_MMC_SDHCI=y
|
||||||
CONFIG_MMC_SDHCI_SDMA=y
|
CONFIG_MMC_SDHCI_SDMA=y
|
||||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
|
CONFIG_PHY_REALTEK=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_RTL8169=y
|
CONFIG_RTL8169=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
|
|
|
@ -82,6 +82,9 @@ CONFIG_SF_DEFAULT_BUS=4
|
||||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
CONFIG_SPI_FLASH_MACRONIX=y
|
CONFIG_SPI_FLASH_MACRONIX=y
|
||||||
CONFIG_SPI_FLASH_MTD=y
|
CONFIG_SPI_FLASH_MTD=y
|
||||||
|
CONFIG_PHY_REALTEK=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
|
|
@ -80,6 +80,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||||
CONFIG_SPI_FLASH_MACRONIX=y
|
CONFIG_SPI_FLASH_MACRONIX=y
|
||||||
CONFIG_SPI_FLASH_WINBOND=y
|
CONFIG_SPI_FLASH_WINBOND=y
|
||||||
|
CONFIG_PHY_MOTORCOMM=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
|
|
@ -78,6 +78,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||||
CONFIG_SPI_FLASH_MACRONIX=y
|
CONFIG_SPI_FLASH_MACRONIX=y
|
||||||
CONFIG_SPI_FLASH_WINBOND=y
|
CONFIG_SPI_FLASH_WINBOND=y
|
||||||
|
CONFIG_PHY_REALTEK=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
|
|
@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y
|
||||||
CONFIG_SPL_OF_CONTROL=y
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
CONFIG_OF_LIVE=y
|
CONFIG_OF_LIVE=y
|
||||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
CONFIG_SPL_REGMAP=y
|
CONFIG_SPL_REGMAP=y
|
||||||
CONFIG_SPL_SYSCON=y
|
CONFIG_SPL_SYSCON=y
|
||||||
CONFIG_SPL_CLK=y
|
CONFIG_SPL_CLK=y
|
||||||
|
@ -59,8 +60,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
CONFIG_MMC_SDHCI=y
|
CONFIG_MMC_SDHCI=y
|
||||||
CONFIG_MMC_SDHCI_SDMA=y
|
CONFIG_MMC_SDHCI_SDMA=y
|
||||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
CONFIG_ETH_DESIGNWARE=y
|
CONFIG_PHY_REALTEK=y
|
||||||
CONFIG_GMAC_ROCKCHIP=y
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||||
CONFIG_SPL_PINCTRL=y
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
|
|
@ -76,8 +76,9 @@ CONFIG_SF_DEFAULT_BUS=4
|
||||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
CONFIG_SPI_FLASH_MACRONIX=y
|
CONFIG_SPI_FLASH_MACRONIX=y
|
||||||
CONFIG_SPI_FLASH_XTX=y
|
CONFIG_SPI_FLASH_XTX=y
|
||||||
CONFIG_ETH_DESIGNWARE=y
|
CONFIG_PHY_REALTEK=y
|
||||||
CONFIG_GMAC_ROCKCHIP=y
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
|
|
@ -67,6 +67,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
CONFIG_MMC_SDHCI=y
|
CONFIG_MMC_SDHCI=y
|
||||||
CONFIG_MMC_SDHCI_SDMA=y
|
CONFIG_MMC_SDHCI_SDMA=y
|
||||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
|
CONFIG_PHY_MOTORCOMM=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
|
|
@ -67,6 +67,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
CONFIG_MMC_SDHCI=y
|
CONFIG_MMC_SDHCI=y
|
||||||
CONFIG_MMC_SDHCI_SDMA=y
|
CONFIG_MMC_SDHCI_SDMA=y
|
||||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
|
CONFIG_PHY_MOTORCOMM=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
|
|
@ -67,6 +67,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
CONFIG_MMC_SDHCI=y
|
CONFIG_MMC_SDHCI=y
|
||||||
CONFIG_MMC_SDHCI_SDMA=y
|
CONFIG_MMC_SDHCI_SDMA=y
|
||||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
|
CONFIG_PHY_MOTORCOMM=y
|
||||||
|
CONFIG_DWC_ETH_QOS=y
|
||||||
|
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||||
CONFIG_NVME_PCI=y
|
CONFIG_NVME_PCI=y
|
||||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
|
Loading…
Reference in a new issue