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ppc/85xx: Fix enabling of L2 cache

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We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-09-22 15:45:44 -05:00
parent cb0ff65c61
commit 25bacf7a2b
2 changed files with 4 additions and 3 deletions
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4
cpu/mpc85xx/cpu_init.c
View file

@ -336,8 +336,8 @@ int cpu_init_r(void)
u32 l2cfg0 = mfspr(SPRN_L2CFG0); u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */ /* invalidate the L2 cache */
mtspr(SPRN_L2CSR0, L2CSR0_L2FI); mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
; ;
/* enable the cache */ /* enable the cache */

3
cpu/mpc85xx/release.S
View file

@ -102,7 +102,8 @@ __secondary_start_page:
#ifdef CONFIG_BACKSIDE_L2_CACHE #ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */ /* Enable/invalidate the L2 cache */
msync msync
lis r3,L2CSR0_L2FI@h lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
mtspr SPRN_L2CSR0,r3 mtspr SPRN_L2CSR0,r3
1: 1:
mfspr r3,SPRN_L2CSR0 mfspr r3,SPRN_L2CSR0