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Remove legacy NAND and disk on chip references from boards.

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Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2009-07-16 19:08:04 -05:00
parent be33b046b5
commit 2419169f57
43 changed files with 0 additions and 1053 deletions
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4
board/delta/nand.c
View file

@ -23,7 +23,6 @@
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/pxa-regs.h>
@ -550,7 +549,4 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
#else
#error "U-Boot legacy NAND support not available for Monahans DFC."
#endif
#endif

50
board/esd/common/auto_update.c
View file

@ -27,9 +27,6 @@
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
#if defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
#endif
#include <fat.h>
#include <part.h>
@ -58,20 +55,6 @@ extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
/* references to names in cmd_nand.c */
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
#define NANDRW_JFFS2 0x02
#define NANDRW_JFFS2_SKIP 0x04
extern struct nand_chip nand_dev_desc[];
extern int nand_legacy_rw(struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf);
extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs,
size_t len, int clean);
#endif
extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
int au_check_cksum_valid(int i, long nbytes)
@ -158,9 +141,6 @@ int au_do_update(int i, long sz)
int off, rc;
uint nbytes;
int k;
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
int total;
#endif
hdr = (image_header_t *)LOAD_ADDR;
#if defined(CONFIG_FIT)
@ -240,15 +220,6 @@ int au_do_update(int i, long sz)
au_image[i].name);
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
flash_sect_erase (start, end);
} else {
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
printf ("Updating NAND FLASH with image %s\n",
au_image[i].name);
debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
rc = nand_legacy_erase (nand_dev_desc, start,
end - start + 1, 0);
debug ("nand_legacy_erase returned %x\n", rc);
#endif
}
udelay(10000);
@ -273,18 +244,7 @@ int au_do_update(int i, long sz)
rc = flash_write ((char *)addr, start,
(nbytes + 1) & ~1);
} else {
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
debug ("nand_legacy_rw(%p, %lx, %x)\n",
addr, start, nbytes);
rc = nand_legacy_rw (nand_dev_desc,
NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total,
(uchar *)addr);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n",
rc, total, nbytes);
#else
rc = -1;
#endif
}
if (rc != 0) {
printf ("Flashing failed due to error %d\n", rc);
@ -297,16 +257,6 @@ int au_do_update(int i, long sz)
if (au_image[i].type != AU_NAND) {
rc = crc32 (0, (uchar *)(start + off),
image_get_data_size (hdr));
} else {
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
rc = nand_legacy_rw (nand_dev_desc,
NANDRW_READ | NANDRW_JFFS2 |
NANDRW_JFFS2_SKIP,
start, nbytes, (size_t *)&total,
(uchar *)addr);
rc = crc32 (0, (uchar *)(addr + off),
image_get_data_size (hdr));
#endif
}
if (rc != image_get_dcrc (hdr)) {
printf ("Image %s Bad Data Checksum After COPY\n",

15
board/g2000/g2000.c
View file

@ -148,21 +148,6 @@ phys_size_t initdram (int board_type)
return ret;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CONFIG_SYS_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
#if 0 /* test-only !!! */
int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{

16
board/netphone/netphone.c
View file

@ -597,22 +597,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)

15
board/netta/netta.c
View file

@ -555,21 +555,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_init(void)

16
board/netta2/netta2.c
View file

@ -595,22 +595,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)

15
board/netvia/netvia.c
View file

@ -415,18 +415,3 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif

23
board/omap2420h4/omap2420h4.c
View file

@ -31,10 +31,6 @@
#include <asm/arch/mem.h>
#include <i2c.h>
#include <asm/mach-types.h>
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -846,22 +842,3 @@ void update_mux(u32 btype,u32 mtype)
}
}
}
#if defined(CONFIG_CMD_NAND)
void nand_init(void)
{
extern flash_info_t flash_info[];
nand_probe(CONFIG_SYS_NAND_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#ifdef CONFIG_SYS_JFFS2_MEM_NAND
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
#endif
}
#endif

11
board/samsung/smdk6400/smdk6400.c
View file

@ -107,17 +107,6 @@ ulong virt_to_phy_smdk6400(ulong addr)
}
#endif
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CONFIG_SYS_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
print_size(nand_dev_desc[0].totlen, "\n");
}
#endif
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */

5
board/sixnet/sixnet.c
View file

@ -33,11 +33,6 @@
# include <status_led.h>
#endif
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
#endif
DECLARE_GLOBAL_DATA_PTR;
#define ORMASK(size) ((-size) & OR_AM_MSK)

16
board/stxxtc/stxxtc.c
View file

@ -574,22 +574,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)

4
board/zylonite/nand.c
View file

@ -23,7 +23,6 @@
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#ifdef CONFIG_NEW_NAND_CODE
#include <nand.h>
#include <asm/arch/pxa-regs.h>
@ -554,7 +553,4 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
#else
#error "U-Boot legacy NAND support not available for Monahans DFC."
#endif
#endif

4
include/configs/BMW.h
View file

@ -81,13 +81,9 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
/* CONFIG_CMD_DOC required legacy NAND support */
#define CONFIG_NAND_LEGACY
#if 0
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */

8
include/configs/CATcenter.h
View file

@ -209,16 +209,8 @@
/* For CATcenter there is only NAND on the module */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define NAND_NO_RB
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */

10
include/configs/CPU86.h
View file

@ -145,15 +145,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
* Disk-On-Chip configuration
*/
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*-----------------------------------------------------------------------
* Miscellaneous configuration options
*/
@ -179,7 +170,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS

4
include/configs/CPU87.h
View file

@ -182,7 +182,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
@ -190,9 +189,6 @@
#define CONFIG_CMD_PCI
#endif
#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/

20
include/configs/G2000.h
View file

@ -196,32 +196,12 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CONFIG_SYS_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#endif
/*-----------------------------------------------------------------------

17
include/configs/GEN860T.h
View file

@ -244,10 +244,6 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG
#if !defined(CONFIG_SC)
#define CONFIG_CMD_DOC
#endif
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif
@ -279,9 +275,6 @@
#define CONFIG_FPGA_VIRTEX2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_NAND_LEGACY
/*
* Verbose help from command monitor.
*/
@ -737,16 +730,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Disk On Chip (millenium) configuration
*/
#if !defined(CONFIG_SC)
#define CONFIG_SYS_MAX_DOC_DEVICE 1
#undef CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
#undef CONFIG_SYS_DOC_PASSIVE_PROBE
#endif
/*
* FEC interrupt assignment
*/

10
include/configs/MIP405.h
View file

@ -84,12 +84,9 @@
#if !defined(CONFIG_MIP405T)
#define CONFIG_CMD_USB
#define CONFIG_CMD_DOC
#endif
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/**************************************************************
@ -383,13 +380,6 @@
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
/************************************************************
* Disk-On-Chip configuration
************************************************************/
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/************************************************************
* Keyboard support
************************************************************/

86
include/configs/NETPHONE.h
View file

@ -497,95 +497,9 @@
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
/****************************************************************/
/* NAND */
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
} while(0)
#if CONFIG_NETPHONE_VERSION == 1
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#elif CONFIG_NETPHONE_VERSION == 2
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#endif
#define WRITE_NAND_COMMAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND_ADDRESS(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/

99
include/configs/NETTA.h
View file

@ -616,105 +616,6 @@
#define ER_BASE 0xF1020000
#define DUMMY_BASE 0xF1FF0000
/****************************************************************/
/* NAND */
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* #define NAND_NO_RB */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
#define NAND_DISABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
} while(0)
#ifndef NAND_NO_RB
#define NAND_WAIT_READY(nand) \
do { \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
WATCHDOG_RESET(); \
} \
} while (0)
#else
#define NAND_WAIT_READY(nand) udelay(12)
#endif
#define WRITE_NAND_COMMAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND_ADDRESS(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_SIZE 0x00100000
#define CONFIG_JFFS2_PART_OFFSET 0x00200000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=netta-nand"
#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)"
*/
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP

86
include/configs/NETTA2.h
View file

@ -498,95 +498,9 @@
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
/****************************************************************/
/* NAND */
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
} while(0)
#if CONFIG_NETTA2_VERSION == 1
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#elif CONFIG_NETTA2_VERSION == 2
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#endif
#define WRITE_NAND_COMMAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND_ADDRESS(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/

74
include/configs/NETVIA.h
View file

@ -393,80 +393,6 @@
#endif
/*****************************************************************************/
#define CONFIG_NAND_LEGACY
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* NAND */
#define CONFIG_SYS_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_DISABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0040; \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0100; \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0080; \
} while(0)
#define NAND_WAIT_READY(nand) \
do { \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
; \
} while (0)
#define WRITE_NAND_COMMAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND_ADDRESS(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
#endif
/*****************************************************************************/

12
include/configs/PCIPPC2.h
View file

@ -75,7 +75,6 @@
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
@ -84,8 +83,6 @@
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/
@ -250,15 +247,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------
* Disk-On-Chip configuration
*/
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*-----------------------------------------------------------------------
RTC m48t59
*/

12
include/configs/PCIPPC6.h
View file

@ -75,7 +75,6 @@
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
@ -86,8 +85,6 @@
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/
@ -252,15 +249,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------
* Disk-On-Chip configuration
*/
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*-----------------------------------------------------------------------
RTC m48t59
*/

4
include/configs/PIP405.h
View file

@ -71,14 +71,10 @@
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_DOC
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/**************************************************************

19
include/configs/PM520.h
View file

@ -86,12 +86,6 @@
#define CONFIG_USB_STORAGE
#endif
#if !defined(CONFIG_BOOT_ROM)
/* DoC requires legacy NAND for now */
#define CONFIG_NAND_LEGACY
#endif
/*
* BOOTP options
*/
@ -117,10 +111,6 @@
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#if !defined(CONFIG_BOOT_ROM)
#define CONFIG_CMD_DOC
#endif
#if defined(CONFIG_MPC5200)
#define CONFIG_CMD_PCI
#endif
@ -186,15 +176,6 @@
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
/*
* Disk-On-Chip configuration
*/
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
#define CONFIG_SYS_DOC_BASE 0xE0000000
#define CONFIG_SYS_DOC_SIZE 0x00100000

14
include/configs/PM826.h
View file

@ -169,7 +169,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
@ -179,19 +178,6 @@
#define CONFIG_CMD_PCI
#endif
#define CONFIG_NAND_LEGACY
/*
* Disk-On-Chip configuration
*/
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*
* Miscellaneous configurable options
*/

13
include/configs/PM828.h
View file

@ -169,7 +169,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
@ -179,18 +178,6 @@
#define CONFIG_CMD_PCI
#endif
/*
* Disk-On-Chip configuration
*/
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*
* Miscellaneous configurable options
*/

26
include/configs/PPChameleonEVB.h
View file

@ -309,32 +309,6 @@
} \
} while(0)
#if 0
#define SECTORSIZE 512
#define NAND_NO_RB
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
#define NAND_WAIT_READY(nand) do { \
udelay(12); \
} while (0)
#else
/* use the R/B pin */
/* TBD */
#endif
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

9
include/configs/RBC823.h
View file

@ -114,7 +114,6 @@
#define CONFIG_CMD_CDP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
@ -329,14 +328,6 @@
#endif
/************************************************************
* Disk-On-Chip configuration
************************************************************/
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------

67
include/configs/SXNI855T.h
View file

@ -163,75 +163,8 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition */
#undef CONFIG_CMD_MTDPARTS
/*
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0x00780000
#define CONFIG_JFFS2_PART_OFFSET 0x00080000
*/
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_SIZE 0x00200000
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand"
#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
*/
/* NAND flash support */
#define CONFIG_NAND_LEGACY
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
/* DFBUSY is available on Port C, bit 12; 0 if busy */
#define NAND_WAIT_READY(nand) \
while (!(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x0008));
#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
#define WRITE_NAND(d, adr) \
do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */
#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */
#define CE_LO 0x04 /* 1 selects chip (CE low) */
#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
#define NAND_DISABLE_CE(nand) \
nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
#define NAND_ENABLE_CE(nand) \
nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
#define NAND_CTL_CLRALE(nandptr) \
nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
#define NAND_CTL_SETALE(nandptr) \
nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
#define NAND_CTL_CLRCLE(nandptr) \
nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
#define NAND_CTL_SETCLE(nandptr) \
nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
/*
* Miscellaneous configurable options
*/

2
include/configs/TQM85xx.h
View file

@ -351,8 +351,6 @@
/* NAND FLASH */
#ifdef CONFIG_NAND
#undef CONFIG_NAND_LEGACY
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */

38
include/configs/VCMA9.h
View file

@ -246,42 +246,4 @@
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
/*-----------------------------------------------------------------------
* NAND flash settings
*/
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_WAIT_READY(nand) NF_WaitRB()
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
#define WRITE_NAND(d, adr) NF_Write(d)
#define READ_NAND(adr) NF_Read()
/* the following functions are NOP's because S3C24X0 handles this in hardware */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_MTD_NAND_ECC_JFFS2 1
#endif
#endif /* __CONFIG_H */

30
include/configs/at91rm9200dk.h
View file

@ -117,38 +117,8 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
/* the following are NOP's in our implementation */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000

32
include/configs/csb637.h
View file

@ -121,38 +121,6 @@
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PING
#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
/* the following are NOP's in our implementation */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000

9
include/configs/delta.h
View file

@ -220,8 +220,6 @@
/*
* NAND Flash
*/
#undef CONFIG_NAND_LEGACY
#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
#undef CONFIG_SYS_NAND1_BASE
@ -255,13 +253,6 @@
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1

5
include/configs/m501sk.h
View file

@ -162,11 +162,6 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000

36
include/configs/omap2420h4.h
View file

@ -147,42 +147,6 @@
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
/*
* Board NAND Info.
*/
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
#define NAND_WAIT_READY(nand) udelay(10)
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP
#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS

23
include/configs/sbc2410x.h
View file

@ -201,29 +201,6 @@
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_S3C2410
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_WAIT_READY(nand) NF_WaitRB()
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
#define WRITE_NAND(d, adr) NF_Write(d)
#define READ_NAND(adr) NF_Read()
/* the following functions are NOP's because S3C24X0 handles this in hardware */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
#endif /* CONFIG_CMD_NAND */
#define CONFIG_SETUP_MEMORY_TAGS

82
include/configs/stxxtc.h
View file

@ -118,7 +118,6 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
@ -446,90 +445,9 @@
#define NAND_SIZE 0x00010000 /* 64K */
#define NAND_BASE 0xF1000000
/****************************************************************/
/* NAND */
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#undef NAND_NO_RB
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
#define NAND_DISABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
} while(0)
#ifndef NAND_NO_RB
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#else
#define NAND_WAIT_READY(nand) udelay(12)
#endif
#define WRITE_NAND_COMMAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND_ADDRESS(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/

4
include/configs/svm_sc8xx.h
View file

@ -147,12 +147,8 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_DATE
#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/

8
include/configs/zylonite.h
View file

@ -193,7 +193,6 @@
/*
* NAND Flash
*/
#define CONFIG_NEW_NAND_CODE
#define CONFIG_SYS_NAND0_BASE 0x0
#undef CONFIG_SYS_NAND1_BASE
@ -227,13 +226,6 @@
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1