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https://github.com/AsahiLinux/u-boot
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Add support for Eukrea CPU9260/CPU9G20 SBC
these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
This commit is contained in:
Tom Rix
parent
d8380c9d35
commit
23b80982a0
9 changed files with 900 additions and 1 deletions
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@ -528,6 +528,8 @@ Dirk Behme <dirk.behme@gmail.com>
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Eric Benard <eric@eukrea.com>
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cpuat91 ARM920T
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cpu9260 ARM926EJS (AT91SAM9260 SoC)
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cpu9G20 ARM926EJS (AT91SAM9G20 SoC)
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Rishi Bhattacharya <rishi@ti.com>
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2
MAKEALL
2
MAKEALL
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@ -624,6 +624,8 @@ LIST_at91=" \
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at91sam9rlek \
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cmc_pu2 \
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CPUAT91 \
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CPU9260 \
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CPU9G20 \
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csb637 \
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kb9202 \
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meesc \
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8
Makefile
8
Makefile
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@ -2827,6 +2827,14 @@ at91sam9rlek_config : unconfig
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fi;
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@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
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CPU9G20_128M_config \
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CPU9G20_config \
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CPU9260_128M_config \
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CPU9260_config : unconfig
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@mkdir -p $(obj)include
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@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
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@$(MKCONFIG) -a cpu9260 arm arm926ejs cpu9260 eukrea at91
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meesc_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91
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59
board/eukrea/cpu9260/Makefile
Normal file
59
board/eukrea/cpu9260/Makefile
Normal file
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@ -0,0 +1,59 @@
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian.pop@leadtechdesign.com
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# Lead Tech Design <www.leadtechdesign.com>
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# Ilko Iliev <www.ronetix.at>
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#
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# (C) Copyright 2009
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# Eric Benard <eric@eukrea.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += led.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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1
board/eukrea/cpu9260/config.mk
Normal file
1
board/eukrea/cpu9260/config.mk
Normal file
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@ -0,0 +1 @@
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TEXT_BASE = 0x21f00000
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220
board/eukrea/cpu9260/cpu9260.c
Normal file
220
board/eukrea/cpu9260/cpu9260.c
Normal file
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@ -0,0 +1,220 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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* Ilko Iliev <www.ronetix.at>
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*
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* (C) Copyright 2009
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* Eric Benard <eric@eukrea.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/sizes.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91sam9_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void cpu9260_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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#if defined(CONFIG_CPU9G20)
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) |
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AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 |
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AT91_SMC_TDF_(3));
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#elif defined(CONFIG_CPU9260)
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 |
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AT91_SMC_TDF_(2));
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#endif
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void cpu9260_macb_hw_init(void)
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{
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unsigned long rstc;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PA17) => PHY normal mode (not Test mode)
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* ERX0 (PA14) => PHY ADDR0
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* ERX1 (PA15) => PHY ADDR1
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* ERX2 (PA25) => PHY ADDR2
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* ERX3 (PA26) => PHY ADDR3
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* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0D << 8)) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
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;
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(rstc) |
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AT91_RSTC_URSTEN);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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at91_macb_hw_init();
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of the board */
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#if defined(CONFIG_CPU9G20)
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gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
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#elif defined(CONFIG_CPU9260)
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gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91_serial_hw_init();
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#ifdef CONFIG_CMD_NAND
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cpu9260_nand_hw_init();
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#endif
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#ifdef CONFIG_MACB
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cpu9260_macb_hw_init();
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#endif
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) !=
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PHYS_SDRAM_SIZE)
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return -1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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153
board/eukrea/cpu9260/led.c
Normal file
153
board/eukrea/cpu9260/led.c
Normal file
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@ -0,0 +1,153 @@
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/*
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* Copyright (c) 2009 Wind River Systems, Inc.
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* Tom Rix <Tom.Rix@windriver.com>
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* (C) Copyright 2009
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* Eric Benard <eric@eukrea.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <status_led.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
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STATUS_LED_OFF, STATUS_LED_OFF};
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void coloured_LED_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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at91_set_gpio_output(CONFIG_RED_LED, 1);
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at91_set_gpio_output(CONFIG_GREEN_LED, 1);
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at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
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at91_set_gpio_output(CONFIG_BLUE_LED, 1);
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at91_set_gpio_value(CONFIG_RED_LED, 1);
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at91_set_gpio_value(CONFIG_GREEN_LED, 1);
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at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
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at91_set_gpio_value(CONFIG_BLUE_LED, 1);
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}
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void red_LED_off(void)
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{
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at91_set_gpio_value(CONFIG_RED_LED, 1);
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saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
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}
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void green_LED_off(void)
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{
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at91_set_gpio_value(CONFIG_GREEN_LED, 1);
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saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
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}
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void yellow_LED_off(void)
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{
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at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
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saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
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}
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void blue_LED_off(void)
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{
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at91_set_gpio_value(CONFIG_BLUE_LED, 1);
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saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
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}
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void red_LED_on(void)
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{
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at91_set_gpio_value(CONFIG_RED_LED, 0);
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saved_state[STATUS_LED_RED] = STATUS_LED_ON;
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}
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void green_LED_on(void)
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{
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at91_set_gpio_value(CONFIG_GREEN_LED, 0);
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saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
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}
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void yellow_LED_on(void)
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{
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at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
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saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
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}
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void blue_LED_on(void)
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{
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at91_set_gpio_value(CONFIG_BLUE_LED, 0);
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saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
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}
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void __led_init(led_id_t mask, int state)
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{
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__led_set(mask, state);
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}
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|
||||
void __led_toggle(led_id_t mask)
|
||||
{
|
||||
if (STATUS_LED_BLUE == mask) {
|
||||
if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
|
||||
blue_LED_off();
|
||||
else
|
||||
blue_LED_on();
|
||||
} else if (STATUS_LED_RED == mask) {
|
||||
if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
|
||||
red_LED_off();
|
||||
else
|
||||
red_LED_on();
|
||||
} else if (STATUS_LED_GREEN == mask) {
|
||||
if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
|
||||
green_LED_off();
|
||||
else
|
||||
green_LED_on();
|
||||
} else if (STATUS_LED_YELLOW == mask) {
|
||||
if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
|
||||
yellow_LED_off();
|
||||
else
|
||||
yellow_LED_on();
|
||||
}
|
||||
}
|
||||
|
||||
void __led_set(led_id_t mask, int state)
|
||||
{
|
||||
if (STATUS_LED_BLUE == mask) {
|
||||
if (STATUS_LED_ON == state)
|
||||
blue_LED_on();
|
||||
else
|
||||
blue_LED_off();
|
||||
} else if (STATUS_LED_RED == mask) {
|
||||
if (STATUS_LED_ON == state)
|
||||
red_LED_on();
|
||||
else
|
||||
red_LED_off();
|
||||
} else if (STATUS_LED_GREEN == mask) {
|
||||
if (STATUS_LED_ON == state)
|
||||
green_LED_on();
|
||||
else
|
||||
green_LED_off();
|
||||
} else if (STATUS_LED_YELLOW == mask) {
|
||||
if (STATUS_LED_ON == state)
|
||||
yellow_LED_on();
|
||||
else
|
||||
yellow_LED_off();
|
||||
}
|
||||
}
|
||||
|
|
@ -194,7 +194,8 @@ SMRDATA:
|
|||
.word CONFIG_SYS_PIOD_PPUDR_VAL
|
||||
.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
|
||||
.word CONFIG_SYS_PIOD_PPUDR_VAL
|
||||
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261)
|
||||
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
|
||||
|| defined(CONFIG_AT91SAM9G20)
|
||||
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
|
||||
.word CONFIG_SYS_PIOC_PDR_VAL1
|
||||
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
|
||||
|
|
|
|||
453
include/configs/cpu9260.h
Normal file
453
include/configs/cpu9260.h
Normal file
|
|
@ -0,0 +1,453 @@
|
|||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
* Ilko Iliev <www.ronetix.at>
|
||||
*
|
||||
* (C) Copyright 2009
|
||||
* Eric Benard <eric@eukrea.com>
|
||||
*
|
||||
* Configuration settings for the Eukrea CPU9260 board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO 1
|
||||
|
||||
#define AT91_MAIN_CLOCK 18432000
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_ARM926EJS 1
|
||||
|
||||
#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
|
||||
#define CONFIG_CPU9260 1
|
||||
#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_CPU9G20 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_AT91SAM9G20 1
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define CONFIG_AT91SAM9260 1
|
||||
#else
|
||||
#error "Unknown board"
|
||||
#endif
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/* clocks */
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define MASTER_PLL_DIV 0x01
|
||||
#define MASTER_PLL_MUL 0x2B
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define MASTER_PLL_DIV 0x09
|
||||
#define MASTER_PLL_MUL 0x61
|
||||
#endif
|
||||
|
||||
/* CKGR_MOR - enable main osc. */
|
||||
#define CONFIG_SYS_MOR_VAL \
|
||||
(AT91_PMC_MOSCEN | \
|
||||
(255 << 8)) /* Main Oscillator Start-up Time */
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_SYS_PLLAR_VAL \
|
||||
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
|
||||
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define CONFIG_SYS_PLLAR_VAL \
|
||||
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
|
||||
AT91_PMC_OUT | \
|
||||
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_SYS_MCKR1_VAL \
|
||||
(AT91_PMC_CSS_PLLA | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91SAM9_PMC_MDIV_6 | \
|
||||
AT91_PMC_PDIV_2)
|
||||
#define CONFIG_SYS_MCKR2_VAL \
|
||||
CONFIG_SYS_MCKR1_VAL
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define CONFIG_SYS_MCKR1_VAL \
|
||||
(AT91_PMC_CSS_SLOW | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91SAM9_PMC_MDIV_2 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
#define CONFIG_SYS_MCKR2_VAL \
|
||||
(AT91_PMC_CSS_PLLA | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91SAM9_PMC_MDIV_2 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
#endif
|
||||
|
||||
/* define PDC[31:16] as DATA[31:16] */
|
||||
#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
|
||||
/* no pull-up for D[31:16] */
|
||||
#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
|
||||
|
||||
/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
|
||||
#define CONFIG_SYS_MATRIX_EBICSA_VAL \
|
||||
(AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
|
||||
AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
|
||||
|
||||
/* SDRAM */
|
||||
/* SDRAMC_MR Mode register */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
|
||||
/* SDRAMC_TR - Refresh Timer register */
|
||||
#define CONFIG_SYS_SDRC_TR_VAL1 0x287
|
||||
/* SDRAMC_CR - Configuration register*/
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_SYS_SDRC_CR_VAL_64MB \
|
||||
(AT91_SDRAMC_NC_9 | \
|
||||
AT91_SDRAMC_NR_13 | \
|
||||
AT91_SDRAMC_NB_4 | \
|
||||
AT91_SDRAMC_CAS_2 | \
|
||||
AT91_SDRAMC_DBW_32 | \
|
||||
(2 << 8) | /* Write Recovery Delay */ \
|
||||
(9 << 12) | /* Row Cycle Delay */ \
|
||||
(3 << 16) | /* Row Precharge Delay */ \
|
||||
(3 << 20) | /* Row to Column Delay */ \
|
||||
(6 << 24) | /* Active to Precharge Delay */ \
|
||||
(10 << 28)) /* Exit Self Refresh to Active Delay */
|
||||
|
||||
#define CONFIG_SYS_SDRC_CR_VAL_128MB \
|
||||
(AT91_SDRAMC_NC_10 | \
|
||||
AT91_SDRAMC_NR_13 | \
|
||||
AT91_SDRAMC_NB_4 | \
|
||||
AT91_SDRAMC_CAS_2 | \
|
||||
AT91_SDRAMC_DBW_32 | \
|
||||
(2 << 8) | /* Write Recovery Delay */ \
|
||||
(9 << 12) | /* Row Cycle Delay */ \
|
||||
(3 << 16) | /* Row Precharge Delay */ \
|
||||
(3 << 20) | /* Row to Column Delay */ \
|
||||
(6 << 24) | /* Active to Precharge Delay */ \
|
||||
(10 << 28)) /* Exit Self Refresh to Active Delay */
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define CONFIG_SYS_SDRC_CR_VAL_64MB \
|
||||
(AT91_SDRAMC_NC_9 | \
|
||||
AT91_SDRAMC_NR_13 | \
|
||||
AT91_SDRAMC_NB_4 | \
|
||||
AT91_SDRAMC_CAS_2 | \
|
||||
AT91_SDRAMC_DBW_32 | \
|
||||
(2 << 8) | /* Write Recovery Delay */ \
|
||||
(7 << 12) | /* Row Cycle Delay */ \
|
||||
(2 << 16) | /* Row Precharge Delay */ \
|
||||
(2 << 20) | /* Row to Column Delay */ \
|
||||
(5 << 24) | /* Active to Precharge Delay */ \
|
||||
(8 << 28)) /* Exit Self Refresh to Active Delay */
|
||||
|
||||
#define CONFIG_SYS_SDRC_CR_VAL_128MB \
|
||||
(AT91_SDRAMC_NC_10 | \
|
||||
AT91_SDRAMC_NR_13 | \
|
||||
AT91_SDRAMC_NB_4 | \
|
||||
AT91_SDRAMC_CAS_2 | \
|
||||
AT91_SDRAMC_DBW_32 | \
|
||||
(2 << 8) | /* Write Recovery Delay */ \
|
||||
(7 << 12) | /* Row Cycle Delay */ \
|
||||
(2 << 16) | /* Row Precharge Delay */ \
|
||||
(2 << 20) | /* Row to Column Delay */ \
|
||||
(5 << 24) | /* Active to Precharge Delay */ \
|
||||
(8 << 28)) /* Exit Self Refresh to Active Delay */
|
||||
#endif
|
||||
|
||||
/* Memory Device Register -> SDRAM */
|
||||
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
|
||||
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
|
||||
#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
|
||||
#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
|
||||
#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
|
||||
#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
|
||||
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
|
||||
|
||||
/* setup SMC0, CS0 (NOR Flash) - 16-bit */
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_SYS_SMC0_SETUP0_VAL \
|
||||
(AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
|
||||
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
|
||||
#define CONFIG_SYS_SMC0_PULSE0_VAL \
|
||||
(AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
|
||||
AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
|
||||
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
|
||||
(AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
|
||||
#define CONFIG_SYS_SMC0_MODE0_VAL \
|
||||
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
|
||||
AT91_SMC_DBW_16 | \
|
||||
AT91_SMC_TDFMODE | \
|
||||
AT91_SMC_TDF_(3))
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define CONFIG_SYS_SMC0_SETUP0_VAL \
|
||||
(AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
|
||||
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
|
||||
#define CONFIG_SYS_SMC0_PULSE0_VAL \
|
||||
(AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
|
||||
AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
|
||||
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
|
||||
(AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
|
||||
#define CONFIG_SYS_SMC0_MODE0_VAL \
|
||||
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
|
||||
AT91_SMC_DBW_16 | \
|
||||
AT91_SMC_TDFMODE | \
|
||||
AT91_SMC_TDF_(2))
|
||||
#endif
|
||||
|
||||
/* user reset enable */
|
||||
#define CONFIG_SYS_RSTC_RMR_VAL \
|
||||
(AT91_RSTC_KEY | \
|
||||
AT91_RSTC_PROCRST | \
|
||||
AT91_RSTC_RSTTYP_WAKEUP | \
|
||||
AT91_RSTC_RSTTYP_WATCHDOG)
|
||||
|
||||
/* Disable Watchdog */
|
||||
#define CONFIG_SYS_WDTC_WDMR_VAL \
|
||||
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
|
||||
AT91_WDT_WDV | \
|
||||
AT91_WDT_WDDIS | \
|
||||
AT91_WDT_WDD)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
#undef CONFIG_USART2
|
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1
|
||||
#define CONFIG_BOOTP_BOOTPATH 1
|
||||
#define CONFIG_BOOTP_GATEWAY 1
|
||||
#define CONFIG_BOOTP_HOSTNAME 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_CMD_PING 1
|
||||
#define CONFIG_CMD_DHCP 1
|
||||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_CMD_USB 1
|
||||
#define CONFIG_CMD_FAT 1
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
|
||||
#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
|
||||
#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
|
||||
#else
|
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
|
||||
#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
|
||||
#endif
|
||||
|
||||
/* NAND flash */
|
||||
#define CONFIG_NAND_ATMEL 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_DBW_8 1
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
|
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
|
||||
/* NOR flash */
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define PHYS_FLASH_1 0x10000000
|
||||
#define PHYS_FLASH_2 0x12000000
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST \
|
||||
{ PHYS_FLASH_1, PHYS_FLASH_2 }
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO 1
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1
|
||||
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_RMII 1
|
||||
#define CONFIG_RESET_PHY_R 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_MACB_SEARCH_PHY 1
|
||||
|
||||
/* LEDS */
|
||||
/* Status LED */
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||
#define CONFIG_BOARD_SPECIFIC_LED 1
|
||||
#define STATUS_LED_RED 0
|
||||
#define STATUS_LED_GREEN 1
|
||||
#define STATUS_LED_YELLOW 2
|
||||
#define STATUS_LED_BLUE 3
|
||||
/* Red */
|
||||
#define STATUS_LED_BIT STATUS_LED_RED
|
||||
#define STATUS_LED_STATE STATUS_LED_OFF
|
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
||||
/* Green */
|
||||
#define STATUS_LED_BIT1 STATUS_LED_GREEN
|
||||
#define STATUS_LED_STATE1 STATUS_LED_OFF
|
||||
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
|
||||
/* Yellow */
|
||||
#define STATUS_LED_BIT2 STATUS_LED_YELLOW
|
||||
#define STATUS_LED_STATE2 STATUS_LED_OFF
|
||||
#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
|
||||
/* Blue */
|
||||
#define STATUS_LED_BIT3 STATUS_LED_BLUE
|
||||
#define STATUS_LED_STATE3 STATUS_LED_ON
|
||||
#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
|
||||
/* Optional value */
|
||||
#define STATUS_LED_BOOT STATUS_LED_BIT
|
||||
|
||||
#define CONFIG_RED_LED AT91_PIN_PC11
|
||||
#define CONFIG_GREEN_LED AT91_PIN_PC12
|
||||
#define CONFIG_YELLOW_LED AT91_PIN_PC7
|
||||
#define CONFIG_BLUE_LED AT91_PIN_PC9
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_ATMEL 1
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x21000000
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END 0x21e00000
|
||||
|
||||
#undef CONFIG_SYS_USE_NANDFLASH
|
||||
#define CONFIG_SYS_USE_FLASH 1
|
||||
|
||||
#if defined(CONFIG_SYS_USE_FLASH)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x40000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flashboot"
|
||||
|
||||
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
|
||||
#define MTDPARTS_DEFAULT \
|
||||
"mtdparts=physmap-flash.0:" \
|
||||
"256k(u-boot)ro," \
|
||||
"128k(u-boot-env)ro," \
|
||||
"1792k(kernel)," \
|
||||
"-(rootfs);" \
|
||||
"atmel_nand:-(nand)"
|
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
|
||||
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_SYS_BASEDIR "cpu9G20"
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define CONFIG_SYS_BASEDIR "cpu9260"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"partition=nand0,0\0" \
|
||||
"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
|
||||
"ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
|
||||
"run ramargs;bootm 22000000\0" \
|
||||
"flashboot=run ramargs;bootm 0x10060000\0" \
|
||||
"basedir=" CONFIG_SYS_BASEDIR "\0" \
|
||||
"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
|
||||
"off 0x10000000 0x1003ffff;erase 0x10000000 " \
|
||||
"0x1003ffff;cp.b 0x24000000 0x10000000 " \
|
||||
"$(filesize)\0" \
|
||||
"updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
|
||||
" 0x10060000 0x1021ffff;erase 0x10060000 " \
|
||||
"0x1021ffff;cp.b 0x24000000 0x10060000 " \
|
||||
"$(filesize)\0" \
|
||||
"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
|
||||
"protect off 0x10220000 0x13ffffff;erase " \
|
||||
"0x10220000 0x13ffffff;cp.b 0x24000000 " \
|
||||
"0x10220000 $(filesize)\0" \
|
||||
""
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#if defined(CONFIG_CPU9G20)
|
||||
#define CONFIG_SYS_PROMPT "CPU9G20=> "
|
||||
#elif defined(CONFIG_CPU9260)
|
||||
#define CONFIG_SYS_PROMPT "CPU9260=> "
|
||||
#endif
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_SILENT_CONSOLE 1
|
||||
#define CONFIG_NETCONSOLE 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN \
|
||||
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
|
||||
#define CONFIG_STACKSIZE (32 * 1024)
|
||||
|
||||
#if defined(CONFIG_USE_IRQ)
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue