mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
ARM: dts: stm32: Synchronize DT with kernel one
This patch synchronizes U-boot DT with kernel one This is based on https://patchwork.kernel.org/cover/10797115/ This patch adds initial support of STM32MP157 discovery boards: - Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1). This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Several connections are available on this boards: 4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ... - Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2). This board is a "super-set" of stm32mp157a-dk1. A display panel (otm8009a) and Murata wifi/BT combo is added. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard
Patrick Delaunay
parent
31e45a1a9e
commit
2366160eb2
12 changed files with 1108 additions and 72 deletions
|
|
@ -684,6 +684,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
|
|||
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_STM32MP1) += \
|
||||
stm32mp157a-dk1.dtb \
|
||||
stm32mp157c-dk2.dtb \
|
||||
stm32mp157c-ed1.dtb \
|
||||
stm32mp157c-ev1.dtb
|
||||
|
||||
|
|
|
|||
120
arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
Normal file
120
arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* STM32MP157C DK1/DK2 BOARD configuration
|
||||
* 1x DDR3L 4Gb, 16-bit, 533MHz.
|
||||
* Reference used NT5CC256M16DP-DI from NANYA
|
||||
*
|
||||
* DDR type / Platform DDR3/3L
|
||||
* freq 533MHz
|
||||
* width 16
|
||||
* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
|
||||
* DDR density 4
|
||||
* timing mode optimized
|
||||
* Scheduling/QoS options : type = 2
|
||||
* address mapping : RBC
|
||||
* Tc > + 85C : N
|
||||
*/
|
||||
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43"
|
||||
#define DDR_MEM_SPEED 533
|
||||
#define DDR_MEM_SIZE 0x20000000
|
||||
|
||||
#define DDR_MSTR 0x00041401
|
||||
#define DDR_MRCTRL0 0x00000010
|
||||
#define DDR_MRCTRL1 0x00000000
|
||||
#define DDR_DERATEEN 0x00000000
|
||||
#define DDR_DERATEINT 0x00800000
|
||||
#define DDR_PWRCTL 0x00000000
|
||||
#define DDR_PWRTMG 0x00400010
|
||||
#define DDR_HWLPCTL 0x00000000
|
||||
#define DDR_RFSHCTL0 0x00210000
|
||||
#define DDR_RFSHCTL3 0x00000000
|
||||
#define DDR_RFSHTMG 0x0081008B
|
||||
#define DDR_CRCPARCTL0 0x00000000
|
||||
#define DDR_DRAMTMG0 0x121B2414
|
||||
#define DDR_DRAMTMG1 0x000A041C
|
||||
#define DDR_DRAMTMG2 0x0608090F
|
||||
#define DDR_DRAMTMG3 0x0050400C
|
||||
#define DDR_DRAMTMG4 0x08040608
|
||||
#define DDR_DRAMTMG5 0x06060403
|
||||
#define DDR_DRAMTMG6 0x02020002
|
||||
#define DDR_DRAMTMG7 0x00000202
|
||||
#define DDR_DRAMTMG8 0x00001005
|
||||
#define DDR_DRAMTMG14 0x000000A0
|
||||
#define DDR_ZQCTL0 0xC2000040
|
||||
#define DDR_DFITMG0 0x02060105
|
||||
#define DDR_DFITMG1 0x00000202
|
||||
#define DDR_DFILPCFG0 0x07000000
|
||||
#define DDR_DFIUPD0 0xC0400003
|
||||
#define DDR_DFIUPD1 0x00000000
|
||||
#define DDR_DFIUPD2 0x00000000
|
||||
#define DDR_DFIPHYMSTR 0x00000000
|
||||
#define DDR_ADDRMAP1 0x00070707
|
||||
#define DDR_ADDRMAP2 0x00000000
|
||||
#define DDR_ADDRMAP3 0x1F000000
|
||||
#define DDR_ADDRMAP4 0x00001F1F
|
||||
#define DDR_ADDRMAP5 0x06060606
|
||||
#define DDR_ADDRMAP6 0x0F060606
|
||||
#define DDR_ADDRMAP9 0x00000000
|
||||
#define DDR_ADDRMAP10 0x00000000
|
||||
#define DDR_ADDRMAP11 0x00000000
|
||||
#define DDR_ODTCFG 0x06000600
|
||||
#define DDR_ODTMAP 0x00000001
|
||||
#define DDR_SCHED 0x00000C01
|
||||
#define DDR_SCHED1 0x00000000
|
||||
#define DDR_PERFHPR1 0x01000001
|
||||
#define DDR_PERFLPR1 0x08000200
|
||||
#define DDR_PERFWR1 0x08000400
|
||||
#define DDR_DBG0 0x00000000
|
||||
#define DDR_DBG1 0x00000000
|
||||
#define DDR_DBGCMD 0x00000000
|
||||
#define DDR_POISONCFG 0x00000000
|
||||
#define DDR_PCCFG 0x00000010
|
||||
#define DDR_PCFGR_0 0x00010000
|
||||
#define DDR_PCFGW_0 0x00000000
|
||||
#define DDR_PCFGQOS0_0 0x02100C03
|
||||
#define DDR_PCFGQOS1_0 0x00800100
|
||||
#define DDR_PCFGWQOS0_0 0x01100C03
|
||||
#define DDR_PCFGWQOS1_0 0x01000200
|
||||
#define DDR_PCFGR_1 0x00010000
|
||||
#define DDR_PCFGW_1 0x00000000
|
||||
#define DDR_PCFGQOS0_1 0x02100C03
|
||||
#define DDR_PCFGQOS1_1 0x00800040
|
||||
#define DDR_PCFGWQOS0_1 0x01100C03
|
||||
#define DDR_PCFGWQOS1_1 0x01000200
|
||||
#define DDR_PGCR 0x01442E02
|
||||
#define DDR_PTR0 0x0022AA5B
|
||||
#define DDR_PTR1 0x04841104
|
||||
#define DDR_PTR2 0x042DA068
|
||||
#define DDR_ACIOCR 0x10400812
|
||||
#define DDR_DXCCR 0x00000C40
|
||||
#define DDR_DSGCR 0xF200001F
|
||||
#define DDR_DCR 0x0000000B
|
||||
#define DDR_DTPR0 0x38D488D0
|
||||
#define DDR_DTPR1 0x098B00D8
|
||||
#define DDR_DTPR2 0x10023600
|
||||
#define DDR_MR0 0x00000840
|
||||
#define DDR_MR1 0x00000000
|
||||
#define DDR_MR2 0x00000208
|
||||
#define DDR_MR3 0x00000000
|
||||
#define DDR_ODTCR 0x00010000
|
||||
#define DDR_ZQ0CR1 0x00000038
|
||||
#define DDR_DX0GCR 0x0000CE81
|
||||
#define DDR_DX0DLLCR 0x40000000
|
||||
#define DDR_DX0DQTR 0xFFFFFFFF
|
||||
#define DDR_DX0DQSTR 0x3DB02000
|
||||
#define DDR_DX1GCR 0x0000CE81
|
||||
#define DDR_DX1DLLCR 0x40000000
|
||||
#define DDR_DX1DQTR 0xFFFFFFFF
|
||||
#define DDR_DX1DQSTR 0x3DB02000
|
||||
#define DDR_DX2GCR 0x0000CE81
|
||||
#define DDR_DX2DLLCR 0x40000000
|
||||
#define DDR_DX2DQTR 0xFFFFFFFF
|
||||
#define DDR_DX2DQSTR 0x3DB02000
|
||||
#define DDR_DX3GCR 0x0000CE81
|
||||
#define DDR_DX3DLLCR 0x40000000
|
||||
#define DDR_DX3DQTR 0xFFFFFFFF
|
||||
#define DDR_DX3DQSTR 0x3DB02000
|
||||
|
||||
#include "stm32mp15-ddr.dtsi"
|
||||
|
|
@ -157,6 +157,52 @@
|
|||
};
|
||||
};
|
||||
|
||||
ethernet0_rgmii_pins_a: rgmii-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
|
||||
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
|
||||
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
|
||||
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
|
||||
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
|
||||
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
|
||||
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
|
||||
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
|
||||
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
||||
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
|
||||
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
|
||||
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
|
||||
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
|
||||
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
||||
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
|
||||
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
|
||||
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
|
||||
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
|
||||
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
||||
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
|
||||
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
|
||||
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
||||
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
|
||||
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
|
||||
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
|
||||
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
||||
|
|
@ -187,6 +233,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
m_can1_pins_a: m-can1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2_pins_a: pwm2-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
|
||||
|
|
@ -360,6 +419,21 @@
|
|||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1_pins_a: spi1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
|
||||
<STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
178
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
Normal file
178
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright : STMicroelectronics 2018
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp157-u-boot.dtsi"
|
||||
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &sdmmc1;
|
||||
};
|
||||
config {
|
||||
u-boot,boot-led = "heartbeat";
|
||||
u-boot,error-led = "error";
|
||||
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
|
||||
};
|
||||
led {
|
||||
red {
|
||||
label = "error";
|
||||
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
blue {
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
st,digbypass;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&i2c4_pins_a {
|
||||
u-boot,dm-pre-reloc;
|
||||
pins {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&pmic {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&rcc {
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_PLL12_HSE
|
||||
CLK_PLL3_HSE
|
||||
CLK_PLL4_HSE
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
1 /*MPU*/
|
||||
0 /*AXI*/
|
||||
0 /*MCU*/
|
||||
1 /*APB1*/
|
||||
1 /*APB2*/
|
||||
1 /*APB3*/
|
||||
1 /*APB4*/
|
||||
2 /*APB5*/
|
||||
23 /*RTC*/
|
||||
0 /*MCO1*/
|
||||
0 /*MCO2*/
|
||||
>;
|
||||
|
||||
st,pkcs = <
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_DISABLED
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4Q
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_LSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
||||
pll1: st,pll@0 {
|
||||
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
||||
frac = < 0x800 >;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
||||
frac = < 0x1400 >;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
||||
pll3: st,pll@2 {
|
||||
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
||||
frac = < 0x1a04 >;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
||||
pll4: st,pll@3 {
|
||||
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdmmc1_b4_pins_a {
|
||||
u-boot,dm-spl;
|
||||
pins {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart4_pins_a {
|
||||
u-boot,dm-pre-reloc;
|
||||
pins1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
usb1600;
|
||||
hnp-srp-disable;
|
||||
};
|
||||
|
||||
&v3v3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
262
arch/arm/dts/stm32mp157a-dk1.dts
Normal file
262
arch/arm/dts/stm32mp157a-dk1.dts
Normal file
|
|
@ -0,0 +1,262 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
|
||||
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ðernet0;
|
||||
serial0 = &uart4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
led {
|
||||
compatible = "gpio-leds";
|
||||
blue {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
||||
pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
pmic: stpmic@33 {
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
st,main-control-register = <0x04>;
|
||||
st,vin-control-register = <0xc0>;
|
||||
st,usb-control-register = <0x20>;
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr: buck2 {
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd: buck3 {
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
v1v8_audio: ldo1 {
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO1 0>;
|
||||
};
|
||||
|
||||
v3v3_hdmi: ldo2 {
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO2 0>;
|
||||
};
|
||||
|
||||
vtt_ddr: ldo3 {
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
interrupts = <IT_CURLIM_LDO4 0>;
|
||||
};
|
||||
|
||||
vdda: ldo5 {
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
interrupts = <IT_CURLIM_LDO5 0>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi: ldo6 {
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO6 0>;
|
||||
|
||||
};
|
||||
|
||||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
interrupts = <IT_OCP_BOOST 0>;
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
interrupts = <IT_OCP_OTG 0>;
|
||||
regulator-active-discharge;
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
interrupts = <IT_OCP_SWOUT 0>;
|
||||
regulator-active-discharge;
|
||||
};
|
||||
};
|
||||
|
||||
onkey {
|
||||
compatible = "st,stpmic1-onkey";
|
||||
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
|
||||
interrupt-names = "onkey-falling", "onkey-rising";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "st,stpmic1-wdt";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwr {
|
||||
pwr-supply = <&vdd>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
phy-names = "usb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
vdd3v3-supply = <&vdd_usb>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vrefbuf {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vdda-supply = <&vdd>;
|
||||
status = "okay";
|
||||
};
|
||||
6
arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
Normal file
6
arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright : STMicroelectronics 2018
|
||||
*/
|
||||
|
||||
#include "stm32mp157a-dk1-u-boot.dtsi"
|
||||
67
arch/arm/dts/stm32mp157c-dk2.dts
Normal file
67
arch/arm/dts/stm32mp157c-dk2.dts
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157a-dk1.dts"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
|
||||
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
phy-dsi-supply = <®18>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <<dc_ep1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "orisetech,otm8009a";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ltdc_ep1_out: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -9,9 +9,9 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &sdmmc1;
|
||||
mmc1 = &sdmmc2;
|
||||
i2c3 = &i2c4;
|
||||
};
|
||||
|
||||
config {
|
||||
|
|
@ -48,14 +48,8 @@
|
|||
st,digbypass;
|
||||
};
|
||||
|
||||
&uart4_pins_a {
|
||||
&i2c4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
pins1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4_pins_a {
|
||||
|
|
@ -65,14 +59,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pmic {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -170,8 +156,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* SPL part **************************************/
|
||||
/* MMC1 boot */
|
||||
&sdmmc1_b4_pins_a {
|
||||
u-boot,dm-spl;
|
||||
pins {
|
||||
|
|
@ -190,7 +174,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
/* MMC2 boot */
|
||||
&sdmmc2_b4_pins_a {
|
||||
u-boot,dm-spl;
|
||||
pins {
|
||||
|
|
@ -208,3 +191,17 @@
|
|||
&sdmmc2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart4_pins_a {
|
||||
u-boot,dm-pre-reloc;
|
||||
pins1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,13 +15,17 @@
|
|||
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial3:115200n8";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
reg = <0xC0000000 0x40000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
|
||||
sd_switch: regulator-sd_switch {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "sd_switch";
|
||||
|
|
@ -36,17 +40,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
&hwspinlock {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timers6 {
|
||||
status = "okay";
|
||||
timer@5 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
|
|
@ -321,10 +318,27 @@
|
|||
};
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hwlocks = <&hwspinlock 0>;
|
||||
};
|
||||
|
||||
&pwr {
|
||||
pwr-supply = <&vdd>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
broken-cd;
|
||||
|
|
@ -355,6 +369,13 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&timers6 {
|
||||
status = "okay";
|
||||
timer@5 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
|
|
@ -365,14 +386,6 @@
|
|||
usb33d-supply = <&usb33>;
|
||||
};
|
||||
|
||||
&hwspinlock {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hwlocks = <&hwspinlock 0>;
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
vdda1v1-supply = <®11>;
|
||||
|
|
|
|||
|
|
@ -7,29 +7,21 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
spi0 = &qspi;
|
||||
i2c1 = &i2c2;
|
||||
i2c4 = &i2c5;
|
||||
spi0 = &qspi;
|
||||
};
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
compatible = "spi-flash";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&flash1 {
|
||||
compatible = "spi-flash";
|
||||
};
|
||||
|
||||
&v3v3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
g-tx-fifo-size = <576>;
|
||||
};
|
||||
|
||||
/* SPL part **************************************/
|
||||
&qspi {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -61,7 +53,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
u-boot,dm-spl;
|
||||
&usbotg_hs {
|
||||
g-tx-fifo-size = <576>;
|
||||
};
|
||||
|
||||
&v3v3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,6 +11,21 @@
|
|||
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
|
||||
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
panel_backlight: panel-backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
|
||||
default-on;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cec {
|
||||
|
|
@ -19,6 +34,64 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <<dc_ep0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out: endpoint {
|
||||
remote-endpoint = <&dsi_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel-dsi@0 {
|
||||
compatible = "raydium,rm68200";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&panel_backlight>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
dsi_panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
||||
pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
|
|
@ -35,6 +108,26 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ltdc_ep0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&m_can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&m_can1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
||||
|
|
@ -60,6 +153,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers2 {
|
||||
status = "disabled";
|
||||
pwm {
|
||||
|
|
@ -106,6 +205,7 @@
|
|||
&usbotg_hs {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
dr_mode = "peripheral";
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -106,26 +106,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
pm_domain {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32mp157c-pd";
|
||||
|
||||
pd_core_ret: core-ret-power-domain@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
label = "CORE-RETENTION";
|
||||
|
||||
pd_core: core-power-domain@2 {
|
||||
reg = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
label = "CORE";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -339,6 +319,34 @@
|
|||
};
|
||||
};
|
||||
|
||||
spi2: spi@4000b000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x4000b000 0x400>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI2_K>;
|
||||
resets = <&rcc SPI2_R>;
|
||||
dmas = <&dmamux1 39 0x400 0x05>,
|
||||
<&dmamux1 40 0x400 0x05>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@4000c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x4000c000 0x400>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI3_K>;
|
||||
resets = <&rcc SPI3_R>;
|
||||
dmas = <&dmamux1 61 0x400 0x05>,
|
||||
<&dmamux1 62 0x400 0x05>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@4000e000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000e000 0x400>;
|
||||
|
|
@ -522,6 +530,34 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@44004000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x44004000 0x400>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI1_K>;
|
||||
resets = <&rcc SPI1_R>;
|
||||
dmas = <&dmamux1 37 0x400 0x05>,
|
||||
<&dmamux1 38 0x400 0x05>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@44005000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x44005000 0x400>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI4_K>;
|
||||
resets = <&rcc SPI4_R>;
|
||||
dmas = <&dmamux1 83 0x400 0x05>,
|
||||
<&dmamux1 84 0x400 0x05>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers15: timer@44006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -584,6 +620,116 @@
|
|||
};
|
||||
};
|
||||
|
||||
spi5: spi@44009000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x44009000 0x400>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI5_K>;
|
||||
resets = <&rcc SPI5_R>;
|
||||
dmas = <&dmamux1 85 0x400 0x05>,
|
||||
<&dmamux1 86 0x400 0x05>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dfsdm: dfsdm@4400d000 {
|
||||
compatible = "st,stm32mp1-dfsdm";
|
||||
reg = <0x4400d000 0x800>;
|
||||
clocks = <&rcc DFSDM_K>;
|
||||
clock-names = "dfsdm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
dfsdm0: filter@0 {
|
||||
compatible = "st,stm32-dfsdm-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmamux1 101 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dfsdm1: filter@1 {
|
||||
compatible = "st,stm32-dfsdm-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <1>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmamux1 102 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dfsdm2: filter@2 {
|
||||
compatible = "st,stm32-dfsdm-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <2>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmamux1 103 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dfsdm3: filter@3 {
|
||||
compatible = "st,stm32-dfsdm-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <3>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmamux1 104 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dfsdm4: filter@4 {
|
||||
compatible = "st,stm32-dfsdm-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <4>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmamux1 91 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dfsdm5: filter@5 {
|
||||
compatible = "st,stm32-dfsdm-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <5>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmamux1 92 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
m_can1: can@4400e000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can2: can@4400f000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma1: dma@48000000 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x48000000 0x400>;
|
||||
|
|
@ -647,6 +793,8 @@
|
|||
reg = <0x0>;
|
||||
interrupt-parent = <&adc>;
|
||||
interrupts = <0>;
|
||||
dmas = <&dmamux1 9 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -656,6 +804,8 @@
|
|||
reg = <0x100>;
|
||||
interrupt-parent = <&adc>;
|
||||
interrupts = <1>;
|
||||
dmas = <&dmamux1 10 0x400 0x01>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -675,7 +825,7 @@
|
|||
};
|
||||
|
||||
usbotg_hs: usb-otg@49000000 {
|
||||
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x49000000 0x10000>;
|
||||
clocks = <&rcc USBO_K>;
|
||||
clock-names = "otg";
|
||||
|
|
@ -686,7 +836,6 @@
|
|||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
||||
dr_mode = "otg";
|
||||
power-domains = <&pd_core>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -753,7 +902,7 @@
|
|||
reg = <0x5000d000 0x400>;
|
||||
};
|
||||
|
||||
syscfg: system-config@50020000 {
|
||||
syscfg: syscon@50020000 {
|
||||
compatible = "st,stm32mp157-syscfg", "syscon";
|
||||
reg = <0x50020000 0x400>;
|
||||
};
|
||||
|
|
@ -853,6 +1002,18 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hash1: hash@54002000 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc HASH1>;
|
||||
resets = <&rcc HASH1_R>;
|
||||
dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
|
||||
dma-names = "in";
|
||||
dma-maxburst = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rng1: rng@54003000 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x54003000 0x400>;
|
||||
|
|
@ -871,7 +1032,7 @@
|
|||
dma-requests = <48>;
|
||||
};
|
||||
|
||||
qspi: qspi@58003000 {
|
||||
qspi: spi@58003000 {
|
||||
compatible = "st,stm32f469-qspi";
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
||||
reg-names = "qspi", "qspi_mm";
|
||||
|
|
@ -915,6 +1076,36 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
stmmac_axi_config_0: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <0x7>;
|
||||
snps,rd_osr_lmt = <0x7>;
|
||||
snps,blen = <0 0 0 0 16 8 4>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@5800a000 {
|
||||
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
|
||||
reg = <0x5800a000 0x2000>;
|
||||
reg-names = "stmmaceth";
|
||||
interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clock-names = "stmmaceth",
|
||||
"mac-clk-tx",
|
||||
"mac-clk-rx",
|
||||
"ethstp",
|
||||
"syscfg-clk";
|
||||
clocks = <&rcc ETHMAC>,
|
||||
<&rcc ETHTX>,
|
||||
<&rcc ETHRX>,
|
||||
<&rcc ETHSTP>,
|
||||
<&rcc SYSCFG>;
|
||||
st,syscon = <&syscfg 0x4>;
|
||||
snps,mixed-burst;
|
||||
snps,pbl = <2>;
|
||||
snps,axi-config = <&stmmac_axi_config_0>;
|
||||
snps,tso;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh_ohci: usbh-ohci@5800c000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x5800c000 0x1000>;
|
||||
|
|
@ -955,6 +1146,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
iwdg2: watchdog@5a002000 {
|
||||
compatible = "st,stm32mp1-iwdg";
|
||||
reg = <0x5a002000 0x400>;
|
||||
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
||||
clock-names = "pclk", "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphyc: usbphyc@5a006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -983,6 +1182,20 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi6: spi@5c001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x5c001000 0x400>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI6_K>;
|
||||
resets = <&rcc SPI6_R>;
|
||||
dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
|
||||
<&mdma1 35 0x0 0x40002 0x0 0x0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@5c002000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x5c002000 0x400>;
|
||||
|
|
@ -996,6 +1209,15 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@5c004000 {
|
||||
compatible = "st,stm32mp1-rtc";
|
||||
reg = <0x5c004000 0x400>;
|
||||
clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
||||
clock-names = "pclk", "rtc_ck";
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsec: nvmem@5c005000 {
|
||||
compatible = "st,stm32mp15-bsec";
|
||||
reg = <0x5c005000 0x400>;
|
||||
|
|
|
|||
Loading…
Reference in a new issue