mirror of
https://github.com/AsahiLinux/u-boot
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i.mx: add the initial support for freescale i.MX6Q processor
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor. Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc:Stefano Babic <sbabic@denx.de>
This commit is contained in:
Jason Liu
Albert ARIBAUD
parent
18936ee2ad
commit
23608e23fd
12 changed files with 3628 additions and 0 deletions
48
arch/arm/cpu/armv7/mx6/Makefile
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48
arch/arm/cpu/armv7/mx6/Makefile
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@ -0,0 +1,48 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2011 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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COBJS = soc.o clock.o iomux-v3.o
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SOBJS = lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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366
arch/arm/cpu/armv7/mx6/clock.c
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366
arch/arm/cpu/armv7/mx6/clock.c
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@ -0,0 +1,366 @@
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/*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/ccm_regs.h>
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#include <asm/arch/clock.h>
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enum pll_clocks {
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PLL_SYS, /* System PLL */
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PLL_BUS, /* System Bus PLL*/
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PLL_USBOTG, /* OTG USB PLL */
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PLL_ENET, /* ENET PLL */
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};
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struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
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static u32 decode_pll(enum pll_clocks pll, u32 infreq)
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{
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u32 div;
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switch (pll) {
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case PLL_SYS:
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div = __raw_readl(&imx_ccm->analog_pll_sys);
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div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
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return infreq * (div >> 1);
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case PLL_BUS:
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div = __raw_readl(&imx_ccm->analog_pll_528);
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div &= BM_ANADIG_PLL_528_DIV_SELECT;
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return infreq * (20 + (div << 1));
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case PLL_USBOTG:
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div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
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div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
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return infreq * (20 + (div << 1));
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case PLL_ENET:
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div = __raw_readl(&imx_ccm->analog_pll_enet);
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div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
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return (div == 3 ? 125000000 : 25000000 * (div << 1));
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default:
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return 0;
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}
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/* NOTREACHED */
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}
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static u32 get_mcu_main_clk(void)
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{
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u32 reg, freq;
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reg = __raw_readl(&imx_ccm->cacrr);
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reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
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reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
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freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
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return freq / (reg + 1);
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}
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static u32 get_periph_clk(void)
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{
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u32 reg, freq = 0;
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reg = __raw_readl(&imx_ccm->cbcdr);
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if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
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reg = __raw_readl(&imx_ccm->cbcmr);
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reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
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reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
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switch (reg) {
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case 0:
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freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
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break;
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case 1:
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case 2:
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freq = CONFIG_SYS_MX6_HCLK;
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break;
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default:
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break;
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}
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} else {
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reg = __raw_readl(&imx_ccm->cbcmr);
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reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
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reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
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switch (reg) {
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case 0:
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freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
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break;
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case 1:
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freq = PLL2_PFD2_FREQ;
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break;
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case 2:
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freq = PLL2_PFD0_FREQ;
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break;
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case 3:
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freq = PLL2_PFD2_DIV_FREQ;
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break;
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default:
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break;
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}
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}
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return freq;
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}
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static u32 get_ahb_clk(void)
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{
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u32 reg, ahb_podf;
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reg = __raw_readl(&imx_ccm->cbcdr);
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reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
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ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
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return get_periph_clk() / (ahb_podf + 1);
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}
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static u32 get_ipg_clk(void)
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{
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u32 reg, ipg_podf;
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reg = __raw_readl(&imx_ccm->cbcdr);
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reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
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ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
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return get_ahb_clk() / (ipg_podf + 1);
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}
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static u32 get_ipg_per_clk(void)
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{
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u32 reg, perclk_podf;
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reg = __raw_readl(&imx_ccm->cscmr1);
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perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
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return get_ipg_clk() / (perclk_podf + 1);
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}
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static u32 get_uart_clk(void)
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{
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u32 reg, uart_podf;
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reg = __raw_readl(&imx_ccm->cscdr1);
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reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
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uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
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return PLL3_80M / (uart_podf + 1);
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}
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static u32 get_cspi_clk(void)
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{
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u32 reg, cspi_podf;
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reg = __raw_readl(&imx_ccm->cscdr2);
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reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
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cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
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return PLL3_60M / (cspi_podf + 1);
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}
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static u32 get_axi_clk(void)
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{
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u32 root_freq, axi_podf;
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
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axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
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if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
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if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
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root_freq = PLL2_PFD2_FREQ;
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else
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root_freq = PLL3_PFD1_FREQ;
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} else
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root_freq = get_periph_clk();
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return root_freq / (axi_podf + 1);
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}
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static u32 get_emi_slow_clk(void)
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{
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u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
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cscmr1 = __raw_readl(&imx_ccm->cscmr1);
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emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
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emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
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emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
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emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
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switch (emi_clk_sel) {
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case 0:
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root_freq = get_axi_clk();
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break;
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case 1:
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root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
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break;
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case 2:
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root_freq = PLL2_PFD2_FREQ;
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break;
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case 3:
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root_freq = PLL2_PFD0_FREQ;
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break;
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}
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return root_freq / (emi_slow_pof + 1);
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}
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static u32 get_mmdc_ch0_clk(void)
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{
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
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MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
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return get_periph_clk() / (mmdc_ch0_podf + 1);
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}
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static u32 get_usdhc_clk(u32 port)
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{
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u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
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u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
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u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
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switch (port) {
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case 0:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
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break;
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case 1:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
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break;
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case 2:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
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break;
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case 3:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
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break;
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default:
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break;
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}
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if (clk_sel)
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root_freq = PLL2_PFD0_FREQ;
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else
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root_freq = PLL2_PFD2_FREQ;
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return root_freq / (usdhc_podf + 1);
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}
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u32 imx_get_uartclk(void)
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{
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return get_uart_clk();
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_mcu_main_clk();
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case MXC_PER_CLK:
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return get_periph_clk();
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case MXC_AHB_CLK:
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return get_ahb_clk();
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case MXC_IPG_CLK:
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return get_ipg_clk();
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case MXC_IPG_PERCLK:
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return get_ipg_per_clk();
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case MXC_UART_CLK:
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return get_uart_clk();
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case MXC_CSPI_CLK:
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return get_cspi_clk();
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case MXC_AXI_CLK:
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return get_axi_clk();
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case MXC_EMI_SLOW_CLK:
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return get_emi_slow_clk();
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case MXC_DDR_CLK:
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return get_mmdc_ch0_clk();
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case MXC_ESDHC_CLK:
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return get_usdhc_clk(0);
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case MXC_ESDHC2_CLK:
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return get_usdhc_clk(1);
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case MXC_ESDHC3_CLK:
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return get_usdhc_clk(2);
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case MXC_ESDHC4_CLK:
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return get_usdhc_clk(3);
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case MXC_SATA_CLK:
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return get_ahb_clk();
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default:
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break;
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}
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return -1;
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}
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/*
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* Dump some core clockes.
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*/
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int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 freq;
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freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
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printf("PLL_SYS %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
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printf("PLL_BUS %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
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printf("PLL_OTG %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
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printf("PLL_NET %8d MHz\n", freq / 1000000);
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printf("\n");
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printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
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printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
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printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
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printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
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printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
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printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
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printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
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printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
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printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
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printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
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printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
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printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
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return 0;
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}
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/***************************************************/
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
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"display clocks",
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""
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);
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71
arch/arm/cpu/armv7/mx6/iomux-v3.c
Normal file
71
arch/arm/cpu/armv7/mx6/iomux-v3.c
Normal file
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@ -0,0 +1,71 @@
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/*
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* Based on the iomux-v3.c from Linux kernel:
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
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*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/iomux-v3.h>
|
||||
|
||||
static void *base = (void *)IOMUXC_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* configures a single pad in the iomuxer
|
||||
*/
|
||||
int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
|
||||
{
|
||||
u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
|
||||
u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
|
||||
u32 sel_input_ofs =
|
||||
(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
|
||||
u32 sel_input =
|
||||
(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
|
||||
u32 pad_ctrl_ofs =
|
||||
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
|
||||
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
|
||||
|
||||
if (mux_ctrl_ofs)
|
||||
__raw_writel(mux_mode, base + mux_ctrl_ofs);
|
||||
|
||||
if (sel_input_ofs)
|
||||
__raw_writel(sel_input, base + sel_input_ofs);
|
||||
|
||||
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
|
||||
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
|
||||
{
|
||||
iomux_v3_cfg_t *p = pad_list;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
ret = imx_iomux_v3_setup_pad(*p);
|
||||
if (ret)
|
||||
return ret;
|
||||
p++;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
24
arch/arm/cpu/armv7/mx6/lowlevel_init.S
Normal file
24
arch/arm/cpu/armv7/mx6/lowlevel_init.S
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
.section ".text.init", "x"
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
mov pc, lr
|
||||
82
arch/arm/cpu/armv7/mx6/soc.c
Normal file
82
arch/arm/cpu/armv7/mx6/soc.c
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Sascha Hauer, Pengutronix
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
int system_rev = 0x61000 | CHIP_REV_1_0;
|
||||
|
||||
return system_rev;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_CPU_INIT
|
||||
void init_aips(void)
|
||||
{
|
||||
u32 reg = AIPS1_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
||||
* not forced to user-mode.
|
||||
*/
|
||||
writel(0x77777777, reg + 0x00);
|
||||
writel(0x77777777, reg + 0x04);
|
||||
|
||||
reg = AIPS2_BASE_ADDR;
|
||||
writel(0x77777777, reg + 0x00);
|
||||
writel(0x77777777, reg + 0x04);
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
init_aips();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
void imx_get_mac_from_fuse(unsigned char *mac)
|
||||
{
|
||||
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
|
||||
struct fuse_bank *bank = &iim->bank[4];
|
||||
struct fuse_bank4_regs *fuse =
|
||||
(struct fuse_bank4_regs *)bank->fuse_regs;
|
||||
|
||||
u32 mac_lo = readl(&fuse->mac_addr_low);
|
||||
u32 mac_hi = readl(&fuse->mac_addr_high);
|
||||
|
||||
*(u32 *)mac = mac_lo;
|
||||
|
||||
mac[4] = mac_hi & 0xff;
|
||||
mac[5] = (mac_hi >> 8) & 0xff;
|
||||
|
||||
}
|
||||
#endif
|
||||
892
arch/arm/include/asm/arch-mx6/ccm_regs.h
Normal file
892
arch/arm/include/asm/arch-mx6/ccm_regs.h
Normal file
|
|
@ -0,0 +1,892 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
|
||||
|
||||
struct imx_ccm_reg {
|
||||
u32 ccr; /* 0x0000 */
|
||||
u32 ccdr;
|
||||
u32 csr;
|
||||
u32 ccsr;
|
||||
u32 cacrr; /* 0x0010*/
|
||||
u32 cbcdr;
|
||||
u32 cbcmr;
|
||||
u32 cscmr1;
|
||||
u32 cscmr2; /* 0x0020 */
|
||||
u32 cscdr1;
|
||||
u32 cs1cdr;
|
||||
u32 cs2cdr;
|
||||
u32 cdcdr; /* 0x0030 */
|
||||
u32 chscdr;
|
||||
u32 cscdr2;
|
||||
u32 cscdr3;
|
||||
u32 cscdr4; /* 0x0040 */
|
||||
u32 resv0;
|
||||
u32 cdhipr;
|
||||
u32 cdcr;
|
||||
u32 ctor; /* 0x0050 */
|
||||
u32 clpcr;
|
||||
u32 cisr;
|
||||
u32 cimr;
|
||||
u32 ccosr; /* 0x0060 */
|
||||
u32 cgpr;
|
||||
u32 CCGR0;
|
||||
u32 CCGR1;
|
||||
u32 CCGR2; /* 0x0070 */
|
||||
u32 CCGR3;
|
||||
u32 CCGR4;
|
||||
u32 CCGR5;
|
||||
u32 CCGR6; /* 0x0080 */
|
||||
u32 CCGR7;
|
||||
u32 cmeor;
|
||||
u32 resv[0xfdd];
|
||||
u32 analog_pll_sys; /* 0x4000 */
|
||||
u32 analog_pll_sys_set;
|
||||
u32 analog_pll_sys_clr;
|
||||
u32 analog_pll_sys_tog;
|
||||
u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
|
||||
u32 analog_usb1_pll_480_ctrl_set;
|
||||
u32 analog_usb1_pll_480_ctrl_clr;
|
||||
u32 analog_usb1_pll_480_ctrl_tog;
|
||||
u32 analog_reserved0[4];
|
||||
u32 analog_pll_528; /* 0x4030 */
|
||||
u32 analog_pll_528_set;
|
||||
u32 analog_pll_528_clr;
|
||||
u32 analog_pll_528_tog;
|
||||
u32 analog_pll_528_ss; /* 0x4040 */
|
||||
u32 analog_reserved1[3];
|
||||
u32 analog_pll_528_num; /* 0x4050 */
|
||||
u32 analog_reserved2[3];
|
||||
u32 analog_pll_528_denom; /* 0x4060 */
|
||||
u32 analog_reserved3[3];
|
||||
u32 analog_pll_audio; /* 0x4070 */
|
||||
u32 analog_pll_audio_set;
|
||||
u32 analog_pll_audio_clr;
|
||||
u32 analog_pll_audio_tog;
|
||||
u32 analog_pll_audio_num; /* 0x4080*/
|
||||
u32 analog_reserved4[3];
|
||||
u32 analog_pll_audio_denom; /* 0x4090 */
|
||||
u32 analog_reserved5[3];
|
||||
u32 analog_pll_video; /* 0x40a0 */
|
||||
u32 analog_pll_video_set;
|
||||
u32 analog_pll_video_clr;
|
||||
u32 analog_pll_video_tog;
|
||||
u32 analog_pll_video_num; /* 0x40b0 */
|
||||
u32 analog_reserved6[3];
|
||||
u32 analog_pll_vedio_denon; /* 0x40c0 */
|
||||
u32 analog_reserved7[7];
|
||||
u32 analog_pll_enet; /* 0x40e0 */
|
||||
u32 analog_pll_enet_set;
|
||||
u32 analog_pll_enet_clr;
|
||||
u32 analog_pll_enet_tog;
|
||||
u32 analog_pfd_480; /* 0x40f0 */
|
||||
u32 analog_pfd_480_set;
|
||||
u32 analog_pfd_480_clr;
|
||||
u32 analog_pfd_480_tog;
|
||||
u32 analog_pfd_528; /* 0x4100 */
|
||||
u32 analog_pfd_528_set;
|
||||
u32 analog_pfd_528_clr;
|
||||
u32 analog_pfd_528_tog;
|
||||
};
|
||||
|
||||
/* Define the bits in register CCR */
|
||||
#define MXC_CCM_CCR_RBC_EN (1 << 27)
|
||||
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
|
||||
#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
|
||||
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
|
||||
#define MXC_CCM_CCR_COSC_EN (1 << 12)
|
||||
#define MXC_CCM_CCR_OSCNT_MASK 0xFF
|
||||
#define MXC_CCM_CCR_OSCNT_OFFSET 0
|
||||
|
||||
/* Define the bits in register CCDR */
|
||||
#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
|
||||
#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
|
||||
|
||||
/* Define the bits in register CSR */
|
||||
#define MXC_CCM_CSR_COSC_READY (1 << 5)
|
||||
#define MXC_CCM_CSR_REF_EN_B (1 << 0)
|
||||
|
||||
/* Define the bits in register CCSR */
|
||||
#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
|
||||
#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
|
||||
#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
|
||||
#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
|
||||
#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
|
||||
#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
|
||||
#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
|
||||
#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
|
||||
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
|
||||
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CACRR */
|
||||
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
|
||||
#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
|
||||
|
||||
/* Define the bits in register CBCDR */
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
|
||||
#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
|
||||
#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
|
||||
#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CBCMR */
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
|
||||
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
|
||||
#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
|
||||
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
|
||||
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CSCMR1 */
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
|
||||
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
|
||||
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
|
||||
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
|
||||
#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
|
||||
#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
|
||||
|
||||
/* Define the bits in register CSCMR2 */
|
||||
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
|
||||
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
|
||||
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
|
||||
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
|
||||
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
|
||||
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
|
||||
|
||||
/* Define the bits in register CSCDR1 */
|
||||
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
|
||||
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
|
||||
#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
|
||||
#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CS1CDR */
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
|
||||
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CS2CDR */
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CDCDR */
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
|
||||
#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
|
||||
|
||||
/* Define the bits in register CHSCCDR */
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in register CSCDR2 */
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in register CSCDR3 */
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
|
||||
|
||||
/* Define the bits in register CDHIPR */
|
||||
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
|
||||
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
|
||||
#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
|
||||
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
|
||||
#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
|
||||
|
||||
/* Define the bits in register CLPCR */
|
||||
#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
|
||||
#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
|
||||
#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
|
||||
#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
|
||||
#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
|
||||
#define MXC_CCM_CLPCR_VSTBY (1 << 8)
|
||||
#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
|
||||
#define MXC_CCM_CLPCR_SBYOS (1 << 6)
|
||||
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
|
||||
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
|
||||
#define MXC_CCM_CLPCR_LPM_MASK 0x3
|
||||
#define MXC_CCM_CLPCR_LPM_OFFSET 0
|
||||
|
||||
/* Define the bits in register CISR */
|
||||
#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
|
||||
#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CISR_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CISR_LRF_PLL 1
|
||||
|
||||
/* Define the bits in register CIMR */
|
||||
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL 1
|
||||
|
||||
/* Define the bits in register CCOSR */
|
||||
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
|
||||
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in registers CGPR */
|
||||
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
|
||||
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
|
||||
#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
|
||||
|
||||
/* Define the bits in registers CCGRx */
|
||||
#define MXC_CCM_CCGR_CG_MASK 3
|
||||
|
||||
#define MXC_CCM_CCGR0_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
|
||||
#define MXC_CCM_CCGR0_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR0_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR0_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR0_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR0_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR0_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR0_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR0_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR0_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR0_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CCGR0_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CCGR0_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CCGR0_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR0_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CCGR0_CG0_OFFSET 0
|
||||
#define MXC_CCM_CCGR0_CG0_MASK 3
|
||||
|
||||
#define MXC_CCM_CCGR1_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR1_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR1_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR1_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR1_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR1_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR1_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR1_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR1_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR1_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR1_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR1_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR1_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR1_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR1_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR1_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR2_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR2_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR2_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR2_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR2_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR2_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR2_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR2_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR2_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR2_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR2_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR2_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR2_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR2_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR2_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR2_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR3_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR3_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR3_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR3_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR3_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR3_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR3_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR3_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR3_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR3_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR3_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR3_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR3_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR3_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR3_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR3_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR4_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR4_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR4_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR4_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR4_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR4_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR4_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR4_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR4_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR4_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR4_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR4_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR4_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR4_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR4_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR4_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR5_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR5_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR5_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR5_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR5_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR5_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR5_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR5_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR5_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR5_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR5_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR5_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR5_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR5_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR5_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR5_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR6_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR6_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR6_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR6_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR6_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR6_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR6_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR6_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR6_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR6_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR6_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR6_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR6_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR6_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR6_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR6_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR7_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR7_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR7_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR7_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR7_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR7_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR7_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR7_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR7_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR7_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR7_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR7_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR7_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR7_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR7_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR7_CG0_OFFSET 0
|
||||
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_SYS_RSVD0 20
|
||||
#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
|
||||
#define BF_ANADIG_PLL_SYS_RSVD0(v) \
|
||||
(((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
|
||||
#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
|
||||
#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
|
||||
#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
|
||||
#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
|
||||
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
|
||||
(((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
|
||||
(((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
|
||||
|
||||
#define BM_ANADIG_PLL_528_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_528_RSVD1 19
|
||||
#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
|
||||
#define BF_ANADIG_PLL_528_RSVD1(v) \
|
||||
(((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
|
||||
#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_528_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_528_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_528_RSVD0 1
|
||||
#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
|
||||
#define BF_ANADIG_PLL_528_RSVD0(v) \
|
||||
(((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
|
||||
#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
|
||||
|
||||
#define BP_ANADIG_PLL_528_SS_STOP 16
|
||||
#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
|
||||
#define BF_ANADIG_PLL_528_SS_STOP(v) \
|
||||
(((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
|
||||
#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
|
||||
#define BP_ANADIG_PLL_528_SS_STEP 0
|
||||
#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
|
||||
#define BF_ANADIG_PLL_528_SS_STEP(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
|
||||
|
||||
#define BP_ANADIG_PLL_528_NUM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
|
||||
#define BP_ANADIG_PLL_528_NUM_A 0
|
||||
#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_528_NUM_A(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
|
||||
|
||||
#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
|
||||
#define BP_ANADIG_PLL_528_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_528_DENOM_B(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
|
||||
|
||||
#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_AUDIO_RSVD0 22
|
||||
#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
|
||||
#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
|
||||
(((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
|
||||
#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
|
||||
#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
|
||||
#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
|
||||
#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
|
||||
(((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
|
||||
#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
|
||||
|
||||
#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
|
||||
#define BP_ANADIG_PLL_AUDIO_NUM_A 0
|
||||
#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
|
||||
|
||||
#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
|
||||
#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
|
||||
|
||||
#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_VIDEO_RSVD0 22
|
||||
#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
|
||||
#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
|
||||
(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
|
||||
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
|
||||
#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
|
||||
#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
|
||||
#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
|
||||
(((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
|
||||
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
|
||||
|
||||
#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
|
||||
#define BP_ANADIG_PLL_VIDEO_NUM_A 0
|
||||
#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
|
||||
|
||||
#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
|
||||
#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
|
||||
|
||||
#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_ENET_RSVD1 21
|
||||
#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
|
||||
#define BF_ANADIG_PLL_ENET_RSVD1(v) \
|
||||
(((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
|
||||
#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_ENET_RSVD0 2
|
||||
#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
|
||||
#define BF_ANADIG_PLL_ENET_RSVD0(v) \
|
||||
(((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
|
||||
#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
|
||||
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
|
||||
|
||||
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
|
||||
#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
|
||||
#define BP_ANADIG_PFD_480_PFD3_FRAC 24
|
||||
#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
|
||||
#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
|
||||
(((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
|
||||
#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
|
||||
#define BP_ANADIG_PFD_480_PFD2_FRAC 16
|
||||
#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
|
||||
#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
|
||||
(((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
|
||||
#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
|
||||
#define BP_ANADIG_PFD_480_PFD1_FRAC 8
|
||||
#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
|
||||
#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
|
||||
(((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
|
||||
#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
|
||||
#define BP_ANADIG_PFD_480_PFD0_FRAC 0
|
||||
#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
|
||||
#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
|
||||
(((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
|
||||
|
||||
#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
|
||||
#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
|
||||
#define BP_ANADIG_PFD_528_PFD3_FRAC 24
|
||||
#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
|
||||
#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
|
||||
(((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
|
||||
#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
|
||||
#define BP_ANADIG_PFD_528_PFD2_FRAC 16
|
||||
#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
|
||||
#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
|
||||
(((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
|
||||
#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
|
||||
#define BP_ANADIG_PFD_528_PFD1_FRAC 8
|
||||
#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
|
||||
#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
|
||||
(((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
|
||||
#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
|
||||
#define BP_ANADIG_PFD_528_PFD0_FRAC 0
|
||||
#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
|
||||
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
|
||||
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
|
||||
|
||||
#define PLL2_PFD0_FREQ 352000000
|
||||
#define PLL2_PFD1_FREQ 594000000
|
||||
#define PLL2_PFD2_FREQ 400000000
|
||||
#define PLL2_PFD2_DIV_FREQ 200000000
|
||||
#define PLL3_PFD0_FREQ 720000000
|
||||
#define PLL3_PFD1_FREQ 540000000
|
||||
#define PLL3_PFD2_FREQ 508200000
|
||||
#define PLL3_PFD3_FREQ 454700000
|
||||
#define PLL3_80M 80000000
|
||||
#define PLL3_60M 60000000
|
||||
|
||||
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
|
||||
50
arch/arm/include/asm/arch-mx6/clock.h
Normal file
50
arch/arm/include/asm/arch-mx6/clock.h
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_PER_CLK,
|
||||
MXC_AHB_CLK,
|
||||
MXC_IPG_CLK,
|
||||
MXC_IPG_PERCLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_AXI_CLK,
|
||||
MXC_EMI_SLOW_CLK,
|
||||
MXC_DDR_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_ESDHC3_CLK,
|
||||
MXC_ESDHC4_CLK,
|
||||
MXC_SATA_CLK,
|
||||
MXC_NFC_CLK,
|
||||
};
|
||||
|
||||
u32 imx_get_uartclk(void);
|
||||
u32 imx_get_fecclk(void);
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
35
arch/arm/include/asm/arch-mx6/gpio.h
Normal file
35
arch/arm/include/asm/arch-mx6/gpio.h
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_ARCH_MX6_GPIO_H
|
||||
#define __ASM_ARCH_MX6_GPIO_H
|
||||
|
||||
/* GPIO registers */
|
||||
struct gpio_regs {
|
||||
u32 gpio_dr;
|
||||
u32 gpio_dir;
|
||||
u32 gpio_psr;
|
||||
};
|
||||
|
||||
#endif /* __ASM_ARCH_MX6_GPIO_H */
|
||||
236
arch/arm/include/asm/arch-mx6/imx-regs.h
Normal file
236
arch/arm/include/asm/arch-mx6/imx-regs.h
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
|
||||
#define __ASM_ARCH_MX6_IMX_REGS_H__
|
||||
|
||||
#define ROMCP_ARB_BASE_ADDR 0x00000000
|
||||
#define ROMCP_ARB_END_ADDR 0x000FFFFF
|
||||
#define CAAM_ARB_BASE_ADDR 0x00100000
|
||||
#define CAAM_ARB_END_ADDR 0x00103FFF
|
||||
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
|
||||
#define APBH_DMA_ARB_END_ADDR 0x00117FFF
|
||||
#define HDMI_ARB_BASE_ADDR 0x00120000
|
||||
#define HDMI_ARB_END_ADDR 0x00128FFF
|
||||
#define GPU_3D_ARB_BASE_ADDR 0x00130000
|
||||
#define GPU_3D_ARB_END_ADDR 0x00133FFF
|
||||
#define GPU_2D_ARB_BASE_ADDR 0x00134000
|
||||
#define GPU_2D_ARB_END_ADDR 0x00137FFF
|
||||
#define DTCP_ARB_BASE_ADDR 0x00138000
|
||||
#define DTCP_ARB_END_ADDR 0x0013BFFF
|
||||
|
||||
/* GPV - PL301 configuration ports */
|
||||
#define GPV2_BASE_ADDR 0x00200000
|
||||
#define GPV3_BASE_ADDR 0x00300000
|
||||
#define GPV4_BASE_ADDR 0x00800000
|
||||
#define IRAM_BASE_ADDR 0x00900000
|
||||
#define SCU_BASE_ADDR 0x00A00000
|
||||
#define IC_INTERFACES_BASE_ADDR 0x00A00100
|
||||
#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
|
||||
#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
|
||||
#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
|
||||
#define GPV0_BASE_ADDR 0x00B00000
|
||||
#define GPV1_BASE_ADDR 0x00C00000
|
||||
#define PCIE_ARB_BASE_ADDR 0x01000000
|
||||
#define PCIE_ARB_END_ADDR 0x01FFFFFF
|
||||
|
||||
#define AIPS1_ARB_BASE_ADDR 0x02000000
|
||||
#define AIPS1_ARB_END_ADDR 0x020FFFFF
|
||||
#define AIPS2_ARB_BASE_ADDR 0x02100000
|
||||
#define AIPS2_ARB_END_ADDR 0x021FFFFF
|
||||
#define SATA_ARB_BASE_ADDR 0x02200000
|
||||
#define SATA_ARB_END_ADDR 0x02203FFF
|
||||
#define OPENVG_ARB_BASE_ADDR 0x02204000
|
||||
#define OPENVG_ARB_END_ADDR 0x02207FFF
|
||||
#define HSI_ARB_BASE_ADDR 0x02208000
|
||||
#define HSI_ARB_END_ADDR 0x0220BFFF
|
||||
#define IPU1_ARB_BASE_ADDR 0x02400000
|
||||
#define IPU1_ARB_END_ADDR 0x027FFFFF
|
||||
#define IPU2_ARB_BASE_ADDR 0x02800000
|
||||
#define IPU2_ARB_END_ADDR 0x02BFFFFF
|
||||
#define WEIM_ARB_BASE_ADDR 0x08000000
|
||||
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
|
||||
|
||||
#define MMDC0_ARB_BASE_ADDR 0x10000000
|
||||
#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
|
||||
#define MMDC1_ARB_BASE_ADDR 0x80000000
|
||||
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
|
||||
|
||||
/* Defines for Blocks connected via AIPS (SkyBlue) */
|
||||
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
|
||||
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
|
||||
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
|
||||
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
|
||||
|
||||
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
|
||||
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
|
||||
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
|
||||
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
|
||||
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
|
||||
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
|
||||
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
|
||||
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
|
||||
#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
|
||||
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
|
||||
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
|
||||
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
|
||||
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
|
||||
#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
|
||||
#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
|
||||
|
||||
#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
|
||||
#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
|
||||
#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
|
||||
#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
|
||||
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
|
||||
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
|
||||
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
|
||||
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
|
||||
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
|
||||
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
|
||||
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
|
||||
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
|
||||
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
|
||||
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
|
||||
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
|
||||
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
|
||||
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
|
||||
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
|
||||
#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
|
||||
#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
|
||||
#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
|
||||
#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
|
||||
#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
|
||||
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
|
||||
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
|
||||
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
|
||||
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
|
||||
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
|
||||
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
|
||||
|
||||
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
|
||||
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
|
||||
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
|
||||
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
|
||||
#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
|
||||
#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
|
||||
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
|
||||
#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
|
||||
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
|
||||
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
|
||||
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
|
||||
#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
|
||||
#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
|
||||
#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
|
||||
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
|
||||
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
|
||||
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
|
||||
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
|
||||
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
|
||||
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
|
||||
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
|
||||
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
|
||||
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
|
||||
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
|
||||
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
|
||||
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
|
||||
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
|
||||
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
|
||||
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
|
||||
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
|
||||
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
|
||||
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
|
||||
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
|
||||
#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
|
||||
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
|
||||
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define IRAM_SIZE 0x00040000
|
||||
#define IMX_IIM_BASE OCOTP_BASE_ADDR
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
|
||||
extern void imx_get_mac_from_fuse(unsigned char *mac);
|
||||
|
||||
/* System Reset Controller (SRC) */
|
||||
struct src {
|
||||
u32 scr;
|
||||
u32 sbmr1;
|
||||
u32 srsr;
|
||||
u32 reserved1[2];
|
||||
u32 sisr;
|
||||
u32 simr;
|
||||
u32 sbmr2;
|
||||
u32 gpr1;
|
||||
u32 gpr2;
|
||||
u32 gpr3;
|
||||
u32 gpr4;
|
||||
u32 gpr5;
|
||||
u32 gpr6;
|
||||
u32 gpr7;
|
||||
u32 gpr8;
|
||||
u32 gpr9;
|
||||
u32 gpr10;
|
||||
};
|
||||
|
||||
struct iim_regs {
|
||||
u32 ctrl;
|
||||
u32 ctrl_set;
|
||||
u32 ctrl_clr;
|
||||
u32 ctrl_tog;
|
||||
u32 timing;
|
||||
u32 rsvd0[3];
|
||||
u32 data;
|
||||
u32 rsvd1[3];
|
||||
u32 read_ctrl;
|
||||
u32 rsvd2[3];
|
||||
u32 fuse_data;
|
||||
u32 rsvd3[3];
|
||||
u32 sticky;
|
||||
u32 rsvd4[3];
|
||||
u32 scs;
|
||||
u32 scs_set;
|
||||
u32 scs_clr;
|
||||
u32 scs_tog;
|
||||
u32 crc_addr;
|
||||
u32 rsvd5[3];
|
||||
u32 crc_value;
|
||||
u32 rsvd6[3];
|
||||
u32 version;
|
||||
u32 rsvd7[0xd8];
|
||||
|
||||
struct fuse_bank {
|
||||
u32 fuse_regs[0x20];
|
||||
} bank[15];
|
||||
};
|
||||
|
||||
struct fuse_bank4_regs {
|
||||
u32 sjc_resp_low;
|
||||
u32 rsvd0[3];
|
||||
u32 sjc_resp_high;
|
||||
u32 rsvd1[3];
|
||||
u32 mac_addr_low;
|
||||
u32 rsvd2[3];
|
||||
u32 mac_addr_high;
|
||||
u32 rsvd3[0x13];
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLER__*/
|
||||
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
|
||||
103
arch/arm/include/asm/arch-mx6/iomux-v3.h
Normal file
103
arch/arm/include/asm/arch-mx6/iomux-v3.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Based on Linux i.MX iomux-v3.h file:
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
|
||||
* <armlinux@phytec.de>
|
||||
*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_IOMUX_V3_H__
|
||||
#define __MACH_IOMUX_V3_H__
|
||||
|
||||
/*
|
||||
* build IOMUX_PAD structure
|
||||
*
|
||||
* This iomux scheme is based around pads, which are the physical balls
|
||||
* on the processor.
|
||||
*
|
||||
* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
|
||||
* things like driving strength and pullup/pulldown.
|
||||
* - Each pad can have but not necessarily does have an output routing register
|
||||
* (IOMUXC_SW_MUX_CTL_PAD_x).
|
||||
* - Each pad can have but not necessarily does have an input routing register
|
||||
* (IOMUXC_x_SELECT_INPUT)
|
||||
*
|
||||
* The three register sets do not have a fixed offset to each other,
|
||||
* hence we order this table by pad control registers (which all pads
|
||||
* have) and put the optional i/o routing registers into additional
|
||||
* fields.
|
||||
*
|
||||
* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
|
||||
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
|
||||
*
|
||||
* IOMUX/PAD Bit field definitions
|
||||
*
|
||||
* MUX_CTRL_OFS: 0..11 (12)
|
||||
* PAD_CTRL_OFS: 12..23 (12)
|
||||
* SEL_INPUT_OFS: 24..35 (12)
|
||||
* MUX_MODE + SION: 36..40 (5)
|
||||
* PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
|
||||
* SEL_INP: 59..62 (4)
|
||||
* reserved: 63 (1)
|
||||
*/
|
||||
|
||||
typedef u64 iomux_v3_cfg_t;
|
||||
|
||||
#define MUX_CTRL_OFS_SHIFT 0
|
||||
#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
|
||||
#define MUX_PAD_CTRL_OFS_SHIFT 12
|
||||
#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
|
||||
MUX_PAD_CTRL_OFS_SHIFT)
|
||||
#define MUX_SEL_INPUT_OFS_SHIFT 24
|
||||
#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
|
||||
MUX_SEL_INPUT_OFS_SHIFT)
|
||||
|
||||
#define MUX_MODE_SHIFT 36
|
||||
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
|
||||
#define MUX_PAD_CTRL_SHIFT 41
|
||||
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
|
||||
#define MUX_SEL_INPUT_SHIFT 59
|
||||
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
|
||||
|
||||
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
|
||||
|
||||
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
|
||||
sel_input, pad_ctrl) \
|
||||
(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
|
||||
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
|
||||
|
||||
#define NO_PAD_CTRL (1 << 17)
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
#define GPIO_PORT_SHIFT 5
|
||||
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define MUX_CONFIG_SION (0x1 << 4)
|
||||
|
||||
int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
|
||||
|
||||
#endif /* __MACH_IOMUX_V3_H__*/
|
||||
1683
arch/arm/include/asm/arch-mx6/mx6x_pins.h
Normal file
1683
arch/arm/include/asm/arch-mx6/mx6x_pins.h
Normal file
File diff suppressed because it is too large
Load diff
38
arch/arm/include/asm/arch-mx6/sys_proto.h
Normal file
38
arch/arm/include/asm/arch-mx6/sys_proto.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
|
||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
|
||||
|
||||
u32 get_cpu_rev(void);
|
||||
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers.
|
||||
* to override, implement board_eth_init()
|
||||
*/
|
||||
|
||||
int fecmxc_initialize(bd_t *bis);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue