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arch: mach-k3: Fix incorrect mapping of higher DDR addresses as device memory

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Entry for physical address 0x500000000 in memory map table for MMU
configuration is spilling over and inadvertently making DDR available at
higher address (above 4GB address space) get mapped as device memory
(nGnRnE).

Fix this by adjusting entry size. Tested on AM62A SK. Before this patch:

=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca

time: 1 minutes, 14.716 seconds

After patch:

=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca

time: 2.710 seconds

Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Sekhar Nori 2024-01-09 14:15:51 +05:30 committed by Tom Rini
parent 2d30b293c8
commit 22d238f25d
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-k3/arm64-mmu.c
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@ -41,7 +41,7 @@ struct mm_region k3_mem_map[] = {
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.size = 0x380000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN