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fsl-ddr: change the default burst mode for DDR3

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For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.

Signed-off-by: Dave Liu <daveliu@freescale.com>
This commit is contained in:
Dave Liu 2010-03-05 12:22:00 +08:00 committed by Kumar Gala
parent ec145e87b8
commit 22c9de064a
1 changed files with 10 additions and 4 deletions
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14
cpu/mpc8xxx/ddr/options.c
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@ -1,9 +1,10 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008, 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <common.h>
@ -109,8 +110,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_E500MC)
popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
#else
popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
#endif
#else
popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
#endif