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Merge branch 'master' of git://git.denx.de/u-boot

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This commit is contained in:
Minkyu Kang 2010-07-06 17:29:44 +09:00
commit 2271d3ddcc
589 changed files with 8244 additions and 23879 deletions
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1189
CHANGELOG
View file

File diff suppressed because it is too large Load diff

35
MAINTAINERS
View file

@ -354,6 +354,10 @@ Daniel Poirot <dan.poirot@windriver.com>
sbc8240 MPC8240
sbc405 PPC405GP
Sudhakar Rajashekhara <sudhakar.raj@ti.com>
da850evm ARM926EJS (DA850/OMAP-L138)
Ricardo Ribalda <ricardo.ribalda@uam.es>
ml507 PPC440x5
@ -388,6 +392,7 @@ Stefan Roese <sr@denx.de>
rainier PPC440GRx
sequoia PPC440EPx
sycamore PPC405GPr
t3corp PPC460GT
taishan PPC440GX
walnut PPC405GP
yellowstone PPC440GR
@ -530,6 +535,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
Albert ARIBAUD <albert.aribaud@free.fr>
edminiv2 ARM926EJS (Orion5x SoC)
Rowel Atienza <rowel@diwalabs.com>
armadillo ARM720T
@ -669,12 +678,6 @@ Sergey Lapin <slapin@ossfans.org>
afeb9260 ARM926EJS (AT91SAM9260 SoC)
Guennadi Liakhovetski <g.liakhovetski@gmx.de>
imx31_phycore_eet i.MX31
mx31ads i.MX31
SMDK6400 S3C6400
Nishanth Menon <nm@ti.com>
omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC)
@ -817,6 +820,10 @@ Unknown / orphaned boards:
ixdp425 xscale Kyle Harris <kharris@nexus-tech.net> / dead address
lubbock xscale Kyle Harris <kharris@nexus-tech.net> / dead address
imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
mx31ads i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
SMDK6400 S3C6400 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
#########################################################################
# x86 Systems: #
# #
@ -851,22 +858,6 @@ Stefan Roese <sr@denx.de>
vct_xxx MIPS32 4Kc
#########################################################################
# Nios-32 Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Stephan Linz <linz@li-pro.net>
DK1S10 Nios-32
ADNPESC1 Nios-32
Scott McNutt <smcnutt@psyent.com>
DK1C20 Nios-32
#########################################################################
# Nios-II Systems: #
# #

22
MAKEALL
View file

@ -262,6 +262,7 @@ LIST_4xx=" \
sc3 \
sequoia \
sequoia_nand \
t3corp \
taihu \
taishan \
v5fx30teval \
@ -393,6 +394,7 @@ LIST_85xx=" \
MPC8536DS_NAND \
MPC8536DS_SDCARD \
MPC8536DS_SPIFLASH \
MPC8536DS_36BIT \
MPC8540ADS \
MPC8540EVAL \
MPC8541CDS \
@ -453,6 +455,7 @@ LIST_85xx=" \
LIST_86xx=" \
MPC8610HPCD \
MPC8641HPCN_36BIT \
MPC8641HPCN \
sbc8641d \
XPEDITE5170 \
@ -561,6 +564,7 @@ LIST_ARM9=" \
cp946es \
cp966 \
da830evm \
da850evm \
edb9301 \
edb9302 \
edb9302a \
@ -569,6 +573,7 @@ LIST_ARM9=" \
edb9312 \
edb9315 \
edb9315a \
edminiv2 \
guruplug \
imx27lite \
lpd7a400 \
@ -814,21 +819,6 @@ LIST_x86=" \
${LIST_I486} \
"
#########################################################################
## NIOS Systems
#########################################################################
LIST_nios=" \
ADNPESC1 \
ADNPESC1_base_32 \
ADNPESC1_DNPEVA2_base_32\
DK1C20 \
DK1C20_standard_32 \
DK1S10 \
DK1S10_standard_32 \
DK1S10_mtx_ldk_20 \
"
#########################################################################
## Nios-II Systems
#########################################################################
@ -1021,7 +1011,7 @@ do
|coldfire \
|microblaze \
|mips|mips_el \
|nios|nios2 \
|nios2 \
|ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
|sh|sh2|sh3|sh4 \
|sparc \

1890
Makefile
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File diff suppressed because it is too large Load diff

23
README
View file

@ -143,9 +143,9 @@ Directory Hierarchy:
/cpu CPU specific files
/arm720t Files specific to ARM 720 CPUs
/arm920t Files specific to ARM 920 CPUs
/at91rm9200 Files specific to Atmel AT91RM9200 CPU
/imx Files specific to Freescale MC9328 i.MX CPUs
/s3c24x0 Files specific to Samsung S3C24X0 CPUs
/at91rm9200 Files specific to Atmel AT91RM9200 CPU
/imx Files specific to Freescale MC9328 i.MX CPUs
/s3c24x0 Files specific to Samsung S3C24X0 CPUs
/arm925t Files specific to ARM 925 CPUs
/arm926ejs Files specific to ARM 926 CPUs
/arm1136 Files specific to ARM 1136 CPUs
@ -177,9 +177,6 @@ Directory Hierarchy:
/mips Files generic to MIPS architecture
/cpu CPU specific files
/lib Architecture specific library files
/nios Files generic to Altera NIOS architecture
/cpu CPU specific files
/lib Architecture specific library files
/nios2 Files generic to Altera NIOS2 architecture
/cpu CPU specific files
/lib Architecture specific library files
@ -2507,7 +2504,7 @@ to save the current settings.
I2C muxes, you can define here, how to reach this
EEPROM. For example:
#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
EEPROM which holds the environment, is reached over
a pca9547 i2c mux with address 0x70, channel 3.
@ -3337,8 +3334,8 @@ details; basically, the header defines the following image properties:
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
INTEGRITY).
* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
* Compression Type (uncompressed, gzip, bzip2)
* Load Address
* Entry Point
@ -4023,6 +4020,14 @@ On ARM, the following registers are used:
==> U-Boot will use R8 to hold a pointer to the global data
On Nios II, the ABI is documented here:
http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
==> U-Boot will use gp to hold a pointer to the global data
Note: on Nios II, we give "-G0" option to gcc and don't use gp
to access small data sections, so gp is free.
NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
or current versions of GCC may "optimize" the code too much.

2
api/api.c
View file

@ -37,7 +37,7 @@
#undef DEBUG
/* U-Boot routines needed */
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*****************************************************************************
*

1
arch/arm/cpu/arm1136/start.S
View file

@ -185,6 +185,7 @@ stack_setup:
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
#endif /* CONFIG_PRELOADER */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/arm1176/start.S
View file

@ -276,6 +276,7 @@ stack_setup:
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/arm720t/start.S
View file

@ -172,6 +172,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/arm920t/start.S
View file

@ -204,6 +204,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/arm925t/start.S
View file

@ -196,6 +196,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

33
arch/nios/cpu/Makefile → arch/arm/cpu/arm926ejs/orion5x/Makefile
View file

@ -1,6 +1,10 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
#
# Based on original Kirkwood support which is
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@ -12,28 +16,31 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
LIB = $(obj)lib$(SOC).a
START = start.o
SOBJS = traps.o
COBJS = cpu.o interrupts.o serial.o asmi.o spi.o
COBJS-y = cpu.o
COBJS-y += dram.o
COBJS-y += timer.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
ifndef CONFIG_SKIP_LOWLEVEL_INIT
SOBJS := lowlevel_init.o
endif
all: $(obj).depend $(START) $(LIB)
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)

270
arch/arm/cpu/arm926ejs/orion5x/cpu.c Normal file
View file

@ -0,0 +1,270 @@
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/cache.h>
#include <u-boot/md5.h>
#include <asm/arch/orion5x.h>
#include <hush.h>
#define BUFLEN 16
void reset_cpu(unsigned long ignored)
{
struct orion5x_cpu_registers *cpureg =
(struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
&cpureg->rstoutn_mask);
writel(readl(&cpureg->sys_soft_rst) | 1,
&cpureg->sys_soft_rst);
while (1)
;
}
/*
* Window Size
* Used with the Base register to set the address window size and location.
* Must be programmed from LSB to MSB as sequence of ones followed by
* sequence of zeros. The number of ones specifies the size of the window in
* 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
* NOTE: A value of 0x0 specifies 64-KByte size.
*/
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
{
int i;
unsigned int j = 0;
u32 val = sizeval >> 1;
for (i = 0; val > 0x10000; i++) {
j |= (1 << i);
val = val >> 1;
}
return 0x0000ffff & j;
}
/*
* orion5x_config_adr_windows - Configure address Windows
*
* There are 8 address windows supported by Orion5x Soc to addess different
* devices. Each window can be configured for size, BAR and remap addr
* Below configuration is standard for most of the cases
*
* If remap function not used, remap_lo must be set as base
*
* Reference Documentation:
* Mbus-L to Mbus Bridge Registers Configuration.
* (Sec 25.1 and 25.3 of Datasheet)
*/
int orion5x_config_adr_windows(void)
{
struct orion5x_win_registers *winregs =
(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
/* Window 0: PCIE MEM address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
ORION5X_WIN_ENABLE), &winregs[0].ctrl);
writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
/* Window 1: PCIE IO address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
ORION5X_WIN_ENABLE), &winregs[1].ctrl);
writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
/* Window 2: PCI MEM address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
ORION5X_WIN_ENABLE), &winregs[2].ctrl);
writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
/* Window 3: PCI IO address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
ORION5X_WIN_ENABLE), &winregs[3].ctrl);
writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
/* Window 4: DEV_CS0 address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
ORION5X_WIN_ENABLE), &winregs[4].ctrl);
writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
/* Window 5: DEV_CS1 address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
ORION5X_WIN_ENABLE), &winregs[5].ctrl);
writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
/* Window 6: DEV_CS2 address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
ORION5X_WIN_ENABLE), &winregs[6].ctrl);
writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
/* Window 7: BOOT Memory address space */
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[7].ctrl);
writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
return 0;
}
/*
* Orion5x identification is done through PCIE space.
*/
u32 orion5x_device_id(void)
{
return readl(PCIE_DEV_ID_OFF) >> 16;
}
u32 orion5x_device_rev(void)
{
return readl(PCIE_DEV_REV_OFF) & 0xff;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
/* Display device and revision IDs.
* This function must cover all known device/revision
* combinations, not only the one for which u-boot is
* compiled; this way, one can identify actual HW in
* case of a mismatch.
*/
int print_cpuinfo(void)
{
char dev_str[] = "0x0000";
char rev_str[] = "0x00";
char *dev_name = NULL;
char *rev_name = NULL;
u32 dev = orion5x_device_id();
u32 rev = orion5x_device_rev();
if (dev == MV88F5181_DEV_ID) {
dev_name = "MV88F5181";
if (rev == MV88F5181_REV_B1)
rev_name = "B1";
else if (rev == MV88F5181L_REV_A1) {
dev_name = "MV88F5181L";
rev_name = "A1";
} else if (rev == MV88F5181L_REV_A0) {
dev_name = "MV88F5181L";
rev_name = "A0";
}
} else if (dev == MV88F5182_DEV_ID) {
dev_name = "MV88F5182";
if (rev == MV88F5182_REV_A2)
rev_name = "A2";
} else if (dev == MV88F5281_DEV_ID) {
dev_name = "MV88F5281";
if (rev == MV88F5281_REV_D2)
rev_name = "D2";
else if (rev == MV88F5281_REV_D1)
rev_name = "D1";
else if (rev == MV88F5281_REV_D0)
rev_name = "D0";
} else if (dev == MV88F6183_DEV_ID) {
dev_name = "MV88F6183";
if (rev == MV88F6183_REV_B0)
rev_name = "B0";
}
if (dev_name == NULL) {
sprintf(dev_str, "0x%04x", dev);
dev_name = dev_str;
}
if (rev_name == NULL) {
sprintf(rev_str, "0x%02x", rev);
rev_name = rev_str;
}
printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
/* Enable and invalidate L2 cache in write through mode */
invalidate_l2_cache();
orion5x_config_adr_windows();
return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */
/*
* SOC specific misc init
*/
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
u32 temp;
/*CPU streaming & write allocate */
temp = readfr_extra_feature_reg();
temp &= ~(1 << 28); /* disable wr alloc */
writefr_extra_feature_reg(temp);
temp = readfr_extra_feature_reg();
temp &= ~(1 << 29); /* streaming disabled */
writefr_extra_feature_reg(temp);
/* L2Cache settings */
temp = readfr_extra_feature_reg();
/* Disable L2C pre fetch - Set bit 24 */
temp |= (1 << 24);
/* enable L2C - Set bit 22 */
temp |= (1 << 22);
writefr_extra_feature_reg(temp);
icache_enable();
/* Change reset vector to address 0x0 */
temp = get_cr();
set_cr(temp & ~CR_V);
/* Set CPIOs and MPPs - values provided by board
include file */
writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */

64
arch/arm/cpu/arm926ejs/orion5x/dram.c Normal file
View file

@ -0,0 +1,64 @@
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <config.h>
#include <asm/arch/orion5x.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* orion5x_sdram_bar - reads SDRAM Base Address Register
*/
u32 orion5x_sdram_bar(enum memory_bank bank)
{
struct orion5x_ddr_addr_decode_registers *winregs =
(struct orion5x_ddr_addr_decode_registers *)
ORION5X_CPU_WIN_BASE;
u32 result = 0;
u32 enable = 0x01 & winregs[bank].size;
if ((!enable) || (bank > BANK3))
return 0;
result = winregs[bank].base;
return result;
}
int dram_init(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
gd->bd->bi_dram[i].size = get_ram_size(
(volatile long *) (gd->bd->bi_dram[i].start),
CONFIG_MAX_RAM_BANK_SIZE);
}
return 0;
}

293
arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S Normal file
View file

@ -0,0 +1,293 @@
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <config.h>
#include "asm/arch/orion5x.h"
/*
* Configuration values for SDRAM access setup
*/
#define SDRAM_CONFIG 0x3148400
#define SDRAM_MODE 0x62
#define SDRAM_CONTROL 0x4041000
#define SDRAM_TIME_CTRL_LOW 0x11602220
#define SDRAM_TIME_CTRL_HI 0x40c
#define SDRAM_OPEN_PAGE_EN 0x0
/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
#define SDRAM_BANK0_SIZE 0x3ff0001
#define SDRAM_ADDR_CTRL 0x10
#define SDRAM_OP_NOP 0x05
#define SDRAM_OP_SETMODE 0x03
#define SDRAM_PAD_CTRL_WR_EN 0x80000000
#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
/*
* For Guideline MEM-3 - Drive Strength value
*/
#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
/*
* For Guideline MEM-4 - DQS Reference Delay Tuning
*/
#define MSAR_ARMDDRCLCK_MASK 0x000000f0
#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
#define MSAR_ARMDDRCLCK_333_167 0x00000000
#define MSAR_ARMDDRCLCK_500_167 0x00000030
#define MSAR_ARMDDRCLCK_667_167 0x00000060
#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
#define MSAR_ARMDDRCLCK_400_200 0x00000010
#define MSAR_ARMDDRCLCK_600_200 0x00000050
#define MSAR_ARMDDRCLCK_800_200 0x00000070
#define FTDLL_DDR1_166MHZ 0x0047F001
#define FTDLL_DDR1_200MHZ 0x0044D001
/*
* Low-level init happens right after start.S has switched to SVC32,
* flushed and disabled caches and disabled MMU. We're still running
* from the boot chip select, so the first thing we should do is set
* up RAM for us to relocate into.
*/
.globl lowlevel_init
lowlevel_init:
/* Use 'r4 as the base for internal register accesses */
ldr r4, =ORION5X_REGS_PHY_BASE
/* move internal registers from the default 0xD0000000
* to their intended location, defined by SoC */
ldr r3, =0xD0000000
add r3, r3, #0x20000
str r4, [r3, #0x80]
/* Use R3 as the base for DRAM registers */
add r3, r4, #0x01000
/*DDR SDRAM Initialization Control */
ldr r6, =0x00000001
str r6, [r3, #0x480]
/* Use R3 as the base for PCI registers */
add r3, r4, #0x31000
/* Disable arbiter */
ldr r6, =0x00000030
str r6, [r3, #0xd00]
/* Use R3 as the base for DRAM registers */
add r3, r4, #0x01000
/* set all dram windows to 0 */
mov r6, #0
str r6, [r3, #0x504]
str r6, [r3, #0x50C]
str r6, [r3, #0x514]
str r6, [r3, #0x51C]
/* 1) Configure SDRAM */
ldr r6, =SDRAM_CONFIG
str r6, [r3, #0x400]
/* 2) Set SDRAM Control reg */
ldr r6, =SDRAM_CONTROL
str r6, [r3, #0x404]
/* 3) Write SDRAM address control register */
ldr r6, =SDRAM_ADDR_CTRL
str r6, [r3, #0x410]
/* 4) Write SDRAM bank 0 size register */
ldr r6, =SDRAM_BANK0_SIZE
str r6, [r3, #0x504]
/* keep other banks disabled */
/* 5) Write SDRAM open pages control register */
ldr r6, =SDRAM_OPEN_PAGE_EN
str r6, [r3, #0x414]
/* 6) Write SDRAM timing Low register */
ldr r6, =SDRAM_TIME_CTRL_LOW
str r6, [r3, #0x408]
/* 7) Write SDRAM timing High register */
ldr r6, =SDRAM_TIME_CTRL_HI
str r6, [r3, #0x40C]
/* 8) Write SDRAM mode register */
/* The CPU must not attempt to change the SDRAM Mode register setting */
/* prior to DRAM controller completion of the DRAM initialization */
/* sequence. To guarantee this restriction, it is recommended that */
/* the CPU sets the SDRAM Operation register to NOP command, performs */
/* read polling until the register is back in Normal operation value, */
/* and then sets SDRAM Mode register to its new value. */
/* 8.1 write 'nop' to SDRAM operation */
ldr r6, =SDRAM_OP_NOP
str r6, [r3, #0x418]
/* 8.2 poll SDRAM operation until back in 'normal' mode. */
1:
ldr r6, [r3, #0x418]
cmp r6, #0
bne 1b
/* 8.3 Now its safe to write new value to SDRAM Mode register */
ldr r6, =SDRAM_MODE
str r6, [r3, #0x41C]
/* 8.4 Set new mode */
ldr r6, =SDRAM_OP_SETMODE
str r6, [r3, #0x418]
/* 8.5 poll SDRAM operation until back in 'normal' mode. */
2:
ldr r6, [r3, #0x418]
cmp r6, #0
bne 2b
/* DDR SDRAM Address/Control Pads Calibration */
ldr r6, [r3, #0x4C0]
/* Set Bit [31] to make the register writable */
orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
str r6, [r3, #0x4C0]
bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
/* Get the final N locked value of driving strength [22:17] */
mov r1, r6
mov r1, r1, LSL #9
mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r6, r6, r1
str r6, [r3, #0x4C0]
/* DDR SDRAM Data Pads Calibration */
ldr r6, [r3, #0x4C4]
/* Set Bit [31] to make the register writable */
orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
str r6, [r3, #0x4C4]
bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
/* Get the final N locked value of driving strength [22:17] */
mov r1, r6
mov r1, r1, LSL #9
mov r1, r1, LSR #26
orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r6, r6, r1
str r6, [r3, #0x4C4]
/* Implement Guideline (GL# MEM-3) Drive Strength Value */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
ldr r6, [r3, #0x4C0]
orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
str r6, [r3, #0x4C0]
/* Correct strength and disable writes again */
bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
orr r6, r6, r1
str r6, [r3, #0x4C0]
/* Enable writes to DDR SDRAM Data Pads Calibration register */
ldr r6, [r3, #0x4C4]
orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
str r6, [r3, #0x4C4]
/* Correct strength and disable writes again */
bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
orr r6, r6, r1
str r6, [r3, #0x4C4]
/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
/* Get the "sample on reset" register for the DDR frequancy */
ldr r3, =0x10000
ldr r6, [r3, #0x010]
ldr r1, =MSAR_ARMDDRCLCK_MASK
and r1, r6, r1
ldr r6, =FTDLL_DDR1_166MHZ
cmp r1, #MSAR_ARMDDRCLCK_333_167
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_500_167
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_667_167
beq 3f
ldr r6, =FTDLL_DDR1_200MHZ
cmp r1, #MSAR_ARMDDRCLCK_400_200_1
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_400_200
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_600_200
beq 3f
cmp r1, #MSAR_ARMDDRCLCK_800_200
beq 3f
ldr r6, =0
3:
/* Use R3 as the base for DRAM registers */
add r3, r4, #0x01000
ldr r2, [r3, #0x484]
orr r2, r2, r6
str r2, [r3, #0x484]
/* Return to U-boot via saved link register */
mov pc, lr

181
arch/arm/cpu/arm926ejs/orion5x/timer.c Normal file
View file

@ -0,0 +1,181 @@
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
*
* Based on original Kirkwood support which is
* Copyright (C) Marvell International Ltd. and its affiliates
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/arch/orion5x.h>
#define UBOOT_CNTR 0 /* counter to use for uboot timer */
/* Timer reload and current value registers */
struct orion5x_tmr_val {
u32 reload; /* Timer reload reg */
u32 val; /* Timer value reg */
};
/* Timer registers */
struct orion5x_tmr_registers {
u32 ctrl; /* Timer control reg */
u32 pad[3];
struct orion5x_tmr_val tmr[2];
u32 wdt_reload;
u32 wdt_val;
};
struct orion5x_tmr_registers *orion5x_tmr_regs =
(struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
/*
* ARM Timers Registers Map
*/
#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
/*
* ARM Timers Control Register
* CPU_TIMERS_CTRL_REG (CTCR)
*/
#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
/*
* ARM Timer\Watchdog Reload Register
* CNTMR_RELOAD_REG (TRR)
*/
#define TRG_ARM_TIMER_REL_OFFS 0
#define TRG_ARM_TIMER_REL_MASK 0xffffffff
/*
* ARM Timer\Watchdog Register
* CNTMR_VAL_REG (TVRG)
*/
#define TVR_ARM_TIMER_OFFS 0
#define TVR_ARM_TIMER_MASK 0xffffffff
#define TVR_ARM_TIMER_MAX 0xffffffff
#define TIMER_LOAD_VAL 0xffffffff
static inline ulong read_timer(void)
{
return readl(CNTMR_VAL_REG(UBOOT_CNTR))
/ (CONFIG_SYS_TCLK / 1000);
}
static ulong timestamp;
static ulong lastdec;
void reset_timer_masked(void)
{
/* reset time */
lastdec = read_timer();
timestamp = 0;
}
ulong get_timer_masked(void)
{
ulong now = read_timer();
if (lastdec >= now) {
/* normal mode */
timestamp += lastdec - now;
} else {
/* we have an overflow ... */
timestamp += lastdec +
(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
}
lastdec = now;
return timestamp;
}
void reset_timer(void)
{
reset_timer_masked();
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
timestamp = t;
}
static inline ulong uboot_cntr_val(void)
{
return readl(CNTMR_VAL_REG(UBOOT_CNTR));
}
void __udelay(unsigned long usec)
{
uint current;
ulong delayticks;
current = uboot_cntr_val();
delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
if (current < delayticks) {
delayticks -= current;
while (uboot_cntr_val() < current)
;
while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
;
} else {
while (uboot_cntr_val() > (current - delayticks))
;
}
}
/*
* init the counter
*/
int timer_init(void)
{
unsigned int cntmrctrl;
/* load value into timer */
writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
/* enable timer in auto reload mode */
cntmrctrl = readl(CNTMR_CTRL_REG);
cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
writel(cntmrctrl, CNTMR_CTRL_REG);
/* init the timestamp and lastdec value */
reset_timer_masked();
return 0;
}

2
arch/arm/cpu/arm926ejs/start.S
View file

@ -196,7 +196,7 @@ stack_setup:
#endif
#endif /* CONFIG_PRELOADER */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, r0, #7 /* 8-byte align stack for ABI compliance */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/arm946es/start.S
View file

@ -163,6 +163,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

2
arch/arm/cpu/arm_cortexa8/mx51/clock.c
View file

@ -269,7 +269,7 @@ u32 imx_get_fecclk(void)
/*
* Dump some core clockes.
*/
int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;

2
arch/arm/cpu/arm_cortexa8/omap3/board.c
View file

@ -282,7 +282,7 @@ void abort(void)
/******************************************************************************
* OMAP3 specific command to switch between NAND HW and SW ecc
*****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2)
goto usage;

8
arch/arm/cpu/arm_cortexa8/omap3/cache.S
View file

@ -130,7 +130,7 @@ finished_inval:
l2_cache_enable:
push {r0, r1, r2, lr}
stmfd r13!, {r0, r1, r2, lr}
@ ES2 onwards we can disable/enable L2 ourselves
bl get_cpu_rev
cmp r0, #CPU_3XX_ES20
@ -157,11 +157,11 @@ l2_cache_enable_EARLIER_THAN_ES2:
mov ip, r3
str r3, [sp, #4]
l2_cache_enable_END:
pop {r1, r2, r3, pc}
ldmfd r13!, {r1, r2, r3, pc}
l2_cache_disable:
push {r0, r1, r2, lr}
stmfd r13!, {r0, r1, r2, lr}
@ ES2 onwards we can disable/enable L2 ourselves
bl get_cpu_rev
cmp r0, #CPU_3XX_ES20
@ -188,4 +188,4 @@ l2_cache_disable_EARLIER_THAN_ES2:
mov ip, r3
str r3, [sp, #4]
l2_cache_disable_END:
pop {r1, r2, r3, pc}
ldmfd r13!, {r1, r2, r3, pc}

2
arch/arm/cpu/arm_cortexa8/start.S
View file

@ -164,7 +164,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 @ leave 3 words for abort-stack
and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
bic sp, sp, #7 @ 8-byte alignment for ABI compliance
/* Clear BSS (if any). Is below tx (watch load addr - need space) */
clear_bss:

1
arch/arm/cpu/arm_intcm/start.S
View file

@ -161,6 +161,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/ixp/start.S
View file

@ -289,6 +289,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/lh7a40x/start.S
View file

@ -178,6 +178,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/pxa/start.S
View file

@ -141,6 +141,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

1
arch/arm/cpu/s3c44b0/start.S
View file

@ -163,6 +163,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr pc, _start_armboot

1
arch/arm/cpu/sa1100/start.S
View file

@ -153,6 +153,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */

14
arch/arm/include/asm/arch-at91/at91_pmc.h
View file

@ -35,13 +35,15 @@ typedef struct at91_pmc {
u32 pcer; /* 0x10 Peripheral Clock Enable Register */
u32 pcdr; /* 0x14 Peripheral Clock Disable Register */
u32 pcsr; /* 0x18 Peripheral Clock Status Register */
u32 reserved1;
u32 uckr; /* 0x1C UTMI Clock Register */
u32 mor; /* 0x20 Main Oscilator Register */
u32 mcfr; /* 0x24 Main Clock Frequency Register */
u32 pllar; /* 0x28 PLL A Register */
u32 pllbr; /* 0x2C PLL B Register */
u32 mckr; /* 0x30 Master Clock Register */
u32 reserved2[3];
u32 reserved1;
u32 usb; /* 0x38 USB Clock Register */
u32 reserved2;
u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */
u32 reserved3[4];
u32 ier; /* 0x60 Interrupt Enable Register */
@ -198,6 +200,14 @@ typedef struct at91_pmc {
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */
#endif
#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */

2
arch/arm/include/asm/arch-davinci/emac_defs.h
View file

@ -85,7 +85,7 @@
#endif
/* PHY mask - set only those phy number bits where phy is/can be connected */
#define EMAC_MDIO_PHY_NUM 1
#define EMAC_MDIO_PHY_NUM CONFIG_EMAC_MDIO_PHY_NUM
#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM)
/* Ethernet Min/Max packet size */

1
arch/arm/include/asm/arch-davinci/hardware.h
View file

@ -398,6 +398,7 @@ struct davinci_syscfg_regs {
#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)

203
arch/arm/include/asm/arch-orion5x/cpu.h Normal file
View file

@ -0,0 +1,203 @@
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
*
* Based on original Kirorion5x_ood support which is
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _ORION5X_CPU_H
#define _ORION5X_CPU_H
#include <asm/system.h>
#ifndef __ASSEMBLY__
#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
enum memory_bank {
BANK0,
BANK1,
BANK2,
BANK3
};
enum orion5x_cpu_winen {
ORION5X_WIN_DISABLE,
ORION5X_WIN_ENABLE
};
enum orion5x_cpu_target {
ORION5X_TARGET_DRAM = 0,
ORION5X_TARGET_DEVICE = 1,
ORION5X_TARGET_PCI = 3,
ORION5X_TARGET_PCIE = 4,
ORION5X_TARGET_SASRAM = 9
};
enum orion5x_cpu_attrib {
ORION5X_ATTR_DRAM_CS0 = 0x0e,
ORION5X_ATTR_DRAM_CS1 = 0x0d,
ORION5X_ATTR_DRAM_CS2 = 0x0b,
ORION5X_ATTR_DRAM_CS3 = 0x07,
ORION5X_ATTR_PCI_MEM = 0x59,
ORION5X_ATTR_PCI_IO = 0x51,
ORION5X_ATTR_PCIE_MEM = 0x59,
ORION5X_ATTR_PCIE_IO = 0x51,
ORION5X_ATTR_SASRAM = 0x00,
ORION5X_ATTR_DEV_CS0 = 0x1e,
ORION5X_ATTR_DEV_CS1 = 0x1d,
ORION5X_ATTR_DEV_CS2 = 0x1b,
ORION5X_ATTR_BOOTROM = 0x0f
};
/*
* Default Device Address MAP BAR values
*/
#define ORION5X_DEFADR_PCIE_MEM 0x90000000
#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000
#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0
#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024)
#define ORION5X_DEFADR_PCIE_IO 0xf0000000
#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000
#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0
#define ORION5X_DEFSZ_PCIE_IO (64*1024)
#define ORION5X_DEFADR_PCI_MEM 0x98000000
#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024)
#define ORION5X_DEFADR_PCI_IO 0xf0100000
#define ORION5X_DEFSZ_PCI_IO (64*1024)
#define ORION5X_DEFADR_DEV_CS0 0xfa000000
#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024)
#define ORION5X_DEFADR_DEV_CS1 0xf8000000
#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024)
#define ORION5X_DEFADR_DEV_CS2 0xfa800000
#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
#define ORION5X_DEFADR_BOOTROM 0xFFF80000
#define ORION5X_DEFSZ_BOOTROM (512*1024)
/*
* PCIE registers are used for SoC device ID and revision
*/
#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/*
* The following definitions are intended for identifying
* the real device and revision on which u-boot is running
* even if it was compiled only for a specific one. Thus,
* these constants must not be considered chip-specific.
*/
/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
#define MV88F5181_DEV_ID 0x5181
#define MV88F5181_REV_B1 3
#define MV88F5181L_REV_A0 8
#define MV88F5181L_REV_A1 9
/* Orion-NAS (88F5182) */
#define MV88F5182_DEV_ID 0x5182
#define MV88F5182_REV_A2 2
/* Orion-2 (88F5281) */
#define MV88F5281_DEV_ID 0x5281
#define MV88F5281_REV_D0 4
#define MV88F5281_REV_D1 5
#define MV88F5281_REV_D2 6
/* Orion-1-90 (88F6183) */
#define MV88F6183_DEV_ID 0x6183
#define MV88F6183_REV_B0 3
/*
* read feroceon core extra feature register
* using co-proc instruction
*/
static inline unsigned int readfr_extra_feature_reg(void)
{
unsigned int val;
asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
(val) : : "cc");
return val;
}
/*
* write feroceon core extra feature register
* using co-proc instruction
*/
static inline void writefr_extra_feature_reg(unsigned int val)
{
asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
(val) : "cc");
isb();
}
/*
* AHB to Mbus Bridge Registers
* Source: 88F5182 User Manual, Appendix A, section A.4
* Note: only windows 0 and 1 have remap capability.
*/
struct orion5x_win_registers {
u32 ctrl;
u32 base;
u32 remap_lo;
u32 remap_hi;
};
/*
* CPU control and status Registers
* Source: 88F5182 User Manual, Appendix A, section A.4
*/
struct orion5x_cpu_registers {
u32 config; /*0x20100 */
u32 ctrl_stat; /*0x20104 */
u32 rstoutn_mask; /* 0x20108 */
u32 sys_soft_rst; /* 0x2010C */
u32 ahb_mbus_cause_irq; /* 0x20110 */
u32 ahb_mbus_mask_irq; /* 0x20114 */
};
/*
* DDR SDRAM Controller Address Decode Registers
* Source: 88F5182 User Manual, Appendix A, section A.5.1
*/
struct orion5x_ddr_addr_decode_registers {
u32 base;
u32 size;
};
/*
* functions
*/
void reset_cpu(unsigned long ignored);
u32 orion5x_device_id(void);
u32 orion5x_device_rev(void);
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
#endif /* __ASSEMBLY__ */
#endif /* _ORION5X_CPU_H */

40
arch/arm/include/asm/arch-orion5x/mv88f5182.h Normal file
View file

@ -0,0 +1,40 @@
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
*
* Based on original Kirkwood 88F6182 support which is
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Header file for Feroceon CPU core 88F5182 SOC.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_88F5182_H
#define _CONFIG_88F5182_H
/* SOC specific definitions */
#define F88F5182_REGS_PHYS_BASE 0xf1000000
#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE
/* TCLK Core Clock defination */
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_88F5182_H */

69
arch/arm/include/asm/arch-orion5x/orion5x.h Normal file
View file

@ -0,0 +1,69 @@
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Header file for Marvell's Orion SoC with Feroceon CPU core.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _ASM_ARCH_ORION5X_H
#define _ASM_ARCH_ORION5X_H
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <asm/io.h>
#endif /* __ASSEMBLY__ */
#if defined(CONFIG_FEROCEON)
#include <asm/arch/cpu.h>
/* SOC specific definations */
#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
/* Documented registers */
#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000))
#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000))
#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
/* include here SoC variants. 5181, 5281, 6183 should go here when
adding support for them, and this comment should then be updated. */
#if defined(CONFIG_88F5182)
#include <asm/arch/mv88f5182.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_FEROCEON */
#endif /* _ASM_ARCH_ORION5X_H */

25
arch/arm/include/asm/arch-pxa/pxa-regs.h
View file

@ -992,10 +992,6 @@ typedef void (*ExcpHndlr) (void) ;
#define UHCHIE __REG(0x4C000068)
#define UHCHIT __REG(0x4C00006C)
#if defined(CONFIG_CPU_MONAHANS)
#define UP2OCR __REG(0x40600020)
#endif
#define UHCHR_FSBIR (1<<0)
#define UHCHR_FHR (1<<1)
#define UHCHR_CGR (1<<2)
@ -1015,6 +1011,24 @@ typedef void (*ExcpHndlr) (void) ;
#define UHCHIE_HBAIE (1<<8)
#define UHCHIE_RWIE (1<<7)
#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#define UP2OCR __REG(0x40600020)
#endif
#define UP2OCR_HXOE (1<<17)
#define UP2OCR_HXS (1<<16)
#define UP2OCR_IDON (1<<10)
#define UP2OCR_EXSUS (1<<9)
#define UP2OCR_EXSP (1<<8)
#define UP2OCR_DMSTATE (1<<7)
#define UP2OCR_VPM (1<<6)
#define UP2OCR_DPSTATE (1<<5)
#define UP2OCR_DPPUE (1<<4)
#define UP2OCR_DMPDE (1<<3)
#define UP2OCR_DPPDE (1<<2)
#define UP2OCR_CPVPE (1<<1)
#define UP2OCR_CPVEN (1<<0)
#endif
/*
@ -2407,6 +2421,9 @@ typedef void (*ExcpHndlr) (void) ;
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */
#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */
#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */

14
arch/arm/include/asm/io.h
View file

@ -248,13 +248,13 @@ extern void __iounmap(void *addr);
* iomem_to_phys(off)
*/
#ifdef iomem_valid_addr
#define __arch_ioremap(off,sz,nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off),_size,0); \
_ret; \
#define __arch_ioremap(off,sz,nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off),_size,nocache); \
_ret; \
})
#define __arch_iounmap __iounmap

45
arch/arm/lib/bootm.c
View file

@ -33,9 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
defined (CONFIG_CMDLINE_TAG) || \
defined (CONFIG_INITRD_TAG) || \
defined (CONFIG_SERIAL_TAG) || \
defined (CONFIG_REVISION_TAG) || \
defined (CONFIG_VFD) || \
defined (CONFIG_LCD)
defined (CONFIG_REVISION_TAG)
static void setup_start_tag (bd_t *bd);
# ifdef CONFIG_SETUP_MEMORY_TAGS
@ -49,14 +47,10 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start,
# endif
static void setup_end_tag (bd_t *bd);
# if defined (CONFIG_VFD) || defined (CONFIG_LCD)
static void setup_videolfb_tag (gd_t *gd);
# endif
static struct tag *params;
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
bd_t *bd = gd->bd;
char *s;
@ -87,9 +81,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
defined (CONFIG_CMDLINE_TAG) || \
defined (CONFIG_INITRD_TAG) || \
defined (CONFIG_SERIAL_TAG) || \
defined (CONFIG_REVISION_TAG) || \
defined (CONFIG_LCD) || \
defined (CONFIG_VFD)
defined (CONFIG_REVISION_TAG)
setup_start_tag (bd);
#ifdef CONFIG_SERIAL_TAG
setup_serial_tag (&params);
@ -106,9 +98,6 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
#ifdef CONFIG_INITRD_TAG
if (images->rd_start && images->rd_end)
setup_initrd_tag (bd, images->rd_start, images->rd_end);
#endif
#if defined (CONFIG_VFD) || defined (CONFIG_LCD)
setup_videolfb_tag ((gd_t *) gd);
#endif
setup_end_tag (bd);
#endif
@ -136,9 +125,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
defined (CONFIG_CMDLINE_TAG) || \
defined (CONFIG_INITRD_TAG) || \
defined (CONFIG_SERIAL_TAG) || \
defined (CONFIG_REVISION_TAG) || \
defined (CONFIG_LCD) || \
defined (CONFIG_VFD)
defined (CONFIG_REVISION_TAG)
static void setup_start_tag (bd_t *bd)
{
params = (struct tag *) bd->bi_boot_params;
@ -214,30 +201,6 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end)
}
#endif /* CONFIG_INITRD_TAG */
#if defined (CONFIG_VFD) || defined (CONFIG_LCD)
extern ulong calc_fbsize (void);
static void setup_videolfb_tag (gd_t *gd)
{
/* An ATAG_VIDEOLFB node tells the kernel where and how large
* the framebuffer for video was allocated (among other things).
* Note that a _physical_ address is passed !
*
* We only use it to pass the address and size, the other entries
* in the tag_videolfb are not of interest.
*/
params->hdr.tag = ATAG_VIDEOLFB;
params->hdr.size = tag_size (tag_videolfb);
params->u.videolfb.lfb_base = (u32) gd->fb_base;
/* Fb size is calculated according to parameters for our panel
*/
params->u.videolfb.lfb_size = calc_fbsize();
params = tag_next (params);
}
#endif /* CONFIG_VFD || CONFIG_LCD */
#ifdef CONFIG_SERIAL_TAG
void setup_serial_tag (struct tag **tmp)
{

2
arch/arm/lib/reset.c
View file

@ -39,7 +39,7 @@
#include <common.h>
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
puts ("resetting ...\n");

2
arch/avr32/cpu/cpu.c
View file

@ -76,7 +76,7 @@ void prepare_to_boot(void)
"sync 0" : : "r"(0) : "memory");
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* This will reset the CPU core, caches, MMU and all internal busses */
__builtin_mtdr(8, 1 << 13); /* set DC:DBE */

7
arch/avr32/cpu/start.S
View file

@ -27,9 +27,10 @@
#define SYSREG_MMUCR_S_OFFSET 4
#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \
| SYSREG_BIT(FE) | SYSREG_BIT(RE) \
| SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
/* due to errata (unreliable branch folding) clear FE bit explicitly */
#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE) \
| SYSREG_BIT(RE) | SYSREG_BIT(IBE) \
| SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))
/*
* To save some space, we use the same entry point for

1
arch/avr32/include/asm/unaligned.h Normal file
View file

@ -0,0 +1 @@
#include <asm-generic/unaligned.h>

5
arch/avr32/lib/board.c
View file

@ -115,8 +115,9 @@ static int init_baudrate(void)
static int display_banner (void)
{
printf ("\n\n%s\n\n", version_string);
printf ("U-Boot code: %p -> %p data: %p -> %p\n",
_text, _etext, _data, _end);
printf ("U-Boot code: %08lx -> %08lx data: %08lx -> %08lx\n",
(unsigned long)_text, (unsigned long)_etext,
(unsigned long)_data, (unsigned long)_end);
return 0;
}

2
arch/avr32/lib/bootm.c
View file

@ -171,7 +171,7 @@ static void setup_end_tag(struct tag *params)
params->hdr.size = 0;
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
void (*theKernel)(int magic, void *tagtable);
struct tag *params, *params_start;

2
arch/blackfin/cpu/bootrom-asm-offsets.c.in
View file

@ -9,4 +9,4 @@
#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m))
int main(int argc, char *argv[])
int main(int argc, char * const argv[])

2
arch/blackfin/cpu/reset.c
View file

@ -99,7 +99,7 @@ void bfin_reset_or_hang(void)
#endif
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bfin_reset_trampoline();
return 0;

2
arch/blackfin/lib/boot.c
View file

@ -33,7 +33,7 @@ static char *make_command_line(void)
extern ulong bfin_poweron_retx;
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
int (*appl) (char *cmdline);
char *cmdline;

4
arch/blackfin/lib/cmd_cache_dump.c
View file

@ -25,7 +25,7 @@ static int check_limit(const char *type, size_t start_limit, size_t end_limit, s
return 1;
}
int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int cache_status = icache_status();
@ -97,7 +97,7 @@ U_BOOT_CMD(icache_dump, 4, 0, do_icache_dump,
"icache_dump - dump current instruction cache\n",
"[way] [subbank] [set]");
int do_dcache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_dcache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 way, bank, subbank, set;
u32 status, addr;

2
arch/blackfin/lib/kgdb.c
View file

@ -417,7 +417,7 @@ void kgdb_putregs(struct pt_regs *regs, char *buf, int length)
}
void kgdb_breakpoint(int argc, char *argv[])
void kgdb_breakpoint(int argc, char * const argv[])
{
asm volatile ("excpt 0x1\n");
}

2
arch/i386/cpu/cpu.c
View file

@ -56,7 +56,7 @@ int cpu_init_r(void)
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf ("resetting ...\n");
udelay(50000); /* wait 50 ms */

2
arch/i386/lib/board.c
View file

@ -431,7 +431,7 @@ void hang (void)
for (;;);
}
unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[])
unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char * const argv[])
{
/*
* x86 does not use a dedicated register to pass the pointer

2
arch/i386/lib/bootm.c
View file

@ -29,7 +29,7 @@
#include <asm/zimage.h>
/*cmd_boot.c*/
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
void *base_ptr;
ulong os_data, os_len;

2
arch/i386/lib/interrupts.c
View file

@ -136,7 +136,7 @@ void do_irq(int hw_irq)
}
#if defined(CONFIG_CMD_IRQ)
int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int irq;

2
arch/i386/lib/zimage.c
View file

@ -245,7 +245,7 @@ void boot_zimage(void *setup_base)
enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, &regs, &regs);
}
int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
void *base_ptr;
void *bzImage_addr;

2
arch/m68k/cpu/mcf5227x/cpu.c
View file

@ -33,7 +33,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);

2
arch/m68k/cpu/mcf523x/cpu.c
View file

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;

14
arch/m68k/cpu/mcf52x2/cpu.c
View file

@ -38,7 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M5208
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
@ -142,7 +142,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
/* Call the board specific reset actions first. */
if(board_reset) {
@ -177,7 +177,7 @@ int watchdog_init(void)
#endif
#ifdef CONFIG_M5272
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
@ -257,7 +257,7 @@ int watchdog_init(void)
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5275
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
@ -337,7 +337,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
@ -354,7 +354,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(MCFSIM_SYPCR, 0xc0);
@ -384,7 +384,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(SIM_SYPCR, 0xc0);

2
arch/m68k/cpu/mcf532x/cpu.c
View file

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);

2
arch/m68k/cpu/mcf5445x/cpu.c
View file

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);

31
arch/m68k/cpu/mcf5445x/cpu_init.c
View file

@ -185,8 +185,19 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 |
GPIO_PAR_FECI2C_MDIO0_MDIO0);
else
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC1_MDC1 |
GPIO_PAR_FECI2C_MDIO1_MDIO1);
#else
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
@ -196,10 +207,19 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
#ifdef CONFIG_SYS_FEC_FULL_MII
gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII;
#else
gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
else
#endif
} else {
#ifdef CONFIG_SYS_FEC_FULL_MII
gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII;
#else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
#endif
}
}
return 0;
}
@ -238,6 +258,10 @@ int cfspi_claim_bus(uint bus, uint cs)
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
break;
case 3:
gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3;
break;
case 5:
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
@ -264,6 +288,9 @@ void cfspi_release_bus(uint bus, uint cs)
case 2:
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
break;
case 3:
gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
break;
case 5:
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
break;

2
arch/m68k/cpu/mcf547x_8x/cpu.c
View file

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);

1
arch/m68k/include/asm/m5445x.h
View file

@ -314,6 +314,7 @@
#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3)
#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
#define GPIO_PAR_DMA_DACK0_PCS3 (0x08)
#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)

2
arch/m68k/lib/bootm.c
View file

@ -64,7 +64,7 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
ulong rd_len;
ulong initrd_start, initrd_end;

4
arch/microblaze/cpu/interrupts.c
View file

@ -173,7 +173,7 @@ void interrupt_handler (void)
#if defined(CONFIG_CMD_IRQ)
#ifdef CONFIG_SYS_INTC_0
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
int i;
struct irq_action *act = vecs;
@ -193,7 +193,7 @@ int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
return (0);
}
#else
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
puts ("Undefined interrupt controller\n");
}

2
arch/microblaze/lib/bootm.c
View file

@ -32,7 +32,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
/* First parameter is mapped to $r5 for kernel boot args */
void (*theKernel) (char *, ulong, ulong);

2
arch/mips/cpu/cpu.c
View file

@ -42,7 +42,7 @@ void __attribute__((weak)) _machine_restart(void)
{
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
_machine_restart();

2
arch/mips/lib/bootm.c
View file

@ -43,7 +43,7 @@ static int linux_env_idx;
static void linux_params_init (ulong start, char * commandline);
static void linux_env_set (char * env_name, char * env_val);
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
void (*theKernel) (int, char **, char **, int *);
char *commandline = getenv ("bootargs");

2
arch/mips/lib/bootm_qemu_mips.c
View file

@ -29,7 +29,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
void (*theKernel) (int, char **, char **, int *);
char *bootargs = getenv ("bootargs");

29
arch/nios/config.mk
View file

@ -1,29 +0,0 @@
#
# (C) Copyright 2003
# Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CROSS_COMPILE ?= nios-elf-
STANDALONE_LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32
PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs

695
arch/nios/cpu/asmi.c
View file

@ -1,695 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_NIOS_ASMI)
#include <command.h>
#include <nios-io.h>
#if !defined(CONFIG_SYS_NIOS_ASMIBASE)
#error "*** CONFIG_SYS_NIOS_ASMIBASE not defined ***"
#endif
/*-----------------------------------------------------------------------*/
#define SHORT_HELP\
"asmi - read/write Cyclone ASMI configuration device.\n"
#define LONG_HELP\
"\n"\
"asmi erase start [end]\n"\
" - erase sector start or sectors start through end.\n"\
"asmi info\n"\
" - display ASMI device information.\n"\
"asmi protect on | off\n"\
" - turn device protection on or off.\n"\
"asmi read addr offset count\n"\
" - read count bytes from offset to addr.\n"\
"asmi write addr offset count\n"\
" - write count bytes to offset from addr.\n"\
"asmi verify addr offset count\n"\
" - verify count bytes at offset from addr."
/*-----------------------------------------------------------------------*/
/* Operation codes for serial configuration devices
*/
#define ASMI_WRITE_ENA 0x06 /* Write enable */
#define ASMI_WRITE_DIS 0x04 /* Write disable */
#define ASMI_READ_STAT 0x05 /* Read status */
#define ASMI_READ_BYTES 0x03 /* Read bytes */
#define ASMI_READ_ID 0xab /* Read silicon id */
#define ASMI_WRITE_STAT 0x01 /* Write status */
#define ASMI_WRITE_BYTES 0x02 /* Write bytes */
#define ASMI_ERASE_BULK 0xc7 /* Erase entire device */
#define ASMI_ERASE_SECT 0xd8 /* Erase sector */
/* Device status register bits
*/
#define ASMI_STATUS_WIP (1<<0) /* Write in progress */
#define ASMI_STATUS_WEL (1<<1) /* Write enable latch */
static nios_asmi_t *asmi = (nios_asmi_t *)CONFIG_SYS_NIOS_ASMIBASE;
/***********************************************************************
* Device access
***********************************************************************/
static void asmi_cs (int assert)
{
if (assert) {
asmi->control |= NIOS_ASMI_SSO;
} else {
/* Let all bits shift out */
while ((asmi->status & NIOS_ASMI_TMT) == 0)
;
asmi->control &= ~NIOS_ASMI_SSO;
}
}
static void asmi_tx (unsigned char c)
{
while ((asmi->status & NIOS_ASMI_TRDY) == 0)
;
asmi->txdata = c;
}
static int asmi_rx (void)
{
while ((asmi->status & NIOS_ASMI_RRDY) == 0)
;
return (asmi->rxdata);
}
static unsigned char bitrev[] = {
0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e,
0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
};
static unsigned char asmi_bitrev( unsigned char c )
{
unsigned char val;
val = bitrev[c>>4];
val |= bitrev[c & 0x0f]<<4;
return (val);
}
static void asmi_rcv (unsigned char *dst, int len)
{
while (len--) {
asmi_tx (0);
*dst++ = asmi_rx ();
}
}
static void asmi_rrcv (unsigned char *dst, int len)
{
while (len--) {
asmi_tx (0);
*dst++ = asmi_bitrev (asmi_rx ());
}
}
static void asmi_snd (unsigned char *src, int len)
{
while (len--) {
asmi_tx (*src++);
asmi_rx ();
}
}
static void asmi_rsnd (unsigned char *src, int len)
{
while (len--) {
asmi_tx (asmi_bitrev (*src++));
asmi_rx ();
}
}
static void asmi_wr_enable (void)
{
asmi_cs (1);
asmi_tx (ASMI_WRITE_ENA);
asmi_rx ();
asmi_cs (0);
}
static unsigned char asmi_status_rd (void)
{
unsigned char status;
asmi_cs (1);
asmi_tx (ASMI_READ_STAT);
asmi_rx ();
asmi_tx (0);
status = asmi_rx ();
asmi_cs (0);
return (status);
}
static void asmi_status_wr (unsigned char status)
{
asmi_wr_enable ();
asmi_cs (1);
asmi_tx (ASMI_WRITE_STAT);
asmi_rx ();
asmi_tx (status);
asmi_rx ();
asmi_cs (0);
return;
}
/***********************************************************************
* Device information
***********************************************************************/
typedef struct asmi_devinfo_t {
const char *name; /* Device name */
unsigned char id; /* Device silicon id */
unsigned char size; /* Total size log2(bytes)*/
unsigned char num_sects; /* Number of sectors */
unsigned char sz_sect; /* Sector size log2(bytes) */
unsigned char sz_page; /* Page size log2(bytes) */
unsigned char prot_mask; /* Protection mask */
}asmi_devinfo_t;
static struct asmi_devinfo_t devinfo[] = {
{ "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c },
{ "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c },
{ 0, 0, 0, 0, 0, 0 }
};
static asmi_devinfo_t *asmi_dev_find (void)
{
unsigned char buf[4];
unsigned char id;
int i;
struct asmi_devinfo_t *dev = NULL;
/* Read silicon id requires 3 "dummy bytes" before it's put
* on the wire.
*/
buf[0] = ASMI_READ_ID;
buf[1] = 0;
buf[2] = 0;
buf[3] = 0;
asmi_cs (1);
asmi_snd (buf,4);
asmi_rcv (buf,1);
asmi_cs (0);
id = buf[0];
/* Find the info struct */
i = 0;
while (devinfo[i].name) {
if (id == devinfo[i].id) {
dev = &devinfo[i];
break;
}
i++;
}
return (dev);
}
/***********************************************************************
* Misc Utilities
***********************************************************************/
static unsigned asmi_cfgsz (void)
{
unsigned sz = 0;
unsigned char buf[128];
unsigned char *p;
/* Read in the first 128 bytes of the device */
buf[0] = ASMI_READ_BYTES;
buf[1] = 0;
buf[2] = 0;
buf[3] = 0;
asmi_cs (1);
asmi_snd (buf,4);
asmi_rrcv (buf, sizeof(buf));
asmi_cs (0);
/* Search for the starting 0x6a which is followed by the
* 4-byte 'register' and 4-byte bit-count.
*/
p = buf;
while (p < buf + sizeof(buf)-8) {
if ( *p == 0x6a ) {
/* Point to bit count and extract */
p += 5;
sz = *p++;
sz |= *p++ << 8;
sz |= *p++ << 16;
sz |= *p++ << 24;
/* Convert to byte count */
sz += 7;
sz >>= 3;
} else if (*p == 0xff) {
/* 0xff is ok ... just skip */
p++;
continue;
} else {
/* Not 0xff or 0x6a ... something's not
* right ... report 'unknown' (sz=0).
*/
break;
}
}
return (sz);
}
static int asmi_erase (unsigned start, unsigned end)
{
unsigned off, sectsz;
unsigned char buf[4];
struct asmi_devinfo_t *dev = asmi_dev_find ();
if (!dev || (start>end))
return (-1);
/* Erase the requested sectors. An address is required
* that lies within the requested sector -- we'll just
* use the first address in the sector.
*/
printf ("asmi erasing sector %d ", start);
if (start != end)
printf ("to %d ", end);
sectsz = (1 << dev->sz_sect);
while (start <= end) {
off = start * sectsz;
start++;
buf[0] = ASMI_ERASE_SECT;
buf[1] = off >> 16;
buf[2] = off >> 8;
buf[3] = off;
asmi_wr_enable ();
asmi_cs (1);
asmi_snd (buf,4);
asmi_cs (0);
printf ("."); /* Some user feedback */
/* Wait for erase to complete */
while (asmi_status_rd() & ASMI_STATUS_WIP)
;
}
printf (" done.\n");
return (0);
}
static int asmi_read (ulong addr, ulong off, ulong cnt)
{
unsigned char buf[4];
buf[0] = ASMI_READ_BYTES;
buf[1] = off >> 16;
buf[2] = off >> 8;
buf[3] = off;
asmi_cs (1);
asmi_snd (buf,4);
asmi_rrcv ((unsigned char *)addr, cnt);
asmi_cs (0);
return (0);
}
static
int asmi_write (ulong addr, ulong off, ulong cnt)
{
ulong wrcnt;
unsigned pgsz;
unsigned char buf[4];
struct asmi_devinfo_t *dev = asmi_dev_find ();
if (!dev)
return (-1);
pgsz = (1<<dev->sz_page);
while (cnt) {
if (off % pgsz)
wrcnt = pgsz - (off % pgsz);
else
wrcnt = pgsz;
wrcnt = (wrcnt > cnt) ? cnt : wrcnt;
buf[0] = ASMI_WRITE_BYTES;
buf[1] = off >> 16;
buf[2] = off >> 8;
buf[3] = off;
asmi_wr_enable ();
asmi_cs (1);
asmi_snd (buf,4);
asmi_rsnd ((unsigned char *)addr, wrcnt);
asmi_cs (0);
/* Wait for write to complete */
while (asmi_status_rd() & ASMI_STATUS_WIP)
;
cnt -= wrcnt;
off += wrcnt;
addr += wrcnt;
}
return (0);
}
static
int asmi_verify (ulong addr, ulong off, ulong cnt, ulong *err)
{
ulong rdcnt;
unsigned char buf[256];
unsigned char *start,*end;
int i;
start = end = (unsigned char *)addr;
while (cnt) {
rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt;
asmi_read ((ulong)buf, off, rdcnt);
for (i=0; i<rdcnt; i++) {
if (*end != buf[i]) {
*err = end - start;
return(-1);
}
end++;
}
cnt -= rdcnt;
off += rdcnt;
}
return (0);
}
static int asmi_sect_erased (int sect, unsigned *offset,
struct asmi_devinfo_t *dev)
{
unsigned char buf[128];
unsigned off, end;
unsigned sectsz;
int i;
sectsz = (1 << dev->sz_sect);
off = sectsz * sect;
end = off + sectsz;
while (off < end) {
asmi_read ((ulong)buf, off, sizeof(buf));
for (i=0; i < sizeof(buf); i++) {
if (buf[i] != 0xff) {
*offset = off + i;
return (0);
}
}
off += sizeof(buf);
}
return (1);
}
/***********************************************************************
* Commands
***********************************************************************/
static
void do_asmi_info (struct asmi_devinfo_t *dev, int argc, char *argv[])
{
int i;
unsigned char stat;
unsigned tmp;
int erased;
/* Basic device info */
printf ("%s: %d kbytes (%d sectors x %d kbytes,"
" %d bytes/page)\n",
dev->name, 1 << (dev->size-10),
dev->num_sects, 1 << (dev->sz_sect-10),
1 << dev->sz_page );
/* Status -- for now protection is all-or-nothing */
stat = asmi_status_rd();
printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n",
stat,
(stat & ASMI_STATUS_WIP) ? 1 : 0,
(stat & ASMI_STATUS_WEL) ? 1 : 0,
(stat & dev->prot_mask) ? "on" : "off" );
/* Configuration */
tmp = asmi_cfgsz ();
if (tmp) {
printf ("config: 0x%06x (%d) bytes\n", tmp, tmp );
} else {
printf ("config: unknown\n" );
}
/* Sector info */
for (i=0; i<dev->num_sects; i++) {
erased = asmi_sect_erased (i, &tmp, dev);
printf (" %d: %06x ",
i, i*(1<<dev->sz_sect) );
if (erased)
printf ("erased\n");
else
printf ("data @ 0x%06x\n", tmp);
}
return;
}
static
void do_asmi_erase (struct asmi_devinfo_t *dev, int argc, char *argv[])
{
unsigned start,end;
if ((argc < 3) || (argc > 4)) {
printf ("USAGE: asmi erase sect [end]\n");
return;
}
if ((asmi_status_rd() & dev->prot_mask) != 0) {
printf ( "asmi: device protected.\n");
return;
}
start = simple_strtoul (argv[2], NULL, 10);
if (argc > 3)
end = simple_strtoul (argv[3], NULL, 10);
else
end = start;
if ((start >= dev->num_sects) || (start > end)) {
printf ("asmi: invalid sector range: [%d:%d]\n",
start, end );
return;
}
asmi_erase (start, end);
return;
}
static
void do_asmi_protect (struct asmi_devinfo_t *dev, int argc, char *argv[])
{
unsigned char stat;
/* For now protection is all-or-nothing to keep things
* simple. The protection bits don't map in a linear
* fashion ... and we would rather protect the bottom
* of the device since it contains the config data and
* leave the top unprotected for app use. But unfortunately
* protection works from top-to-bottom so it does
* really help very much from a software app point-of-view.
*/
if (argc < 3) {
printf ("USAGE: asmi protect on | off\n");
return;
}
if (!dev)
return;
/* Protection on/off is just a matter of setting/clearing
* all protection bits in the status register.
*/
stat = asmi_status_rd ();
if (strcmp ("on", argv[2]) == 0) {
stat |= dev->prot_mask;
} else if (strcmp ("off", argv[2]) == 0 ) {
stat &= ~dev->prot_mask;
} else {
printf ("asmi: unknown protection: %s\n", argv[2]);
return;
}
asmi_status_wr (stat);
return;
}
static
void do_asmi_read (struct asmi_devinfo_t *dev, int argc, char *argv[])
{
ulong addr,off,cnt;
ulong sz;
if (argc < 5) {
printf ("USAGE: asmi read addr offset count\n");
return;
}
sz = 1 << dev->size;
addr = simple_strtoul (argv[2], NULL, 16);
off = simple_strtoul (argv[3], NULL, 16);
cnt = simple_strtoul (argv[4], NULL, 16);
if (off > sz) {
printf ("offset is greater than device size"
"... aborting.\n");
return;
}
if ((off + cnt) > sz) {
printf ("request exceeds device size"
"... truncating.\n");
cnt = sz - off;
}
printf ("asmi: read %08lx <- %06lx (0x%lx bytes)\n",
addr, off, cnt);
asmi_read (addr, off, cnt);
return;
}
static
void do_asmi_write (struct asmi_devinfo_t *dev, int argc, char *argv[])
{
ulong addr,off,cnt;
ulong sz;
ulong err;
if (argc < 5) {
printf ("USAGE: asmi write addr offset count\n");
return;
}
if ((asmi_status_rd() & dev->prot_mask) != 0) {
printf ( "asmi: device protected.\n");
return;
}
sz = 1 << dev->size;
addr = simple_strtoul (argv[2], NULL, 16);
off = simple_strtoul (argv[3], NULL, 16);
cnt = simple_strtoul (argv[4], NULL, 16);
if (off > sz) {
printf ("offset is greater than device size"
"... aborting.\n");
return;
}
if ((off + cnt) > sz) {
printf ("request exceeds device size"
"... truncating.\n");
cnt = sz - off;
}
printf ("asmi: write %08lx -> %06lx (0x%lx bytes)\n",
addr, off, cnt);
asmi_write (addr, off, cnt);
if (asmi_verify (addr, off, cnt, &err) != 0)
printf ("asmi: write error at offset %06lx\n", err);
return;
}
static
void do_asmi_verify (struct asmi_devinfo_t *dev, int argc, char *argv[])
{
ulong addr,off,cnt;
ulong sz;
ulong err;
if (argc < 5) {
printf ("USAGE: asmi verify addr offset count\n");
return;
}
sz = 1 << dev->size;
addr = simple_strtoul (argv[2], NULL, 16);
off = simple_strtoul (argv[3], NULL, 16);
cnt = simple_strtoul (argv[4], NULL, 16);
if (off > sz) {
printf ("offset is greater than device size"
"... aborting.\n");
return;
}
if ((off + cnt) > sz) {
printf ("request exceeds device size"
"... truncating.\n");
cnt = sz - off;
}
printf ("asmi: verify %08lx -> %06lx (0x%lx bytes)\n",
addr, off, cnt);
if (asmi_verify (addr, off, cnt, &err) != 0)
printf ("asmi: verify error at offset %06lx\n", err);
return;
}
/*-----------------------------------------------------------------------*/
int do_asmi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int len;
struct asmi_devinfo_t *dev = asmi_dev_find ();
if (argc < 2) {
printf ("Usage:%s", LONG_HELP);
return (0);
}
if (!dev) {
printf ("asmi: device not found.\n");
return (0);
}
len = strlen (argv[1]);
if (strncmp ("info", argv[1], len) == 0) {
do_asmi_info ( dev, argc, argv);
} else if (strncmp ("erase", argv[1], len) == 0) {
do_asmi_erase (dev, argc, argv);
} else if (strncmp ("protect", argv[1], len) == 0) {
do_asmi_protect (dev, argc, argv);
} else if (strncmp ("read", argv[1], len) == 0) {
do_asmi_read (dev, argc, argv);
} else if (strncmp ("write", argv[1], len) == 0) {
do_asmi_write (dev, argc, argv);
} else if (strncmp ("verify", argv[1], len) == 0) {
do_asmi_verify (dev, argc, argv);
} else {
printf ("asmi: unknown operation: %s\n", argv[1]);
}
return (0);
}
/*-----------------------------------------------------------------------*/
U_BOOT_CMD( asmi, 5, 0, do_asmi, SHORT_HELP, LONG_HELP );
#endif /* CONFIG_NIOS_ASMI */

24
arch/nios/cpu/config.mk
View file

@ -1,24 +0,0 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS +=

78
arch/nios/cpu/cpu.c
View file

@ -1,78 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <nios.h>
int checkcpu (void)
{
unsigned val;
unsigned rev_major;
unsigned rev_minor;
short nregs, hi_limit, lo_limit;
/* Get cpu version info */
val = rdctl (CTL_CPU_ID);
puts ("CPU: ");
printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 ");
rev_major = (val>>12) & 0x07;
rev_minor = (val>>4) & 0x0ff;
printf ("Rev. %d.%d (0x%04x)", rev_major, rev_minor,
val & 0xffff);
if (rev_major == 0x08)
printf (" [OpenCore (R) Plus]");
printf ("\n");
/* Check register file */
val = rdctl (CTL_WVALID);
lo_limit = val & 0x01f;
hi_limit = (val>>5) & 0x1f;
nregs = (hi_limit + 2) * 16;
printf ("Reg file size: %d LO_LIMIT/HI_LIMIT: %d/%d\n",
nregs, lo_limit, hi_limit);
return (0);
}
int do_reset (void)
{
/* trap 0 does the trick ... at least with the OCI debug
* present -- haven't tested without it yet (stm).
*/
disable_interrupts ();
ipri (1);
asm volatile ("trap 0\n");
/* No return ;-) */
return(0);
}
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
}
#endif /* CONFIG_WATCHDOG */

196
arch/nios/cpu/interrupts.c
View file

@ -1,196 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <nios.h>
#include <nios-io.h>
#include <asm/ptrace.h>
#include <common.h>
#include <command.h>
#include <watchdog.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
/****************************************************************************/
struct irq_action {
interrupt_handler_t *handler;
void *arg;
int count;
};
static struct irq_action irq_vecs[64];
/*************************************************************************/
volatile ulong timestamp = 0;
void reset_timer (void)
{
timestamp = 0;
}
ulong get_timer (ulong base)
{
WATCHDOG_RESET ();
return (timestamp - base);
}
void set_timer (ulong t)
{
timestamp = t;
}
/* The board must handle this interrupt if a timer is not
* provided.
*/
#if defined(CONFIG_SYS_NIOS_TMRBASE)
void timer_interrupt (struct pt_regs *regs)
{
/* Interrupt is cleared by writing anything to the
* status register.
*/
nios_timer_t *tmr = (nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
tmr->status = 0;
timestamp += CONFIG_SYS_NIOS_TMRMS;
#ifdef CONFIG_STATUS_LED
status_led_tick(timestamp);
#endif
}
#endif
/*************************************************************************/
int disable_interrupts (void)
{
int val = 0;
/* Writing anything to CLR_IE disables interrupts */
val = rdctl (CTL_STATUS);
wrctl (CTL_CLR_IE, 0);
return (val & STATUS_IE);
}
void enable_interrupts( void )
{
/* Writing anything SET_IE enables interrupts */
wrctl (CTL_SET_IE, 0);
}
void external_interrupt (struct pt_regs *regs)
{
unsigned vec;
vec = (regs->status & STATUS_IPRI) >> 9; /* ipri */
irq_vecs[vec].count++;
if (irq_vecs[vec].handler != NULL) {
(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
} else {
/* A sad side-effect of masking a bogus interrupt is
* that lower priority interrupts will also be disabled.
* This is probably not what we want ... so hang insted.
*/
printf ("Unhandled interrupt: 0x%x\n", vec);
disable_interrupts ();
hang ();
}
}
/*************************************************************************/
int interrupt_init (void)
{
int vec;
#if defined(CONFIG_SYS_NIOS_TMRBASE)
nios_timer_t *tmr = (nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
tmr->control &= ~NIOS_TIMER_ITO;
tmr->control |= NIOS_TIMER_STOP;
#if defined(CONFIG_SYS_NIOS_TMRCNT)
tmr->periodl = CONFIG_SYS_NIOS_TMRCNT & 0xffff;
tmr->periodh = (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff;
#endif
#endif
for (vec=0; vec<64; vec++ ) {
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
irq_vecs[vec].count = 0;
}
/* Need timus interruptus -- start the lopri timer */
#if defined(CONFIG_SYS_NIOS_TMRBASE)
tmr->control |= ( NIOS_TIMER_ITO |
NIOS_TIMER_CONT |
NIOS_TIMER_START );
ipri (CONFIG_SYS_NIOS_TMRIRQ + 1);
#endif
enable_interrupts ();
return (0);
}
void irq_install_handler (int vec, interrupt_handler_t *handler, void *arg)
{
struct irq_action *irqa = irq_vecs;
int i = vec;
int flag;
if (irqa[i].handler != NULL) {
printf ("Interrupt vector %d: handler 0x%x "
"replacing 0x%x\n",
vec, (uint)handler, (uint)irqa[i].handler);
}
flag = disable_interrupts ();
irqa[i].handler = handler;
irqa[i].arg = arg;
if (flag )
enable_interrupts ();
}
/*************************************************************************/
#if defined(CONFIG_CMD_IRQ)
int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int vec;
printf ("\nInterrupt-Information:\n");
printf ("Nr Routine Arg Count\n");
for (vec=0; vec<64; vec++) {
if (irq_vecs[vec].handler != NULL) {
printf ("%02d %08lx %08lx %d\n",
vec,
(ulong)irq_vecs[vec].handler<<1,
(ulong)irq_vecs[vec].arg,
irq_vecs[vec].count);
}
}
return (0);
}
#endif

135
arch/nios/cpu/serial.c
View file

@ -1,135 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <nios-io.h>
DECLARE_GLOBAL_DATA_PTR;
/*------------------------------------------------------------------
* JTAG acts as the serial port
*-----------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
void serial_setbrg( void ){ return; }
int serial_init( void ) { return(0);}
void serial_putc (char c)
{
while ((jtag->txcntl & NIOS_JTAG_TRDY) != 0)
WATCHDOG_RESET ();
jtag->txcntl = NIOS_JTAG_TRDY | (unsigned char)c;
}
void serial_puts (const char *s)
{
while (*s != 0)
serial_putc (*s++);
}
int serial_tstc (void)
{
return (jtag->rxcntl & NIOS_JTAG_RRDY);
}
int serial_getc (void)
{
int c;
while (serial_tstc() == 0)
WATCHDOG_RESET ();
c = jtag->rxcntl & 0x0ff;
jtag->rxcntl = 0;
return (c);
}
/*------------------------------------------------------------------
* UART the serial port
*-----------------------------------------------------------------*/
#else
static nios_uart_t *uart = (nios_uart_t *)CONFIG_SYS_NIOS_CONSOLE;
#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
/* Everything's already setup for fixed-baud PTF
* assignment
*/
void serial_setbrg (void){ return; }
int serial_init (void) { return (0);}
#else
void serial_setbrg (void)
{
unsigned div;
div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
uart->divisor = div;
return;
}
int serial_init (void)
{
serial_setbrg ();
return (0);
}
#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
/*-----------------------------------------------------------------------
* UART CONSOLE
*---------------------------------------------------------------------*/
void serial_putc (char c)
{
if (c == '\n')
serial_putc ('\r');
while ((uart->status & NIOS_UART_TRDY) == 0)
WATCHDOG_RESET ();
uart->txdata = (unsigned char)c;
}
void serial_puts (const char *s)
{
while (*s != 0) {
serial_putc (*s++);
}
}
int serial_tstc (void)
{
return (uart->status & NIOS_UART_RRDY);
}
int serial_getc (void)
{
while (serial_tstc () == 0)
WATCHDOG_RESET ();
return( uart->rxdata & 0x00ff );
}
#endif /* CONFIG_JTAG_CONSOLE */

195
arch/nios/cpu/spi.c
View file

@ -1,195 +0,0 @@
/*
* (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/ctype.h>
#if defined(CONFIG_NIOS_SPI)
#include <nios-io.h>
#include <spi.h>
#if !defined(CONFIG_SYS_NIOS_SPIBASE)
#error "*** CONFIG_SYS_NIOS_SPIBASE not defined ***"
#endif
#if !defined(CONFIG_SYS_NIOS_SPIBITS)
#error "*** CONFIG_SYS_NIOS_SPIBITS not defined ***"
#endif
#if (CONFIG_SYS_NIOS_SPIBITS != 8) && (CONFIG_SYS_NIOS_SPIBITS != 16)
#error "*** CONFIG_SYS_NIOS_SPIBITS should be either 8 or 16 ***"
#endif
static nios_spi_t *spi = (nios_spi_t *)CONFIG_SYS_NIOS_SPIBASE;
/* Warning:
* You cannot enable DEBUG for early system initalization, i. e. when
* this driver is used to read environment parameters like "baudrate"
* from EEPROM which are used to initialize the serial port which is
* needed to print the debug messages...
*/
#undef DEBUG
#ifdef DEBUG
#define DPRINT(a) printf a;
/* -----------------------------------------------
* Helper functions to peek into tx and rx buffers
* ----------------------------------------------- */
static const char * const hex_digit = "0123456789ABCDEF";
static char quickhex (int i)
{
return hex_digit[i];
}
static void memdump (const void *pv, int num)
{
int i;
const unsigned char *pc = (const unsigned char *) pv;
for (i = 0; i < num; i++)
printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
printf ("\t");
for (i = 0; i < num; i++)
printf ("%c", isprint (pc[i]) ? pc[i] : '.');
printf ("\n");
}
#else /* !DEBUG */
#define DPRINT(a)
#define memdump(p,n)
#endif /* DEBUG */
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct spi_slave *slave;
if (!spi_cs_is_valid(bus, cs))
return NULL;
slave = malloc(sizeof(struct spi_slave));
if (!slave)
return NULL;
slave->bus = bus;
slave->cs = cs;
/* TODO: Add support for different modes and speeds */
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
free(slave);
}
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
/*
* SPI transfer:
*
* See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
* for more informations.
*/
int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout,
void *din, unsigned long flags)
{
const u8 *txd = dout;
u8 *rxd = din;
int j;
DPRINT(("spi_xfer: slave %u:%u dout %08X din %08X bitlen %d\n",
slave->bus, slave->cs, *(uint *)dout, *(uint *)din, bitlen));
memdump(dout, (bitlen + 7) / 8);
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
if (!(flags & SPI_XFER_END) || bitlen > CONFIG_SYS_NIOS_SPIBITS) {
/* leave chip select active */
spi->control |= NIOS_SPI_SSO;
}
for ( j = 0; /* count each byte in */
j < ((bitlen + 7) / 8); /* dout[] and din[] */
#if (CONFIG_SYS_NIOS_SPIBITS == 8)
j++) {
while ((spi->status & NIOS_SPI_TRDY) == 0)
;
spi->txdata = (unsigned)(txd[j]);
while ((spi->status & NIOS_SPI_RRDY) == 0)
;
rxd[j] = (unsigned char)(spi->rxdata & 0xff);
#elif (CONFIG_SYS_NIOS_SPIBITS == 16)
j++, j++) {
while ((spi->status & NIOS_SPI_TRDY) == 0)
;
if ((j+1) < ((bitlen + 7) / 8))
spi->txdata = (unsigned)((txd[j] << 8) | txd[j+1]);
else
spi->txdata = (unsigned)(txd[j] << 8);
while ((spi->status & NIOS_SPI_RRDY) == 0)
;
rxd[j] = (unsigned char)((spi->rxdata >> 8) & 0xff);
if ((j+1) < ((bitlen + 7) / 8))
rxd[j+1] = (unsigned char)(spi->rxdata & 0xff);
#else
#error "*** unsupported value of CONFIG_SYS_NIOS_SPIBITS ***"
#endif
}
if (bitlen > CONFIG_SYS_NIOS_SPIBITS && (flags & SPI_XFER_END)) {
spi->control &= ~NIOS_SPI_SSO;
}
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
memdump(din, (bitlen + 7) / 8);
return 0;
}
#endif /* CONFIG_NIOS_SPI */

238
arch/nios/cpu/start.S
View file

@ -1,238 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <timestamp.h>
#include <version.h>
#if !defined(CONFIG_IDENT_STRING)
#define CONFIG_IDENT_STRING ""
#endif
#define STATUS_INIT 0x8600 /* IE=1, IPRI=2 */
/*************************************************************************
* RESTART
************************************************************************/
.text
.global _start
_start:
bsr 0f
nop
.long _start
/* GERMS -- The "standard-32" configuration GERMS monitor looks
* for the string "Nios" at flash_base + 0xc (actually it only
* tests for 'N', 'i'). You can leave support for this in place
* as it's only a few words.
*/
. = _start + 0x000c
.string "Nios"
.align 4
0:
/*
* Early setup -- set cwp = HI_LIMIT, IPRI = 2, IE = 1 to
* enable underflow exceptions. Disable cache.
* NOTE: %o7 has return addr -- save in %g7 use later.
*/
mov %g7, %o7
pfx 2 /* WVALID */
rdctl %g0
lsri %g0, 1
pfx %hi(STATUS_INIT)
or %g0, %lo(STATUS_INIT)
wrctl %g0 /* update status */
nop
/*
* STACK
*/
pfx %hi(CONFIG_SYS_INIT_SP)
movi %sp, %lo(CONFIG_SYS_INIT_SP)
pfx %xhi(CONFIG_SYS_INIT_SP)
movhi %sp, %xlo(CONFIG_SYS_INIT_SP)
mov %fp, %sp
pfx %hi(4*16)
subi %sp, %lo(4*16) /* Space for reg window mgmt */
/*
* RELOCATE -- %g7 has return addr from bsr at _start.
*/
pfx %hi(__u_boot_cmd_end)
movi %g5, %lo(__u_boot_cmd_end)
pfx %xhi(__u_boot_cmd_end)
movhi %g5, %xlo(__u_boot_cmd_end) /* %g5 <- end address */
lsli %g7, 1 /* mem = retaddr << 1 */
mov %g6, %g7
subi %g6, 4 /* %g6 <- src addr */
ld %g7, [%g7] /* %g7 <- dst addr */
/* No need to move text sections if we're already located
* at the proper address.
*/
cmp %g7, %g6
ifs cc_z
br reloc
nop /* delay slot */
1: cmp %g7, %g5
skps cc_nz
br 2f
nop /* delay slot */
ld %g0, [%g6]
addi %g6, 4 /* src++ */
st [%g7], %g0
addi %g7, 4 /* dst++ */
br 1b
nop /* delay slot */
2:
/*
* Jump to relocation address
*/
pfx %hi(reloc@h)
movi %g0, %lo(reloc@h)
pfx %xhi(reloc@h)
movhi %g0, %xlo(reloc@h)
jmp %g0
nop /* delay slot */
reloc:
/*
* CLEAR BSS
*/
pfx %hi(__bss_end)
movi %g5, %lo(__bss_end)
pfx %xhi(__bss_end)
movhi %g5, %xlo(__bss_end) /* %g5 <- end address */
pfx %hi(__bss_start)
movi %g7, %lo(__bss_start)
pfx %xhi(__bss_start)
movhi %g7, %xlo(__bss_start) /* %g7 <- end address */
movi %g0, 0
3: cmp %g7, %g5
skps cc_nz
br 4f
nop /* delay slot */
st [%g7], %g0
addi %g7, 4 /* (delay slot) dst++ */
br 3b
nop /* delay slot */
4:
/*
* INIT VECTOR TABLE
*/
pfx %hi(CONFIG_SYS_VECT_BASE)
movi %g0, %lo(CONFIG_SYS_VECT_BASE)
pfx %xhi(CONFIG_SYS_VECT_BASE)
movhi %g0, %xlo(CONFIG_SYS_VECT_BASE) /* dst */
mov %l0, %g0
pfx %hi(_vectors)
movi %g1, %lo(_vectors)
pfx %xhi(_vectors)
movhi %g1, %xlo(_vectors) /* src */
bgen %g2, 6 /* cnt = 64 */
ldp %g3, [%l0, 3] /* bkpt vector */
ldp %g4, [%l0, 4] /* single step vector */
5: ld %g7, [%g1]
addi %g1, 4 /* src++ */
st [%g0], %g7
addi %g0, 4 /* dst++ */
subi %g2, 1 /* cnt-- */
ifrnz %g2
br 5b
nop /* delay slot */
#if defined(CONFIG_ROM_STUBS)
/* Restore the breakpoint and single step exception
* vectors to their original values.
*/
stp [%l0,3], %g3 /* breakpoint */
stp [%l0,4], %g4 /* single step */
#endif
/* For debug startup convenience ... software breakpoints
* set prior to this point may not succeed ;-)
*/
.global __start
__start:
/*
* Call board_init -- never returns
*/
pfx %hi(board_init@h)
movi %g1, %lo(board_init@h)
pfx %xhi(board_init@h)
movhi %g1, %xlo(board_init@h)
call %g1
nop /* Delaly slot */
/* NEVER RETURNS */
/*
* dly_clks -- Nios doesn't have a time/clk reference for simple
* delay loops, so we do our best by counting instruction cycles.
* A control register that counts system clock cycles would be
* a handy feature -- hint for Altera ;-)
*/
.globl dly_clks
/* Each loop is 4 instructions as delay slot is always
* executed. Each instruction is approximately 4 clocks
* (according to some lame info from Altera). So ...
* ... each loop is about 16 clocks.
*/
dly_clks:
lsri %o0, 4 /* cnt/16 */
8: skprnz %o0
br 9f
subi %o0, 1 /* cnt--, Delay slot */
br 8b
nop
9: lret
nop /* Delay slot */
.data
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"

582
arch/nios/cpu/traps.S
View file

@ -1,582 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
/*************************************************************************
* Register window underflow
*
* The register window underflow exception occurs whenever the lowest
* valid register window is in use (CWP=LO_LIMIT) and a save instruction
* is issued. The save moves CWP below LO_LIMIT, %sp is set as normal,
* then the exception is generated prior to executing the instruction
* after the save.
************************************************************************/
.text
.global _cwp_lolimit
.align 4
_cwp_lolimit:
/* Sixteen words are always allocated by the compiler in every
* procedure's stack frame, always starting at %sp, for saving
* 'in' and 'local' registers on a window overflow.
*
* Save the 'global' and 'in' regs on stack. They are restored
* at cwp = HI_LIMIT. The 'local' regs aren't in-use at this point.
*/
sts [%sp,0], %g0 /* Save 'global' regs*/
sts [%sp,1], %g1
sts [%sp,2], %g2
sts [%sp,3], %g3
sts [%sp,4], %g4
sts [%sp,5], %g5
sts [%sp,6], %g6
sts [%sp,7], %g7
sts [%sp,8], %i0 /* Save 'in' regs */
sts [%sp,9], %i1
sts [%sp,10], %i2
sts [%sp,11], %i3
sts [%sp,12], %i4
sts [%sp,13], %i5
sts [%sp,14], %i6
sts [%sp,15], %i7
/* Save current %sp and return address in a global so they are
* available at cwp = HI_LIMIT ... where the 'global'/'in' regs
* are restored. NOTE: %sp changes with cwp.
*/
mov %g7, %o7
mov %g6, %sp
/* Get LO_LIMIT/HI_LIMIT to know where to start & stop. Note: in
* the underflow exception, cwp is __NOT__ guaranteed to be zero.
* If the OCI debug module is enabled the reset value for LO_LIMIT
* is 2, not 1 -- so cwp can be 1 or 0.
*/
pfx 2 /* WVALID */
rdctl %g1
mov %g2, %g1
pfx 0
and %g1, 0x1f /* g1 <- LO_LIMIT */
lsri %g2, 5
pfx 0
and %g2,0x1f /* g2 <- HI_LIMIT */
/* Set istatus so cwp = HI_LIMIT after tret
*/
movi %g5, 0x1f
lsli %g5, 4
not %g5 /* mask to clr cwp */
pfx 1 /* istatus */
rdctl %g0
and %g0, %g5 /* clear cwp field */
mov %g4, %g2
lsli %g4, 4
or %g0, %g4 /* cwp = HI_LIMIT */
pfx 1
wrctl %g0 /* update istatus */
/* Now move up the register file, saving as we go. When loop
* is first entered, %g1 is at LO_LIMIT.
*/
0:
restore /* cwp++ */
sts [%sp,0], %l0 /* Save "local" regs*/
sts [%sp,1], %l1
sts [%sp,2], %l2
sts [%sp,3], %l3
sts [%sp,4], %l4
sts [%sp,5], %l5
sts [%sp,6], %l6
sts [%sp,7], %l7
sts [%sp,8], %i0 /* Save 'in' regs */
sts [%sp,9], %i1
sts [%sp,10], %i2
sts [%sp,11], %i3
sts [%sp,12], %i4
sts [%sp,13], %i5
sts [%sp,14], %i6
sts [%sp,15], %i7
cmp %g1, %g2 /* cwp == HI_LIMIT ? */
skps cc_ne /* if so, we're done */
br 1f
nop /* delay slot */
inc %g1 /* g1 <- cwp++ */
br 0b
nop /* delay slot */
/* At this point cwp = HI_LIMIT, so the global/in regs that were
* in place when the underflow occurred must be restored using
* the original stack pointer (saved in g6).
*/
1:
mov %o7, %g7 /* restore return addr */
mov %sp, %g6 /* Restore original sp */
lds %g0, [%sp,0] /* Restore 'global' regs*/
lds %g1, [%sp,1]
lds %g2, [%sp,2]
lds %g3, [%sp,3]
lds %g4, [%sp,4]
lds %g5, [%sp,5]
lds %g6, [%sp,6]
lds %g7, [%sp,7]
lds %i0, [%sp,8] /* Restore 'in' regs*/
lds %i1, [%sp,9]
lds %i2, [%sp,10]
lds %i3, [%sp,11]
lds %i4, [%sp,12]
lds %i5, [%sp,13]
lds %i6, [%sp,14]
lds %i7, [%sp,15]
tret %o7 /* All done */
/*************************************************************************
* Register window overflow
*
* The register window overflow exception occurs whenever the highest
* valid register window is in use (cwp = HI_LIMIT) and a restore
* instruction is issued. Control is transferred to the overflow handler
* before the instruction following restore is executed.
*
* When a register window overflow exception is taken, the exception
* handler sees cwp at HI_LIMIT.
************************************************************************/
.text
.global _cwp_hilimit
.align 4
_cwp_hilimit:
/* Save 'global'/'in' regs on the stack -- will restore when cwp
* is at LO_LIMIT. Locals don't need saving as they are going away.
*/
sts [%sp,0], %g0 /* Save "global" regs*/
sts [%sp,1], %g1
sts [%sp,2], %g2
sts [%sp,3], %g3
sts [%sp,4], %g4
sts [%sp,5], %g5
sts [%sp,6], %g6
sts [%sp,7], %g7
sts [%sp,8], %i0 /* Save 'in' regs */
sts [%sp,9], %i1
sts [%sp,10], %i2
sts [%sp,11], %i3
sts [%sp,12], %i4
sts [%sp,13], %i5
sts [%sp,14], %i6
sts [%sp,15], %i7
/* The current %sp must be available in global to restore regs
* saved on stack. Need return addr as well ;-)
*/
mov %g7, %o7
mov %g6, %sp
/* Get HI_LIMIT & LO_LIMIT
*/
pfx 2 /* WVALID */
rdctl %g1
mov %g2, %g1
pfx 0
and %g1, 0x1f /* g1 <- LO_LIMIT */
lsri %g2, 5
pfx 0
and %g2,0x1f /* g2 <- HI_LIMIT */
/* Set istatus so cwp = LO_LIMIT after tret
*/
movi %g5, 0x1f
lsli %g5, 4
not %g5 /* mask to clr cwp */
pfx 1 /* istatus */
rdctl %g0
and %g0, %g5 /* clear cwp field */
mov %g4, %g1 /* g4 <- LO_LIMIT */
lsli %g4, 4
or %g0, %g4 /* cwp = LO_LIMIT */
pfx 1
wrctl %g0 /* update istatus */
/* Move to cwp = LO_LIMIT-1 and restore 'in' regs.
*/
subi %g4,(1 << 4) /* g4 <- LO_LIMIT - 1 */
rdctl %g0
and %g0, %g5 /* clear cwp field */
or %g0, %g4 /* cwp = LO_LIMIT - 1 */
wrctl %g0 /* update status */
nop
mov %sp, %g6 /* Restore sp */
lds %i0, [%sp,8] /* Restore 'in' regs */
lds %i1, [%sp,9]
lds %i2, [%sp,10]
lds %i3, [%sp,11]
lds %i4, [%sp,12]
lds %i5, [%sp,13]
lds %i6, [%sp,14] /* sp in next window */
lds %i7, [%sp,15]
/* Starting at LO_LIMIT-1, move up the register file, restoring
* along the way.
*/
0:
restore /* cwp++ */
lds %l0, [%sp,0] /* Restore 'local' regs*/
lds %l1, [%sp,1]
lds %l2, [%sp,2]
lds %l3, [%sp,3]
lds %l4, [%sp,4]
lds %l5, [%sp,5]
lds %l6, [%sp,6]
lds %l7, [%sp,7]
lds %i0, [%sp,8] /* Restore 'in' regs */
lds %i1, [%sp,9]
lds %i2, [%sp,10]
lds %i3, [%sp,11]
lds %i4, [%sp,12]
lds %i5, [%sp,13]
lds %i6, [%sp,14] /* sp in next window */
lds %i7, [%sp,15]
cmp %g1, %g2 /* cwp == HI_LIMIT ? */
skps cc_ne /* if so, we're done */
br 1f
nop /* delay slot */
inc %g1 /* cwp++ */
br 0b
nop /* delay slot */
/* All windows have been updated at this point, but the globals
* still need to be restored. Go to cwp = LO_LIMIT-1 to get
* some registers to use.
*/
1:
rdctl %g0
and %g0, %g5 /* clear cwp field */
or %g0, %g4 /* cwp = LO_LIMIT - 1 */
wrctl %g0 /* update status */
nop
/* Now there are some registers available to use in restoring
* the globals.
*/
mov %sp, %g6
mov %o7, %g7
lds %g0, [%sp,0] /* Restore "global" regs*/
lds %g1, [%sp,1]
lds %g2, [%sp,2]
lds %g3, [%sp,3]
lds %g4, [%sp,4]
lds %g5, [%sp,5]
lds %g6, [%sp,6]
lds %g7, [%sp,7]
/* The tret moves istatus -> status. istatus was already set for
* cwp = LO_LIMIT.
*/
tret %o7 /* done */
/*************************************************************************
* Default exception handler
*
* The default handler passes control to external_interrupt(). So trap
* or hardware interrupt hanlders can be installed using the familiar
* irq_install_handler().
*
* Here, the stack is fixed-up and cwp is incremented prior to calling
* external_interrupt(). This lets the underflow and overflow handlers
* operate normally during the exception.
************************************************************************/
.text
.global _def_xhandler
.align 4
_def_xhandler:
/* Allocate some stack space: 16 words at %sp to accomodate
* a reg window underflow, 8 words to save interrupted task's
* 'out' regs (which are now the 'in' regs), 8 words to preserve
* the 'global' regs and 3 words to save the return address,
* status and istatus. istatus must be saved in the event an
* underflow occurs in a dispatched handler. status is saved so
* a handler can access it on stack.
*/
pfx %hi((16+16+3) * 4)
subi %fp, %lo((16+16+3) * 4)
mov %sp, %fp
/* Save the 'global' regs and the interrupted task's 'out' regs
* (our 'in' regs) along with the return addr, status & istatus.
* First 16 words are for underflow exception.
*/
rdctl %l0 /* status */
pfx 1 /* istatus */
rdctl %l1
sts [%sp,16+0], %g0 /* Save 'global' regs*/
sts [%sp,16+1], %g1
sts [%sp,16+2], %g2
sts [%sp,16+3], %g3
sts [%sp,16+4], %g4
sts [%sp,16+5], %g5
sts [%sp,16+6], %g6
sts [%sp,16+7], %g7
sts [%sp,16+8], %i0 /* Save 'in' regs */
sts [%sp,16+9], %i1
sts [%sp,16+10], %i2
sts [%sp,16+11], %i3
sts [%sp,16+12], %i4
sts [%sp,16+13], %i5
sts [%sp,16+14], %i6
sts [%sp,16+15], %i7
sts [%sp,16+16], %l0 /* status */
sts [%sp,16+17], %l1 /* istatus */
sts [%sp,16+18], %o7 /* return addr */
/* Move to cwp+1 ... this guarantees cwp is at or above LO_LIMIT.
* Need to set IPRI=3 and IE=1 to enable underflow exceptions.
* NOTE: only the 'out' regs have been saved ... can't touch
* the 'in' or 'local' here.
*/
restore /* cwp++ */
rdctl %o0 /* o0 <- status */
pfx %hi(0x7e00)
movi %o1, %lo(0x7e00)
not %o1
and %o0, %o1 /* clear IPRI */
pfx %hi(0x8600)
movi %o1, %lo(0x8600)
or %o0, %o1 /* IPRI=3, IE=1 */
wrctl %o0 /* o0 -> status */
nop
/* It's ok to call a C routine now since cwp >= LO_LIMIT,
* interrupt task's registers are/will be preserved, and
* underflow exceptions can be handled.
*/
pfx %hi(external_interrupt@h)
movi %o1, %lo(external_interrupt@h)
pfx %xhi(external_interrupt@h)
movhi %o1, %xlo(external_interrupt@h)
bgen %o0, 4+2 /* 16 * 4 */
add %o0, %sp /* Ptr to regs */
call %o1
nop
/* Move back to the exception register window, restore the 'out'
* registers, then return from exception.
*/
rdctl %o0 /* o0 <- status */
subi %o0, 16
wrctl %o0 /* cwp-- */
nop
mov %sp, %fp
lds %g0, [%sp,16+0] /* Restore 'global' regs*/
lds %g1, [%sp,16+1]
lds %g2, [%sp,16+2]
lds %g3, [%sp,16+3]
lds %g4, [%sp,16+4]
lds %g5, [%sp,16+5]
lds %g6, [%sp,16+6]
lds %g7, [%sp,16+7]
lds %i0, [%sp,16+8] /* Restore 'in' regs*/
lds %i1, [%sp,16+9]
lds %i2, [%sp,16+10]
lds %i3, [%sp,16+11]
lds %i4, [%sp,16+12]
lds %i5, [%sp,16+13]
lds %i6, [%sp,16+14]
lds %i7, [%sp,16+15]
lds %l0, [%sp,16+16] /* status */
lds %l1, [%sp,16+17] /* istatus */
lds %o7, [%sp,16+18] /* return addr */
pfx 1
wrctl %l1 /* restore istatus */
pfx %hi((16+16+3) * 4)
addi %sp, %lo((16+16+3) * 4)
mov %fp, %sp
tret %o7 /* Done */
/*************************************************************************
* Timebase Timer Interrupt -- This has identical structure to above,
* but calls timer_interrupt(). Doing it this way keeps things similar
* to other architectures (e.g. ppc).
************************************************************************/
.text
.global _timebase_int
.align 4
_timebase_int:
/* Allocate stack space.
*/
pfx %hi((16+16+3) * 4)
subi %fp, %lo((16+16+3) * 4)
mov %sp, %fp
/* Save the 'global' regs & 'out' regs (our 'in' regs)
*/
rdctl %l0 /* status */
pfx 1 /* istatus */
rdctl %l1
sts [%sp,16+0], %g0 /* Save 'global' regs*/
sts [%sp,16+1], %g1
sts [%sp,16+2], %g2
sts [%sp,16+3], %g3
sts [%sp,16+4], %g4
sts [%sp,16+5], %g5
sts [%sp,16+6], %g6
sts [%sp,16+7], %g7
sts [%sp,16+8], %i0 /* Save 'in' regs */
sts [%sp,16+9], %i1
sts [%sp,16+10], %i2
sts [%sp,16+11], %i3
sts [%sp,16+12], %i4
sts [%sp,16+13], %i5
sts [%sp,16+14], %i6
sts [%sp,16+15], %i7
sts [%sp,16+16], %l0 /* status */
sts [%sp,16+17], %l1 /* istatus */
sts [%sp,16+18], %o7 /* return addr */
/* Move to cwp+1.
*/
restore /* cwp++ */
rdctl %o0 /* o0 <- status */
pfx %hi(0x7e00)
movi %o1, %lo(0x7e00)
not %o1
and %o0, %o1 /* clear IPRI */
pfx %hi(0x8600)
movi %o1, %lo(0x8600)
or %o0, %o1 /* IPRI=3, IE=1 */
wrctl %o0 /* o0 -> status */
nop
/* Call timer_interrupt()
*/
pfx %hi(timer_interrupt@h)
movi %o1, %lo(timer_interrupt@h)
pfx %xhi(timer_interrupt@h)
movhi %o1, %xlo(timer_interrupt@h)
bgen %o0, 4+2 /* 16 * 4 */
add %o0, %sp /* Ptr to regs */
call %o1
nop
/* Move back to the exception register window, restore the 'out'
* registers, then return from exception.
*/
rdctl %o0 /* o0 <- status */
subi %o0, 16
wrctl %o0 /* cwp-- */
nop
mov %sp, %fp
lds %g0, [%sp,16+0] /* Restore 'global' regs*/
lds %g1, [%sp,16+1]
lds %g2, [%sp,16+2]
lds %g3, [%sp,16+3]
lds %g4, [%sp,16+4]
lds %g5, [%sp,16+5]
lds %g6, [%sp,16+6]
lds %g7, [%sp,16+7]
lds %i0, [%sp,16+8] /* Restore 'in' regs*/
lds %i1, [%sp,16+9]
lds %i2, [%sp,16+10]
lds %i3, [%sp,16+11]
lds %i4, [%sp,16+12]
lds %i5, [%sp,16+13]
lds %i6, [%sp,16+14]
lds %i7, [%sp,16+15]
lds %l0, [%sp,16+16] /* status */
lds %l1, [%sp,16+17] /* istatus */
lds %o7, [%sp,16+18] /* return addr */
pfx 1
wrctl %l1 /* restore istatus */
pfx %hi((16+16+3) * 4)
addi %sp, %lo((16+16+3) * 4)
mov %fp, %sp
tret %o7 /* Done */
/*************************************************************************
* GDB stubs
************************************************************************/
.text
.global _brkpt_hw_int, _brkpt_sw_int
.align 4
_brkpt_hw_int:
movi %l1, 9
pfx 3
wrctl %l1
pfx 4
wrctl %l1
_brkpt_sw_int:
movi %l1, 9
pfx 3
wrctl %l1
pfx 4
wrctl %l1
tret %o7

38
arch/nios/include/asm/bitops.h
View file

@ -1,38 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_NIOS_BITOPS_H_
#define _ASM_NIOS_BITOPS_H_
extern void set_bit(int nr, volatile void * a);
extern void clear_bit(int nr, volatile void * a);
extern int test_and_clear_bit(int nr, volatile void * a);
extern void change_bit(unsigned long nr, volatile void *addr);
extern int test_and_set_bit(int nr, volatile void * a);
extern int test_and_change_bit(int nr, volatile void * addr);
extern int test_bit(int nr, volatile void * a);
extern int ffs(int i);
#define PLATFORM_FFS
#endif /* _ASM_NIOS_BITOPS_H */

30
arch/nios/include/asm/byteorder.h
View file

@ -1,30 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_NIOS_BYTEORDER_H
#define __ASM_NIOS_BYTEORDER_H
#include <asm/types.h>
#include <linux/byteorder/little_endian.h>
#endif

1
arch/nios/include/asm/cache.h
View file

@ -1 +0,0 @@
/*FIXME: Implement this! */

27
arch/nios/include/asm/config.h
View file

@ -1,27 +0,0 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
/* Relocation to SDRAM works on all NIOS boards */
#define CONFIG_RELOC_FIXUP_WORKS
#endif

54
arch/nios/include/asm/global_data.h
View file

@ -1,54 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_NIOS_GLOBALDATA_H
#define __ASM_NIOS_GLOBALDATA_H
typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid */
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
unsigned long post_log_word; /* Record POST activities */
unsigned long post_init_f_time; /* When post_init_f started */
#endif
void **jt; /* Standalone app jump table */
} gd_t;
/* flags */
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7")
#endif /* __ASM_NIOS_GLOBALDATA_H */

141
arch/nios/include/asm/io.h
View file

@ -1,141 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_NIOS_IO_H_
#define __ASM_NIOS_IO_H_
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
#define readb(addr)\
({unsigned char val;\
asm volatile( " pfxio 0 \n"\
" ld %0, [%1] \n"\
" ext8d %0, %1 \n"\
:"=r"(val) : "r" (addr)); val;})
#define readw(addr)\
({unsigned short val;\
asm volatile( " pfxio 0 \n"\
" ld %0, [%1] \n"\
" ext16d %0, %1 \n"\
:"=r"(val) : "r" (addr)); val;})
#define readl(addr)\
({unsigned long val;\
asm volatile( " pfxio 0 \n"\
" ld %0, [%1] \n"\
:"=r"(val) : "r" (addr)); val;})
#define writeb(addr,val)\
asm volatile ( " fill8 %%r0, %1 \n"\
" st8d [%0], %%r0 \n"\
: : "r" (addr), "r" (val) : "r0")
#define writew(addr,val)\
asm volatile ( " fill16 %%r0, %1 \n"\
" st16d [%0], %%r0 \n"\
: : "r" (addr), "r" (val) : "r0")
#define writel(addr,val)\
asm volatile ( " st [%0], %1 \n"\
: : "r" (addr), "r" (val))
#define inb(addr) readb(addr)
#define inw(addr) readw(addr)
#define inl(addr) readl(addr)
#define outb(val,addr) writeb(addr,val)
#define outw(val,addr) writew(addr,val)
#define outl(val,addr) writel(addr,val)
static inline void insb (unsigned long port, void *dst, unsigned long count)
{
unsigned char *p = dst;
while (count--) *p++ = inb (port);
}
static inline void insw (unsigned long port, void *dst, unsigned long count)
{
unsigned short *p = dst;
while (count--) *p++ = inw (port);
}
static inline void insl (unsigned long port, void *dst, unsigned long count)
{
unsigned long *p = dst;
while (count--) *p++ = inl (port);
}
static inline void outsb (unsigned long port, const void *src, unsigned long count)
{
const unsigned char *p = src;
while (count--) outb (*p++, port);
}
static inline void outsw (unsigned long port, const void *src, unsigned long count)
{
const unsigned short *p = src;
while (count--) outw (*p++, port);
}
static inline void outsl (unsigned long port, const void *src, unsigned long count)
{
const unsigned long *p = src;
while (count--) outl (*p++, port);
}
static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
static inline phys_addr_t virt_to_phys(void * vaddr)
{
return (phys_addr_t)(vaddr);
}
#endif /* __ASM_NIOS_IO_H_ */

63
arch/nios/include/asm/posix_types.h
View file

@ -1,63 +0,0 @@
#ifndef __ASM_NIOS_POSIX_TYPES_H
#define __ASM_NIOS_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned short __kernel_dev_t;
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned long __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
#undef __FD_CLR
#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
#undef __FD_ISSET
#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
#endif

1
arch/nios/include/asm/processor.h
View file

@ -1 +0,0 @@
/* FIXME: Implement this! */

28
arch/nios/include/asm/psr.h
View file

@ -1,28 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _NIOS_PSR_H
#define _NIOS_PSR_H
#endif /* _NIOS_PSR_H */

36
arch/nios/include/asm/ptrace.h
View file

@ -1,36 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _NIOS_PTRACE_H
#define _NIOS_PTRACE_H
struct pt_regs {
unsigned global[8];
unsigned in[8];
unsigned status;
unsigned istatus;
unsigned retaddr;
};
#endif /* _NIOS_PTRACE_H */

132
arch/nios/include/asm/status_led.h
View file

@ -1,132 +0,0 @@
/*
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* asm-nios/status_led.h
*
* NIOS PIO based status led support functions
*/
#ifndef __ASM_STATUS_LED_H__
#define __ASM_STATUS_LED_H__
#include <nios-io.h>
/* led_id_t is unsigned int mask */
typedef unsigned int led_id_t;
#ifdef STATUS_LED_WRONLY /* emulate read access */
static led_id_t __led_portval = 0;
#endif
static inline void __led_init (led_id_t mask, int state)
{
nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
#ifdef STATUS_LED_WRONLY /* emulate read access */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
__led_portval &= ~mask;
else
__led_portval |= mask;
#else
if (state == STATUS_LED_ON)
__led_portval |= mask;
else
__led_portval &= ~mask;
#endif
piop->data = __led_portval;
#else /* !STATUS_LED_WRONLY */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
piop->data &= ~mask;
else
piop->data |= mask;
#else
if (state == STATUS_LED_ON)
piop->data |= mask;
else
piop->data &= ~mask;
#endif
piop->direction |= mask;
#endif /* STATUS_LED_WRONLY */
}
static inline void __led_toggle (led_id_t mask)
{
nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
#ifdef STATUS_LED_WRONLY /* emulate read access */
__led_portval ^= mask;
piop->data = __led_portval;
#else /* !STATUS_LED_WRONLY */
piop->data ^= mask;
#endif /* STATUS_LED_WRONLY */
}
static inline void __led_set (led_id_t mask, int state)
{
nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
#ifdef STATUS_LED_WRONLY /* emulate read access */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
__led_portval &= ~mask;
else
__led_portval |= mask;
#else
if (state == STATUS_LED_ON)
__led_portval |= mask;
else
__led_portval &= ~mask;
#endif
piop->data = __led_portval;
#else /* !STATUS_LED_WRONLY */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
piop->data &= ~mask;
else
piop->data |= mask;
#else
if (state == STATUS_LED_ON)
piop->data |= mask;
else
piop->data &= ~mask;
#endif
#endif /* STATUS_LED_WRONLY */
}
#endif /* __ASM_STATUS_LED_H__ */

25
arch/nios/include/asm/string.h
View file

@ -1,25 +0,0 @@
#ifndef __ASM_NIOS_STRING_H
#define __ASM_NIOS_STRING_H
#undef __HAVE_ARCH_STRRCHR
extern char * strrchr(const char * s, int c);
#undef __HAVE_ARCH_STRCHR
extern char * strchr(const char * s, int c);
#undef __HAVE_ARCH_MEMCPY
extern void * memcpy(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMMOVE
extern void * memmove(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMCHR
extern void * memchr(const void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMSET
extern void * memset(void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMZERO
extern void memzero(void *ptr, __kernel_size_t n);
#endif

4
arch/nios/include/asm/system.h
View file

@ -1,4 +0,0 @@
#ifndef _ASM_NIOS_SYSTEM_H_
#define _ASM_NIOS_SYSTEM_H_
#endif /* _ASM_NIOS_SYSTEM_H */

60
arch/nios/include/asm/types.h
View file

@ -1,60 +0,0 @@
#ifndef _NIOS_TYPES_H
#define _NIOS_TYPES_H
/*
* This file is never included by application software unless
* explicitly requested (e.g., via linux/types.h) in which case the
* application is Linux specific so (user-) name space pollution is
* not a major issue. However, for interoperability, libraries still
* need to be careful to avoid a name clashes.
*/
typedef unsigned short umode_t;
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__)
__extension__ typedef __signed__ long long __s64;
__extension__ typedef unsigned long long __u64;
#endif
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
#define BITS_PER_LONG 32
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif /* __KERNEL__ */
#endif /* _NIOS_TYPES_H */

48
arch/nios/include/asm/u-boot.h
View file

@ -1,48 +0,0 @@
/*
* (C) Copyright 2003
* Psyent Corporation
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef _U_BOOT_H_
#define _U_BOOT_H_
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned long bi_ip_addr; /* IP Address */
unsigned long bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* _U_BOOT_H_ */

50
arch/nios/lib/Makefile
View file

@ -1,50 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(ARCH).a
SOBJS-y +=
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-y += cache.o
COBJS-y += divmod.o
COBJS-y += mult.o
COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

168
arch/nios/lib/board.c
View file

@ -1,168 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <stdio_dev.h>
#include <watchdog.h>
#include <malloc.h>
#include <net.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
* requirements are just _too_ different. To get rid of the resulting
* mess of board dependend #ifdef'ed code we now make the whole
* initialization sequence configurable to the user.
*
* The requirements for any new initalization function is simple: it
* receives a pointer to the "global data" structure as it's only
* argument, and returns an integer return code, where 0 means
* "continue" and != 0 means "fatal error, hang the system".
*/
typedef int (init_fnc_t) (void);
/************************************************************************
* Initialization sequence *
***********************************************************************/
init_fnc_t *init_sequence[] = {
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f, /* Call board-specific init code early.*/
#endif
env_init,
serial_init,
console_init_f,
display_options,
checkcpu,
checkboard,
NULL, /* Terminate this list */
};
/***********************************************************************/
void board_init (void)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
char *s, *e;
int i;
/* Pointer is writable since we allocated a register for it.
* Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address.
*/
gd = (gd_t *)CONFIG_SYS_GBL_DATA_OFFSET;
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset( gd, 0, CONFIG_SYS_GBL_DATA_SIZE );
gd->bd = (bd_t *)(gd+1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
bd = gd->bd;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET ();
if ((*init_fnc_ptr) () != 0) {
hang ();
}
}
WATCHDOG_RESET ();
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
WATCHDOG_RESET ();
bd->bi_flashsize = flash_init();
WATCHDOG_RESET ();
env_relocate();
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
WATCHDOG_RESET ();
stdio_init();
jumptable_init();
console_init_r();
/*
*/
WATCHDOG_RESET ();
interrupt_init ();
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
main_loop ();
}
}
/***********************************************************************/
void hang (void)
{
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
#endif
puts("### ERROR ### Please reset board ###\n");
for (;;);
}
unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[])
{
/*
* x86 does not use a dedicated register to pass the pointer
* to the global_data
*/
argv[-1] = (char *)gd;
return entry (argc, argv);
}

34
arch/nios/lib/bootm.c
View file

@ -1,34 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
/* FIXME: Once we find a stable version of uC-linux for nios
* we can get this working. ;-)
*
*/
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
return 1;
}

32
arch/nios/lib/cache.c
View file

@ -1,32 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
void flush_cache (ulong addr, ulong size)
{
/* Nios cache is write-thru -- nothing to do here.
*/
return;
}

101
arch/nios/lib/divmod.c
View file

@ -1,101 +0,0 @@
/*
* This file is part of GNU CC.
*
* GNU CC is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published
* by the Free Software Foundation; either version 2, or (at your
* option) any later version.
*
* GNU CC is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with GNU CC; see the file COPYING. If not, write
* to the Free Software Foundation, 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*/
#include "math.h"
USItype udivmodsi4 (USItype num, USItype den, word_type modwanted)
{
USItype bit = 1;
USItype res = 0;
while (den < num && bit && !(den & (1L << 31))) {
den <<= 1;
bit <<= 1;
}
while (bit) {
if (num >= den) {
num -= den;
res |= bit;
}
bit >>= 1;
den >>= 1;
}
if (modwanted)
return num;
return res;
}
SItype __divsi3 (SItype a, SItype b)
{
word_type neg = 0;
SItype res;
if (a < 0) {
a = -a;
neg = !neg;
}
if (b < 0) {
b = -b;
neg = !neg;
}
res = udivmodsi4 (a, b, 0);
if (neg)
res = -res;
return res;
}
SItype __modsi3 (SItype a, SItype b)
{
word_type neg = 0;
SItype res;
if (a < 0) {
a = -a;
neg = 1;
}
if (b < 0)
b = -b;
res = udivmodsi4 (a, b, 1);
if (neg)
res = -res;
return res;
}
SItype __udivsi3 (SItype a, SItype b)
{
return udivmodsi4 (a, b, 0);
}
SItype __umodsi3 (SItype a, SItype b)
{
return udivmodsi4 (a, b, 1);
}

16
arch/nios/lib/math.h
View file

@ -1,16 +0,0 @@
#define BITS_PER_UNIT 8
typedef int HItype __attribute__ ((mode (HI)));
typedef unsigned int UHItype __attribute__ ((mode (HI)));
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int word_type __attribute__ ((mode (__word__)));
struct SIstruct {HItype low, high;};
typedef union {
struct SIstruct s;
SItype ll;
} SIunion;

56
arch/nios/lib/mult.c
View file

@ -1,56 +0,0 @@
/*
* This file is part of GNU CC.
*
* GNU CC is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published
* by the Free Software Foundation; either version 2, or (at your
* option) any later version.
*
* GNU CC is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with GNU CC; see the file COPYING. If not, write
* to the Free Software Foundation, 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*/
#include <common.h>
#if !defined(CONFIG_SYS_NIOS_MULT_HW) && !defined(CONFIG_SYS_NIOS_MULT_MSTEP)
#include "math.h"
USItype __mulsi3 (USItype a, USItype b)
{
USItype c = 0;
while (a != 0) {
if (a & 1)
c += b;
a >>= 1;
b <<= 1;
}
return c;
}
UHItype __mulhi3 (UHItype a, UHItype b)
{
UHItype c = 0;
while (a != 0) {
if (a & 1)
c += b;
a >>= 1;
b <<= 1;
}
return c;
}
#endif /*!defined(CONFIG_SYS_NIOS_MULT_HW) && !defined(CONFIG_SYS_NIOS_MULT_MSTEP) */

38
arch/nios/lib/time.c
View file

@ -1,38 +0,0 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
extern void dly_clks( unsigned long ticks );
void __udelay(unsigned long usec)
{
/* The Nios core doesn't have a timebase, so we do our
* best for now and call a low-level loop that counts
* cpu clocks.
*/
unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec;
dly_clks (cnt);
}

4
arch/nios2/config.mk
View file

@ -24,9 +24,9 @@
CROSS_COMPILE ?= nios2-elf-
STANDALONE_LOAD_ADDR = 0x02000000 -L $(gcclibdir)
STANDALONE_LOAD_ADDR ?= 0x02000000
PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
PLATFORM_CPPFLAGS += -ffixed-r15 -G0
PLATFORM_CPPFLAGS += -G0
LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds

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