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imx: imx8mm_mx8menlo: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
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3 changed files with 1 additions and 12 deletions
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@ -12,15 +12,8 @@
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <spl.h>
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#include <spl.h>
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#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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/* Verdin UART_3, Console/Debug UART */
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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};
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@ -48,8 +41,6 @@ void board_early_init(void)
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set_wdog_reset(wdog);
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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init_uart_clk(1);
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init_uart_clk(1);
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setup_snvs();
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setup_snvs();
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@ -105,6 +105,7 @@ CONFIG_DM_PMIC_PFUZE100=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_SERIAL=y
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CONFIG_MXC_UART=y
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CONFIG_MXC_UART=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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@ -30,7 +30,4 @@
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"initrd_addr=0x43800000\0" \
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"initrd_addr=0x43800000\0" \
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"kernel_image=fitImage\0"
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"kernel_image=fitImage\0"
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#undef CONFIG_MXC_UART_BASE
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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#endif /* __IMX8MM_MX8MENLO_H */
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#endif /* __IMX8MM_MX8MENLO_H */
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