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https://github.com/AsahiLinux/u-boot
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drivers: spi: ti_qspi: prepare driver for DM conversion
Prepare driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
Mugunthan V N
Jagan Teki
parent
9c42558afb
commit
223091443c
1 changed files with 157 additions and 130 deletions
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@ -89,46 +89,14 @@ struct ti_qspi_regs {
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struct ti_qspi_priv {
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struct spi_slave slave;
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struct ti_qspi_regs *base;
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void *ctrl_mod_mmap;
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unsigned int mode;
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u32 cmd;
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u32 dc;
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};
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static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
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static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
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{
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return container_of(slave, struct ti_qspi_priv, slave);
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}
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static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
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{
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struct spi_slave *slave = &priv->slave;
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u32 memval = 0;
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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slave->memory_map = (void *)MMAP_START_ADDR_DRA;
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#else
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slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
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#endif
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#ifdef CONFIG_QSPI_QUAD_SUPPORT
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memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_8_BITS |
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QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS);
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slave->mode_rx = SPI_RX_QUAD;
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#else
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memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
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QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS;
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#endif
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writel(memval, &priv->base->setup0);
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}
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static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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uint clk_div;
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debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
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@ -152,132 +120,77 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
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writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* CS handled in xfer */
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return;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
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writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
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/* dummy readl to ensure bus sync */
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readl(&qslave->base->cmd);
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readl(&priv->base->cmd);
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}
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void spi_init(void)
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static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
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{
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/* nothing to do */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct ti_qspi_priv *priv;
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#ifdef CONFIG_AM43XX
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gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
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gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
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#endif
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priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
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if (!priv) {
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printf("SPI_error: Fail to allocate ti_qspi_priv\n");
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return NULL;
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}
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priv->base = (struct ti_qspi_regs *)QSPI_BASE;
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priv->mode = mode;
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ti_spi_set_speed(&priv->slave, max_hz);
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#ifdef CONFIG_TI_SPI_MMAP
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ti_spi_setup_spi_register(priv);
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#endif
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return &priv->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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free(priv);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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priv->dc = 0;
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if (priv->mode & SPI_CPHA)
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priv->dc |= QSPI_CKPHA(slave->cs);
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if (priv->mode & SPI_CPOL)
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priv->dc |= QSPI_CKPOL(slave->cs);
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if (priv->mode & SPI_CS_HIGH)
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priv->dc |= QSPI_CSPOL(slave->cs);
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writel(priv->dc, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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if (mode & SPI_CPHA)
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priv->dc |= QSPI_CKPHA(0);
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if (mode & SPI_CPOL)
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priv->dc |= QSPI_CKPOL(0);
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if (mode & SPI_CS_HIGH)
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priv->dc |= QSPI_CSPOL(0);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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writel(priv->dc, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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priv->dc <<= cs * 8;
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writel(priv->dc, &priv->base->dc);
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return 0;
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}
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static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
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{
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writel(0, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
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{
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u32 val;
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val = readl(ctrl_mod_mmap);
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if (enable)
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val |= MEM_CS(cs);
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else
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val &= MEM_CS_UNSELECT;
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writel(val, ctrl_mod_mmap);
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}
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static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags,
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u32 cs)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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uint words = bitlen >> 3; /* fixed 8-bit word length */
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const uchar *txp = dout;
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uchar *rxp = din;
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uint status;
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int timeout;
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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int val;
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#endif
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debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
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slave->bus, slave->cs, bitlen, words, flags);
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/* Setup mmap flags */
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if (flags & SPI_XFER_MMAP) {
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writel(MM_SWITCH, &priv->base->memswitch);
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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val = readl(CORE_CTRL_IO);
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val |= MEM_CS(slave->cs);
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writel(val, CORE_CTRL_IO);
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#endif
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
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return 0;
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} else if (flags & SPI_XFER_MMAP_END) {
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writel(~MM_SWITCH, &priv->base->memswitch);
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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val = readl(CORE_CTRL_IO);
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val &= MEM_CS_UNSELECT;
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writel(val, CORE_CTRL_IO);
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#endif
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
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return 0;
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}
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@ -292,7 +205,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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/* Setup command reg */
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priv->cmd = 0;
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priv->cmd |= QSPI_WLEN(8);
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priv->cmd |= QSPI_EN_CS(slave->cs);
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priv->cmd |= QSPI_EN_CS(cs);
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if (priv->mode & SPI_3WIRE)
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priv->cmd |= QSPI_3_PIN;
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priv->cmd |= 0xfff;
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@ -347,7 +260,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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/* Terminate frame */
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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ti_qspi_cs_deactivate(priv);
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return 0;
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}
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@ -374,3 +287,117 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
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*((unsigned int *)offset) += len;
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}
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#endif
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static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
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{
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return container_of(slave, struct ti_qspi_priv, slave);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* CS handled in xfer */
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return;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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ti_qspi_cs_deactivate(priv);
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}
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void spi_init(void)
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{
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/* nothing to do */
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}
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static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
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{
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u32 memval = 0;
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#ifdef CONFIG_QSPI_QUAD_SUPPORT
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struct spi_slave *slave = &priv->slave;
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memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_8_BITS |
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QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS);
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slave->mode_rx = SPI_RX_QUAD;
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#else
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memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
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QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS;
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#endif
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writel(memval, &priv->base->setup0);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct ti_qspi_priv *priv;
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#ifdef CONFIG_AM43XX
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gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
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gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
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#endif
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priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
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if (!priv) {
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printf("SPI_error: Fail to allocate ti_qspi_priv\n");
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return NULL;
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}
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priv->base = (struct ti_qspi_regs *)QSPI_BASE;
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priv->mode = mode;
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
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priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
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#else
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priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
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#endif
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ti_spi_set_speed(priv, max_hz);
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#ifdef CONFIG_TI_SPI_MMAP
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ti_spi_setup_spi_register(priv);
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#endif
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return &priv->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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free(priv);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
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__ti_qspi_set_mode(priv, priv->mode);
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return __ti_qspi_claim_bus(priv, priv->slave.cs);
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
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__ti_qspi_release_bus(priv);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
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priv->slave.bus, priv->slave.cs, bitlen, flags);
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return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
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}
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